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[thirdparty/kernel/stable.git] / arch / arm / mach-omap2 / omap_hwmod_54xx_data.c
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08e4830d
BC		 1/*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
08e4830d
BC		 23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_54xx.h"
33#include "cm2_54xx.h"
34#include "prm54xx.h"
35#include "prm-regbits-54xx.h"
36#include "i2c.h"
37#include "mmc.h"
38#include "wd_timer.h"
39
40/* Base offset for all OMAP5 interrupts external to MPUSS */
41#define OMAP54XX_IRQ_GIC_START 32
42
43/* Base offset for all OMAP5 dma requests */
44#define OMAP54XX_DMA_REQ_START 1
45
46
47/*
48 * IP blocks
49 */
50
51/*
52 * 'dmm' class
53 * instance(s): dmm
54 */
55static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
56 .name = "dmm",
57};
58
59/* dmm */
60static struct omap_hwmod omap54xx_dmm_hwmod = {
61 .name = "dmm",
62 .class = &omap54xx_dmm_hwmod_class,
63 .clkdm_name = "emif_clkdm",
64 .prcm = {
65 .omap4 = {
66 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
67 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
68 },
69 },
70};
71
72/*
73 * 'l3' class
74 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
75 */
76static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
77 .name = "l3",
78};
79
80/* l3_instr */
81static struct omap_hwmod omap54xx_l3_instr_hwmod = {
82 .name = "l3_instr",
83 .class = &omap54xx_l3_hwmod_class,
84 .clkdm_name = "l3instr_clkdm",
85 .prcm = {
86 .omap4 = {
87 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
88 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
89 .modulemode = MODULEMODE_HWCTRL,
90 },
91 },
92};
93
94/* l3_main_1 */
95static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
96 .name = "l3_main_1",
97 .class = &omap54xx_l3_hwmod_class,
98 .clkdm_name = "l3main1_clkdm",
99 .prcm = {
100 .omap4 = {
101 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
102 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
103 },
104 },
105};
106
107/* l3_main_2 */
108static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
109 .name = "l3_main_2",
110 .class = &omap54xx_l3_hwmod_class,
111 .clkdm_name = "l3main2_clkdm",
112 .prcm = {
113 .omap4 = {
114 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
115 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
116 },
117 },
118};
119
120/* l3_main_3 */
121static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
122 .name = "l3_main_3",
123 .class = &omap54xx_l3_hwmod_class,
124 .clkdm_name = "l3instr_clkdm",
125 .prcm = {
126 .omap4 = {
127 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
128 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
129 .modulemode = MODULEMODE_HWCTRL,
130 },
131 },
132};
133
134/*
135 * 'l4' class
136 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
137 */
138static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
139 .name = "l4",
140};
141
142/* l4_abe */
143static struct omap_hwmod omap54xx_l4_abe_hwmod = {
144 .name = "l4_abe",
145 .class = &omap54xx_l4_hwmod_class,
146 .clkdm_name = "abe_clkdm",
147 .prcm = {
148 .omap4 = {
149 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
150 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
151 },
152 },
153};
154
155/* l4_cfg */
156static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
157 .name = "l4_cfg",
158 .class = &omap54xx_l4_hwmod_class,
159 .clkdm_name = "l4cfg_clkdm",
160 .prcm = {
161 .omap4 = {
162 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
163 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
164 },
165 },
166};
167
168/* l4_per */
169static struct omap_hwmod omap54xx_l4_per_hwmod = {
170 .name = "l4_per",
171 .class = &omap54xx_l4_hwmod_class,
172 .clkdm_name = "l4per_clkdm",
173 .prcm = {
174 .omap4 = {
175 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
176 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
177 },
178 },
179};
180
181/* l4_wkup */
182static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
183 .name = "l4_wkup",
184 .class = &omap54xx_l4_hwmod_class,
185 .clkdm_name = "wkupaon_clkdm",
186 .prcm = {
187 .omap4 = {
188 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
189 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
190 },
191 },
192};
193
194/*
195 * 'mpu_bus' class
196 * instance(s): mpu_private
197 */
198static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
199 .name = "mpu_bus",
200};
201
202/* mpu_private */
203static struct omap_hwmod omap54xx_mpu_private_hwmod = {
204 .name = "mpu_private",
205 .class = &omap54xx_mpu_bus_hwmod_class,
206 .clkdm_name = "mpu_clkdm",
207 .prcm = {
208 .omap4 = {
209 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
210 },
211 },
212};
213
214/*
215 * 'counter' class
216 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
217 */
218
219static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
220 .rev_offs = 0x0000,
221 .sysc_offs = 0x0010,
222 .sysc_flags = SYSC_HAS_SIDLEMODE,
223 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
224 .sysc_fields = &omap_hwmod_sysc_type1,
225};
226
227static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
228 .name = "counter",
229 .sysc = &omap54xx_counter_sysc,
230};
231
232/* counter_32k */
233static struct omap_hwmod omap54xx_counter_32k_hwmod = {
234 .name = "counter_32k",
235 .class = &omap54xx_counter_hwmod_class,
236 .clkdm_name = "wkupaon_clkdm",
237 .flags = HWMOD_SWSUP_SIDLE,
238 .main_clk = "wkupaon_iclk_mux",
239 .prcm = {
240 .omap4 = {
241 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
242 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
243 },
244 },
245};
246
247/*
248 * 'dma' class
249 * dma controller for data exchange between memory to memory (i.e. internal or
250 * external memory) and gp peripherals to memory or memory to gp peripherals
251 */
252
253static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
254 .rev_offs = 0x0000,
255 .sysc_offs = 0x002c,
256 .syss_offs = 0x0028,
257 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
258 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
259 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
260 SYSS_HAS_RESET_STATUS),
261 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
262 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
263 .sysc_fields = &omap_hwmod_sysc_type1,
264};
265
266static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
267 .name = "dma",
268 .sysc = &omap54xx_dma_sysc,
269};
270
271/* dma dev_attr */
272static struct omap_dma_dev_attr dma_dev_attr = {
273 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
274 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
275 .lch_count = 32,
276};
277
278/* dma_system */
279static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
280 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
281 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
282 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
283 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
284 { .irq = -1 }
285};
286
287static struct omap_hwmod omap54xx_dma_system_hwmod = {
288 .name = "dma_system",
289 .class = &omap54xx_dma_hwmod_class,
290 .clkdm_name = "dma_clkdm",
291 .mpu_irqs = omap54xx_dma_system_irqs,
292 .main_clk = "l3_iclk_div",
293 .prcm = {
294 .omap4 = {
295 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
296 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
297 },
298 },
299 .dev_attr = &dma_dev_attr,
300};
301
302/*
303 * 'dmic' class
304 * digital microphone controller
305 */
306
307static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
308 .rev_offs = 0x0000,
309 .sysc_offs = 0x0010,
310 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
311 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
312 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
313 SIDLE_SMART_WKUP),
314 .sysc_fields = &omap_hwmod_sysc_type2,
315};
316
317static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
318 .name = "dmic",
319 .sysc = &omap54xx_dmic_sysc,
320};
321
322/* dmic */
323static struct omap_hwmod omap54xx_dmic_hwmod = {
324 .name = "dmic",
325 .class = &omap54xx_dmic_hwmod_class,
326 .clkdm_name = "abe_clkdm",
327 .main_clk = "dmic_gfclk",
328 .prcm = {
329 .omap4 = {
330 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
331 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
332 .modulemode = MODULEMODE_SWCTRL,
333 },
334 },
335};
336
337/*
338 * 'emif' class
339 * external memory interface no1 (wrapper)
340 */
341
342static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
343 .rev_offs = 0x0000,
344};
345
346static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
347 .name = "emif",
348 .sysc = &omap54xx_emif_sysc,
349};
350
351/* emif1 */
352static struct omap_hwmod omap54xx_emif1_hwmod = {
353 .name = "emif1",
354 .class = &omap54xx_emif_hwmod_class,
355 .clkdm_name = "emif_clkdm",
356 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
357 .main_clk = "dpll_core_h11x2_ck",
358 .prcm = {
359 .omap4 = {
360 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
361 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
362 .modulemode = MODULEMODE_HWCTRL,
363 },
364 },
365};
366
367/* emif2 */
368static struct omap_hwmod omap54xx_emif2_hwmod = {
369 .name = "emif2",
370 .class = &omap54xx_emif_hwmod_class,
371 .clkdm_name = "emif_clkdm",
372 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
373 .main_clk = "dpll_core_h11x2_ck",
374 .prcm = {
375 .omap4 = {
376 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
377 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
378 .modulemode = MODULEMODE_HWCTRL,
379 },
380 },
381};
382
383/*
384 * 'gpio' class
385 * general purpose io module
386 */
387
388static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
389 .rev_offs = 0x0000,
390 .sysc_offs = 0x0010,
391 .syss_offs = 0x0114,
392 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
393 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
394 SYSS_HAS_RESET_STATUS),
395 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
396 SIDLE_SMART_WKUP),
397 .sysc_fields = &omap_hwmod_sysc_type1,
398};
399
400static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
401 .name = "gpio",
402 .sysc = &omap54xx_gpio_sysc,
403 .rev = 2,
404};
405
406/* gpio dev_attr */
407static struct omap_gpio_dev_attr gpio_dev_attr = {
408 .bank_width = 32,
409 .dbck_flag = true,
410};
411
412/* gpio1 */
413static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
414 { .role = "dbclk", .clk = "gpio1_dbclk" },
415};
416
417static struct omap_hwmod omap54xx_gpio1_hwmod = {
418 .name = "gpio1",
419 .class = &omap54xx_gpio_hwmod_class,
420 .clkdm_name = "wkupaon_clkdm",
421 .main_clk = "wkupaon_iclk_mux",
422 .prcm = {
423 .omap4 = {
424 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
425 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
426 .modulemode = MODULEMODE_HWCTRL,
427 },
428 },
429 .opt_clks = gpio1_opt_clks,
430 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
431 .dev_attr = &gpio_dev_attr,
432};
433
434/* gpio2 */
435static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
436 { .role = "dbclk", .clk = "gpio2_dbclk" },
437};
438
439static struct omap_hwmod omap54xx_gpio2_hwmod = {
440 .name = "gpio2",
441 .class = &omap54xx_gpio_hwmod_class,
442 .clkdm_name = "l4per_clkdm",
443 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
444 .main_clk = "l4_root_clk_div",
445 .prcm = {
446 .omap4 = {
447 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
448 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
449 .modulemode = MODULEMODE_HWCTRL,
450 },
451 },
452 .opt_clks = gpio2_opt_clks,
453 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
454 .dev_attr = &gpio_dev_attr,
455};
456
457/* gpio3 */
458static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
459 { .role = "dbclk", .clk = "gpio3_dbclk" },
460};
461
462static struct omap_hwmod omap54xx_gpio3_hwmod = {
463 .name = "gpio3",
464 .class = &omap54xx_gpio_hwmod_class,
465 .clkdm_name = "l4per_clkdm",
466 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
467 .main_clk = "l4_root_clk_div",
468 .prcm = {
469 .omap4 = {
470 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
471 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
472 .modulemode = MODULEMODE_HWCTRL,
473 },
474 },
475 .opt_clks = gpio3_opt_clks,
476 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
477 .dev_attr = &gpio_dev_attr,
478};
479
480/* gpio4 */
481static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
482 { .role = "dbclk", .clk = "gpio4_dbclk" },
483};
484
485static struct omap_hwmod omap54xx_gpio4_hwmod = {
486 .name = "gpio4",
487 .class = &omap54xx_gpio_hwmod_class,
488 .clkdm_name = "l4per_clkdm",
489 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
490 .main_clk = "l4_root_clk_div",
491 .prcm = {
492 .omap4 = {
493 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
494 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
495 .modulemode = MODULEMODE_HWCTRL,
496 },
497 },
498 .opt_clks = gpio4_opt_clks,
499 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
500 .dev_attr = &gpio_dev_attr,
501};
502
503/* gpio5 */
504static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
505 { .role = "dbclk", .clk = "gpio5_dbclk" },
506};
507
508static struct omap_hwmod omap54xx_gpio5_hwmod = {
509 .name = "gpio5",
510 .class = &omap54xx_gpio_hwmod_class,
511 .clkdm_name = "l4per_clkdm",
512 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
513 .main_clk = "l4_root_clk_div",
514 .prcm = {
515 .omap4 = {
516 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
517 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
518 .modulemode = MODULEMODE_HWCTRL,
519 },
520 },
521 .opt_clks = gpio5_opt_clks,
522 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
523 .dev_attr = &gpio_dev_attr,
524};
525
526/* gpio6 */
527static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
528 { .role = "dbclk", .clk = "gpio6_dbclk" },
529};
530
531static struct omap_hwmod omap54xx_gpio6_hwmod = {
532 .name = "gpio6",
533 .class = &omap54xx_gpio_hwmod_class,
534 .clkdm_name = "l4per_clkdm",
535 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
536 .main_clk = "l4_root_clk_div",
537 .prcm = {
538 .omap4 = {
539 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
540 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
541 .modulemode = MODULEMODE_HWCTRL,
542 },
543 },
544 .opt_clks = gpio6_opt_clks,
545 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
546 .dev_attr = &gpio_dev_attr,
547};
548
549/* gpio7 */
550static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
551 { .role = "dbclk", .clk = "gpio7_dbclk" },
552};
553
554static struct omap_hwmod omap54xx_gpio7_hwmod = {
555 .name = "gpio7",
556 .class = &omap54xx_gpio_hwmod_class,
557 .clkdm_name = "l4per_clkdm",
558 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
559 .main_clk = "l4_root_clk_div",
560 .prcm = {
561 .omap4 = {
562 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
563 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
564 .modulemode = MODULEMODE_HWCTRL,
565 },
566 },
567 .opt_clks = gpio7_opt_clks,
568 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
569 .dev_attr = &gpio_dev_attr,
570};
571
572/* gpio8 */
573static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
574 { .role = "dbclk", .clk = "gpio8_dbclk" },
575};
576
577static struct omap_hwmod omap54xx_gpio8_hwmod = {
578 .name = "gpio8",
579 .class = &omap54xx_gpio_hwmod_class,
580 .clkdm_name = "l4per_clkdm",
581 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
582 .main_clk = "l4_root_clk_div",
583 .prcm = {
584 .omap4 = {
585 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
586 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
587 .modulemode = MODULEMODE_HWCTRL,
588 },
589 },
590 .opt_clks = gpio8_opt_clks,
591 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
592 .dev_attr = &gpio_dev_attr,
593};
594
595/*
596 * 'i2c' class
597 * multimaster high-speed i2c controller
598 */
599
600static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
601 .sysc_offs = 0x0010,
602 .syss_offs = 0x0090,
603 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
604 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
605 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
606 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
607 SIDLE_SMART_WKUP),
608 .clockact = CLOCKACT_TEST_ICLK,
609 .sysc_fields = &omap_hwmod_sysc_type1,
610};
611
612static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
613 .name = "i2c",
614 .sysc = &omap54xx_i2c_sysc,
615 .reset = &omap_i2c_reset,
616 .rev = OMAP_I2C_IP_VERSION_2,
617};
618
619/* i2c dev_attr */
620static struct omap_i2c_dev_attr i2c_dev_attr = {
621 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
622};
623
624/* i2c1 */
625static struct omap_hwmod omap54xx_i2c1_hwmod = {
626 .name = "i2c1",
627 .class = &omap54xx_i2c_hwmod_class,
628 .clkdm_name = "l4per_clkdm",
629 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
630 .main_clk = "func_96m_fclk",
631 .prcm = {
632 .omap4 = {
633 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
634 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
635 .modulemode = MODULEMODE_SWCTRL,
636 },
637 },
638 .dev_attr = &i2c_dev_attr,
639};
640
641/* i2c2 */
642static struct omap_hwmod omap54xx_i2c2_hwmod = {
643 .name = "i2c2",
644 .class = &omap54xx_i2c_hwmod_class,
645 .clkdm_name = "l4per_clkdm",
646 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
647 .main_clk = "func_96m_fclk",
648 .prcm = {
649 .omap4 = {
650 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
651 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
652 .modulemode = MODULEMODE_SWCTRL,
653 },
654 },
655 .dev_attr = &i2c_dev_attr,
656};
657
658/* i2c3 */
659static struct omap_hwmod omap54xx_i2c3_hwmod = {
660 .name = "i2c3",
661 .class = &omap54xx_i2c_hwmod_class,
662 .clkdm_name = "l4per_clkdm",
663 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
664 .main_clk = "func_96m_fclk",
665 .prcm = {
666 .omap4 = {
667 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
668 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
669 .modulemode = MODULEMODE_SWCTRL,
670 },
671 },
672 .dev_attr = &i2c_dev_attr,
673};
674
675/* i2c4 */
676static struct omap_hwmod omap54xx_i2c4_hwmod = {
677 .name = "i2c4",
678 .class = &omap54xx_i2c_hwmod_class,
679 .clkdm_name = "l4per_clkdm",
680 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
681 .main_clk = "func_96m_fclk",
682 .prcm = {
683 .omap4 = {
684 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
685 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
686 .modulemode = MODULEMODE_SWCTRL,
687 },
688 },
689 .dev_attr = &i2c_dev_attr,
690};
691
692/* i2c5 */
693static struct omap_hwmod omap54xx_i2c5_hwmod = {
694 .name = "i2c5",
695 .class = &omap54xx_i2c_hwmod_class,
696 .clkdm_name = "l4per_clkdm",
697 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
698 .main_clk = "func_96m_fclk",
699 .prcm = {
700 .omap4 = {
701 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
702 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
703 .modulemode = MODULEMODE_SWCTRL,
704 },
705 },
706 .dev_attr = &i2c_dev_attr,
707};
708
709/*
710 * 'kbd' class
711 * keyboard controller
712 */
713
714static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
715 .rev_offs = 0x0000,
716 .sysc_offs = 0x0010,
717 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
718 SYSC_HAS_SOFTRESET),
719 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
720 .sysc_fields = &omap_hwmod_sysc_type1,
721};
722
723static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
724 .name = "kbd",
725 .sysc = &omap54xx_kbd_sysc,
726};
727
728/* kbd */
729static struct omap_hwmod omap54xx_kbd_hwmod = {
730 .name = "kbd",
731 .class = &omap54xx_kbd_hwmod_class,
732 .clkdm_name = "wkupaon_clkdm",
733 .main_clk = "sys_32k_ck",
734 .prcm = {
735 .omap4 = {
736 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
737 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
738 .modulemode = MODULEMODE_SWCTRL,
739 },
740 },
741};
742
743/*
744 * 'mcbsp' class
745 * multi channel buffered serial port controller
746 */
747
748static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
749 .sysc_offs = 0x008c,
750 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
751 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
752 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
753 .sysc_fields = &omap_hwmod_sysc_type1,
754};
755
756static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
757 .name = "mcbsp",
758 .sysc = &omap54xx_mcbsp_sysc,
759 .rev = MCBSP_CONFIG_TYPE4,
760};
761
762/* mcbsp1 */
763static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
764 { .role = "pad_fck", .clk = "pad_clks_ck" },
765 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
766};
767
768static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
769 .name = "mcbsp1",
770 .class = &omap54xx_mcbsp_hwmod_class,
771 .clkdm_name = "abe_clkdm",
772 .main_clk = "mcbsp1_gfclk",
773 .prcm = {
774 .omap4 = {
775 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
776 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
777 .modulemode = MODULEMODE_SWCTRL,
778 },
779 },
780 .opt_clks = mcbsp1_opt_clks,
781 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
782};
783
784/* mcbsp2 */
785static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
786 { .role = "pad_fck", .clk = "pad_clks_ck" },
787 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
788};
789
790static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
791 .name = "mcbsp2",
792 .class = &omap54xx_mcbsp_hwmod_class,
793 .clkdm_name = "abe_clkdm",
794 .main_clk = "mcbsp2_gfclk",
795 .prcm = {
796 .omap4 = {
797 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
798 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
799 .modulemode = MODULEMODE_SWCTRL,
800 },
801 },
802 .opt_clks = mcbsp2_opt_clks,
803 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
804};
805
806/* mcbsp3 */
807static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
808 { .role = "pad_fck", .clk = "pad_clks_ck" },
809 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
810};
811
812static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
813 .name = "mcbsp3",
814 .class = &omap54xx_mcbsp_hwmod_class,
815 .clkdm_name = "abe_clkdm",
816 .main_clk = "mcbsp3_gfclk",
817 .prcm = {
818 .omap4 = {
819 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
820 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
821 .modulemode = MODULEMODE_SWCTRL,
822 },
823 },
824 .opt_clks = mcbsp3_opt_clks,
825 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
826};
827
828/*
829 * 'mcpdm' class
830 * multi channel pdm controller (proprietary interface with phoenix power
831 * ic)
832 */
833
834static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
835 .rev_offs = 0x0000,
836 .sysc_offs = 0x0010,
837 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
838 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
839 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
840 SIDLE_SMART_WKUP),
841 .sysc_fields = &omap_hwmod_sysc_type2,
842};
843
844static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
845 .name = "mcpdm",
846 .sysc = &omap54xx_mcpdm_sysc,
847};
848
849/* mcpdm */
850static struct omap_hwmod omap54xx_mcpdm_hwmod = {
851 .name = "mcpdm",
852 .class = &omap54xx_mcpdm_hwmod_class,
853 .clkdm_name = "abe_clkdm",
854 /*
855 * It's suspected that the McPDM requires an off-chip main
856 * functional clock, controlled via I2C. This IP block is
857 * currently reset very early during boot, before I2C is
858 * available, so it doesn't seem that we have any choice in
859 * the kernel other than to avoid resetting it. XXX This is
860 * really a hardware issue workaround: every IP block should
861 * be able to source its main functional clock from either
862 * on-chip or off-chip sources. McPDM seems to be the only
863 * current exception.
864 */
865
866 .flags = HWMOD_EXT_OPT_MAIN_CLK,
867 .main_clk = "pad_clks_ck",
868 .prcm = {
869 .omap4 = {
870 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
871 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
872 .modulemode = MODULEMODE_SWCTRL,
873 },
874 },
875};
876
877/*
878 * 'mcspi' class
879 * multichannel serial port interface (mcspi) / master/slave synchronous serial
880 * bus
881 */
882
883static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
884 .rev_offs = 0x0000,
885 .sysc_offs = 0x0010,
886 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
887 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
888 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
889 SIDLE_SMART_WKUP),
890 .sysc_fields = &omap_hwmod_sysc_type2,
891};
892
893static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
894 .name = "mcspi",
895 .sysc = &omap54xx_mcspi_sysc,
896 .rev = OMAP4_MCSPI_REV,
897};
898
899/* mcspi1 */
900/* mcspi1 dev_attr */
901static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
902 .num_chipselect = 4,
903};
904
905static struct omap_hwmod omap54xx_mcspi1_hwmod = {
906 .name = "mcspi1",
907 .class = &omap54xx_mcspi_hwmod_class,
908 .clkdm_name = "l4per_clkdm",
909 .main_clk = "func_48m_fclk",
910 .prcm = {
911 .omap4 = {
912 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
913 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
914 .modulemode = MODULEMODE_SWCTRL,
915 },
916 },
917 .dev_attr = &mcspi1_dev_attr,
918};
919
920/* mcspi2 */
921/* mcspi2 dev_attr */
922static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
923 .num_chipselect = 2,
924};
925
926static struct omap_hwmod omap54xx_mcspi2_hwmod = {
927 .name = "mcspi2",
928 .class = &omap54xx_mcspi_hwmod_class,
929 .clkdm_name = "l4per_clkdm",
930 .main_clk = "func_48m_fclk",
931 .prcm = {
932 .omap4 = {
933 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
934 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
935 .modulemode = MODULEMODE_SWCTRL,
936 },
937 },
938 .dev_attr = &mcspi2_dev_attr,
939};
940
941/* mcspi3 */
942/* mcspi3 dev_attr */
943static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
944 .num_chipselect = 2,
945};
946
947static struct omap_hwmod omap54xx_mcspi3_hwmod = {
948 .name = "mcspi3",
949 .class = &omap54xx_mcspi_hwmod_class,
950 .clkdm_name = "l4per_clkdm",
951 .main_clk = "func_48m_fclk",
952 .prcm = {
953 .omap4 = {
954 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
955 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
956 .modulemode = MODULEMODE_SWCTRL,
957 },
958 },
959 .dev_attr = &mcspi3_dev_attr,
960};
961
962/* mcspi4 */
963/* mcspi4 dev_attr */
964static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
965 .num_chipselect = 1,
966};
967
968static struct omap_hwmod omap54xx_mcspi4_hwmod = {
969 .name = "mcspi4",
970 .class = &omap54xx_mcspi_hwmod_class,
971 .clkdm_name = "l4per_clkdm",
972 .main_clk = "func_48m_fclk",
973 .prcm = {
974 .omap4 = {
975 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
976 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
977 .modulemode = MODULEMODE_SWCTRL,
978 },
979 },
980 .dev_attr = &mcspi4_dev_attr,
981};
982
983/*
984 * 'mmc' class
985 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
986 */
987
988static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
989 .rev_offs = 0x0000,
990 .sysc_offs = 0x0010,
991 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
992 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
993 SYSC_HAS_SOFTRESET),
994 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
995 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
996 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
997 .sysc_fields = &omap_hwmod_sysc_type2,
998};
999
1000static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1001 .name = "mmc",
1002 .sysc = &omap54xx_mmc_sysc,
1003};
1004
1005/* mmc1 */
1006static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1007 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1008};
1009
1010/* mmc1 dev_attr */
1011static struct omap_mmc_dev_attr mmc1_dev_attr = {
1012 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1013};
1014
1015static struct omap_hwmod omap54xx_mmc1_hwmod = {
1016 .name = "mmc1",
1017 .class = &omap54xx_mmc_hwmod_class,
1018 .clkdm_name = "l3init_clkdm",
1019 .main_clk = "mmc1_fclk",
1020 .prcm = {
1021 .omap4 = {
1022 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1023 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1024 .modulemode = MODULEMODE_SWCTRL,
1025 },
1026 },
1027 .opt_clks = mmc1_opt_clks,
1028 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1029 .dev_attr = &mmc1_dev_attr,
1030};
1031
1032/* mmc2 */
1033static struct omap_hwmod omap54xx_mmc2_hwmod = {
1034 .name = "mmc2",
1035 .class = &omap54xx_mmc_hwmod_class,
1036 .clkdm_name = "l3init_clkdm",
1037 .main_clk = "mmc2_fclk",
1038 .prcm = {
1039 .omap4 = {
1040 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1041 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1042 .modulemode = MODULEMODE_SWCTRL,
1043 },
1044 },
1045};
1046
1047/* mmc3 */
1048static struct omap_hwmod omap54xx_mmc3_hwmod = {
1049 .name = "mmc3",
1050 .class = &omap54xx_mmc_hwmod_class,
1051 .clkdm_name = "l4per_clkdm",
1052 .main_clk = "func_48m_fclk",
1053 .prcm = {
1054 .omap4 = {
1055 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1056 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1057 .modulemode = MODULEMODE_SWCTRL,
1058 },
1059 },
1060};
1061
1062/* mmc4 */
1063static struct omap_hwmod omap54xx_mmc4_hwmod = {
1064 .name = "mmc4",
1065 .class = &omap54xx_mmc_hwmod_class,
1066 .clkdm_name = "l4per_clkdm",
1067 .main_clk = "func_48m_fclk",
1068 .prcm = {
1069 .omap4 = {
1070 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1071 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1072 .modulemode = MODULEMODE_SWCTRL,
1073 },
1074 },
1075};
1076
1077/* mmc5 */
1078static struct omap_hwmod omap54xx_mmc5_hwmod = {
1079 .name = "mmc5",
1080 .class = &omap54xx_mmc_hwmod_class,
1081 .clkdm_name = "l4per_clkdm",
1082 .main_clk = "func_96m_fclk",
1083 .prcm = {
1084 .omap4 = {
1085 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1086 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1087 .modulemode = MODULEMODE_SWCTRL,
1088 },
1089 },
1090};
1091
1092/*
1093 * 'mpu' class
1094 * mpu sub-system
1095 */
1096
1097static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1098 .name = "mpu",
1099};
1100
1101/* mpu */
1102static struct omap_hwmod omap54xx_mpu_hwmod = {
1103 .name = "mpu",
1104 .class = &omap54xx_mpu_hwmod_class,
1105 .clkdm_name = "mpu_clkdm",
1106 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1107 .main_clk = "dpll_mpu_m2_ck",
1108 .prcm = {
1109 .omap4 = {
1110 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1111 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1112 },
1113 },
1114};
1115
1116/*
1117 * 'timer' class
1118 * general purpose timer module with accurate 1ms tick
1119 * This class contains several variants: ['timer_1ms', 'timer']
1120 */
1121
1122static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1123 .rev_offs = 0x0000,
1124 .sysc_offs = 0x0010,
1125 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1126 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1127 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1128 SIDLE_SMART_WKUP),
1129 .sysc_fields = &omap_hwmod_sysc_type2,
1130 .clockact = CLOCKACT_TEST_ICLK,
1131};
1132
1133static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1134 .name = "timer",
1135 .sysc = &omap54xx_timer_1ms_sysc,
1136};
1137
1138static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1139 .rev_offs = 0x0000,
1140 .sysc_offs = 0x0010,
1141 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1142 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1143 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1144 SIDLE_SMART_WKUP),
1145 .sysc_fields = &omap_hwmod_sysc_type2,
1146};
1147
1148static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1149 .name = "timer",
1150 .sysc = &omap54xx_timer_sysc,
1151};
1152
1153/* timer1 */
1154static struct omap_hwmod omap54xx_timer1_hwmod = {
1155 .name = "timer1",
1156 .class = &omap54xx_timer_1ms_hwmod_class,
1157 .clkdm_name = "wkupaon_clkdm",
1158 .main_clk = "timer1_gfclk_mux",
1159 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1160 .prcm = {
1161 .omap4 = {
1162 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1163 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1164 .modulemode = MODULEMODE_SWCTRL,
1165 },
1166 },
1167};
1168
1169/* timer2 */
1170static struct omap_hwmod omap54xx_timer2_hwmod = {
1171 .name = "timer2",
1172 .class = &omap54xx_timer_1ms_hwmod_class,
1173 .clkdm_name = "l4per_clkdm",
1174 .main_clk = "timer2_gfclk_mux",
1175 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1176 .prcm = {
1177 .omap4 = {
1178 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1179 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1180 .modulemode = MODULEMODE_SWCTRL,
1181 },
1182 },
1183};
1184
1185/* timer3 */
1186static struct omap_hwmod omap54xx_timer3_hwmod = {
1187 .name = "timer3",
1188 .class = &omap54xx_timer_hwmod_class,
1189 .clkdm_name = "l4per_clkdm",
1190 .main_clk = "timer3_gfclk_mux",
1191 .prcm = {
1192 .omap4 = {
1193 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1194 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1195 .modulemode = MODULEMODE_SWCTRL,
1196 },
1197 },
1198};
1199
1200/* timer4 */
1201static struct omap_hwmod omap54xx_timer4_hwmod = {
1202 .name = "timer4",
1203 .class = &omap54xx_timer_hwmod_class,
1204 .clkdm_name = "l4per_clkdm",
1205 .main_clk = "timer4_gfclk_mux",
1206 .prcm = {
1207 .omap4 = {
1208 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1209 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1210 .modulemode = MODULEMODE_SWCTRL,
1211 },
1212 },
1213};
1214
1215/* timer5 */
1216static struct omap_hwmod omap54xx_timer5_hwmod = {
1217 .name = "timer5",
1218 .class = &omap54xx_timer_hwmod_class,
1219 .clkdm_name = "abe_clkdm",
1220 .main_clk = "timer5_gfclk_mux",
1221 .prcm = {
1222 .omap4 = {
1223 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1224 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1225 .modulemode = MODULEMODE_SWCTRL,
1226 },
1227 },
1228};
1229
1230/* timer6 */
1231static struct omap_hwmod omap54xx_timer6_hwmod = {
1232 .name = "timer6",
1233 .class = &omap54xx_timer_hwmod_class,
1234 .clkdm_name = "abe_clkdm",
1235 .main_clk = "timer6_gfclk_mux",
1236 .prcm = {
1237 .omap4 = {
1238 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1239 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1240 .modulemode = MODULEMODE_SWCTRL,
1241 },
1242 },
1243};
1244
1245/* timer7 */
1246static struct omap_hwmod omap54xx_timer7_hwmod = {
1247 .name = "timer7",
1248 .class = &omap54xx_timer_hwmod_class,
1249 .clkdm_name = "abe_clkdm",
1250 .main_clk = "timer7_gfclk_mux",
1251 .prcm = {
1252 .omap4 = {
1253 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1254 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1255 .modulemode = MODULEMODE_SWCTRL,
1256 },
1257 },
1258};
1259
1260/* timer8 */
1261static struct omap_hwmod omap54xx_timer8_hwmod = {
1262 .name = "timer8",
1263 .class = &omap54xx_timer_hwmod_class,
1264 .clkdm_name = "abe_clkdm",
1265 .main_clk = "timer8_gfclk_mux",
1266 .prcm = {
1267 .omap4 = {
1268 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1269 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1270 .modulemode = MODULEMODE_SWCTRL,
1271 },
1272 },
1273};
1274
1275/* timer9 */
1276static struct omap_hwmod omap54xx_timer9_hwmod = {
1277 .name = "timer9",
1278 .class = &omap54xx_timer_hwmod_class,
1279 .clkdm_name = "l4per_clkdm",
1280 .main_clk = "timer9_gfclk_mux",
1281 .prcm = {
1282 .omap4 = {
1283 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1284 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1285 .modulemode = MODULEMODE_SWCTRL,
1286 },
1287 },
1288};
1289
1290/* timer10 */
1291static struct omap_hwmod omap54xx_timer10_hwmod = {
1292 .name = "timer10",
1293 .class = &omap54xx_timer_1ms_hwmod_class,
1294 .clkdm_name = "l4per_clkdm",
1295 .main_clk = "timer10_gfclk_mux",
1296 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1297 .prcm = {
1298 .omap4 = {
1299 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1300 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1301 .modulemode = MODULEMODE_SWCTRL,
1302 },
1303 },
1304};
1305
1306/* timer11 */
1307static struct omap_hwmod omap54xx_timer11_hwmod = {
1308 .name = "timer11",
1309 .class = &omap54xx_timer_hwmod_class,
1310 .clkdm_name = "l4per_clkdm",
1311 .main_clk = "timer11_gfclk_mux",
1312 .prcm = {
1313 .omap4 = {
1314 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1315 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1316 .modulemode = MODULEMODE_SWCTRL,
1317 },
1318 },
1319};
1320
1321/*
1322 * 'uart' class
1323 * universal asynchronous receiver/transmitter (uart)
1324 */
1325
1326static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1327 .rev_offs = 0x0050,
1328 .sysc_offs = 0x0054,
1329 .syss_offs = 0x0058,
1330 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1331 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1332 SYSS_HAS_RESET_STATUS),
1333 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1334 SIDLE_SMART_WKUP),
1335 .sysc_fields = &omap_hwmod_sysc_type1,
1336};
1337
1338static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1339 .name = "uart",
1340 .sysc = &omap54xx_uart_sysc,
1341};
1342
1343/* uart1 */
1344static struct omap_hwmod omap54xx_uart1_hwmod = {
1345 .name = "uart1",
1346 .class = &omap54xx_uart_hwmod_class,
1347 .clkdm_name = "l4per_clkdm",
1348 .main_clk = "func_48m_fclk",
1349 .prcm = {
1350 .omap4 = {
1351 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1352 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1353 .modulemode = MODULEMODE_SWCTRL,
1354 },
1355 },
1356};
1357
1358/* uart2 */
1359static struct omap_hwmod omap54xx_uart2_hwmod = {
1360 .name = "uart2",
1361 .class = &omap54xx_uart_hwmod_class,
1362 .clkdm_name = "l4per_clkdm",
1363 .main_clk = "func_48m_fclk",
1364 .prcm = {
1365 .omap4 = {
1366 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1367 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1368 .modulemode = MODULEMODE_SWCTRL,
1369 },
1370 },
1371};
1372
1373/* uart3 */
1374static struct omap_hwmod omap54xx_uart3_hwmod = {
1375 .name = "uart3",
1376 .class = &omap54xx_uart_hwmod_class,
1377 .clkdm_name = "l4per_clkdm",
7dedd346 1378 .flags = DEBUG_OMAP4UART3_FLAGS,
08e4830d
BC		 1379 .main_clk = "func_48m_fclk",
1380 .prcm = {
1381 .omap4 = {
1382 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1383 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1384 .modulemode = MODULEMODE_SWCTRL,
1385 },
1386 },
1387};
1388
1389/* uart4 */
1390static struct omap_hwmod omap54xx_uart4_hwmod = {
1391 .name = "uart4",
1392 .class = &omap54xx_uart_hwmod_class,
1393 .clkdm_name = "l4per_clkdm",
7dedd346 1394 .flags = DEBUG_OMAP4UART4_FLAGS,
08e4830d
BC		 1395 .main_clk = "func_48m_fclk",
1396 .prcm = {
1397 .omap4 = {
1398 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1399 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1400 .modulemode = MODULEMODE_SWCTRL,
1401 },
1402 },
1403};
1404
1405/* uart5 */
1406static struct omap_hwmod omap54xx_uart5_hwmod = {
1407 .name = "uart5",
1408 .class = &omap54xx_uart_hwmod_class,
1409 .clkdm_name = "l4per_clkdm",
1410 .main_clk = "func_48m_fclk",
1411 .prcm = {
1412 .omap4 = {
1413 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1414 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1415 .modulemode = MODULEMODE_SWCTRL,
1416 },
1417 },
1418};
1419
1420/* uart6 */
1421static struct omap_hwmod omap54xx_uart6_hwmod = {
1422 .name = "uart6",
1423 .class = &omap54xx_uart_hwmod_class,
1424 .clkdm_name = "l4per_clkdm",
1425 .main_clk = "func_48m_fclk",
1426 .prcm = {
1427 .omap4 = {
1428 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1429 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1430 .modulemode = MODULEMODE_SWCTRL,
1431 },
1432 },
1433};
1434
1435/*
1436 * 'usb_otg_ss' class
1437 * 2.0 super speed (usb_otg_ss) controller
1438 */
1439
1440static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1441 .rev_offs = 0x0000,
1442 .sysc_offs = 0x0010,
1443 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1444 SYSC_HAS_SIDLEMODE),
1445 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1446 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1447 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1448 .sysc_fields = &omap_hwmod_sysc_type2,
1449};
1450
1451static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1452 .name = "usb_otg_ss",
1453 .sysc = &omap54xx_usb_otg_ss_sysc,
1454};
1455
1456/* usb_otg_ss */
1457static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1458 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1459};
1460
1461static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1462 .name = "usb_otg_ss",
1463 .class = &omap54xx_usb_otg_ss_hwmod_class,
1464 .clkdm_name = "l3init_clkdm",
1465 .flags = HWMOD_SWSUP_SIDLE,
1466 .main_clk = "dpll_core_h13x2_ck",
1467 .prcm = {
1468 .omap4 = {
1469 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1470 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1471 .modulemode = MODULEMODE_HWCTRL,
1472 },
1473 },
1474 .opt_clks = usb_otg_ss_opt_clks,
1475 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1476};
1477
1478/*
1479 * 'wd_timer' class
1480 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1481 * overflow condition
1482 */
1483
1484static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1485 .rev_offs = 0x0000,
1486 .sysc_offs = 0x0010,
1487 .syss_offs = 0x0014,
1488 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1489 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1490 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1491 SIDLE_SMART_WKUP),
1492 .sysc_fields = &omap_hwmod_sysc_type1,
1493};
1494
1495static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1496 .name = "wd_timer",
1497 .sysc = &omap54xx_wd_timer_sysc,
1498 .pre_shutdown = &omap2_wd_timer_disable,
1499};
1500
1501/* wd_timer2 */
1502static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1503 .name = "wd_timer2",
1504 .class = &omap54xx_wd_timer_hwmod_class,
1505 .clkdm_name = "wkupaon_clkdm",
1506 .main_clk = "sys_32k_ck",
1507 .prcm = {
1508 .omap4 = {
1509 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1510 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1511 .modulemode = MODULEMODE_SWCTRL,
1512 },
1513 },
1514};
1515
1516
1517/*
1518 * Interfaces
1519 */
1520
1521/* l3_main_1 -> dmm */
1522static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1523 .master = &omap54xx_l3_main_1_hwmod,
1524 .slave = &omap54xx_dmm_hwmod,
1525 .clk = "l3_iclk_div",
1526 .user = OCP_USER_SDMA,
1527};
1528
1529/* l3_main_3 -> l3_instr */
1530static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1531 .master = &omap54xx_l3_main_3_hwmod,
1532 .slave = &omap54xx_l3_instr_hwmod,
1533 .clk = "l3_iclk_div",
1534 .user = OCP_USER_MPU | OCP_USER_SDMA,
1535};
1536
1537/* l3_main_2 -> l3_main_1 */
1538static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1539 .master = &omap54xx_l3_main_2_hwmod,
1540 .slave = &omap54xx_l3_main_1_hwmod,
1541 .clk = "l3_iclk_div",
1542 .user = OCP_USER_MPU | OCP_USER_SDMA,
1543};
1544
1545/* l4_cfg -> l3_main_1 */
1546static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1547 .master = &omap54xx_l4_cfg_hwmod,
1548 .slave = &omap54xx_l3_main_1_hwmod,
1549 .clk = "l3_iclk_div",
1550 .user = OCP_USER_MPU | OCP_USER_SDMA,
1551};
1552
1553/* mpu -> l3_main_1 */
1554static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1555 .master = &omap54xx_mpu_hwmod,
1556 .slave = &omap54xx_l3_main_1_hwmod,
1557 .clk = "l3_iclk_div",
1558 .user = OCP_USER_MPU,
1559};
1560
1561/* l3_main_1 -> l3_main_2 */
1562static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1563 .master = &omap54xx_l3_main_1_hwmod,
1564 .slave = &omap54xx_l3_main_2_hwmod,
1565 .clk = "l3_iclk_div",
1566 .user = OCP_USER_MPU,
1567};
1568
1569/* l4_cfg -> l3_main_2 */
1570static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1571 .master = &omap54xx_l4_cfg_hwmod,
1572 .slave = &omap54xx_l3_main_2_hwmod,
1573 .clk = "l3_iclk_div",
1574 .user = OCP_USER_MPU | OCP_USER_SDMA,
1575};
1576
1577/* l3_main_1 -> l3_main_3 */
1578static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1579 .master = &omap54xx_l3_main_1_hwmod,
1580 .slave = &omap54xx_l3_main_3_hwmod,
1581 .clk = "l3_iclk_div",
1582 .user = OCP_USER_MPU,
1583};
1584
1585/* l3_main_2 -> l3_main_3 */
1586static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1587 .master = &omap54xx_l3_main_2_hwmod,
1588 .slave = &omap54xx_l3_main_3_hwmod,
1589 .clk = "l3_iclk_div",
1590 .user = OCP_USER_MPU | OCP_USER_SDMA,
1591};
1592
1593/* l4_cfg -> l3_main_3 */
1594static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1595 .master = &omap54xx_l4_cfg_hwmod,
1596 .slave = &omap54xx_l3_main_3_hwmod,
1597 .clk = "l3_iclk_div",
1598 .user = OCP_USER_MPU | OCP_USER_SDMA,
1599};
1600
1601/* l3_main_1 -> l4_abe */
1602static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1603 .master = &omap54xx_l3_main_1_hwmod,
1604 .slave = &omap54xx_l4_abe_hwmod,
1605 .clk = "abe_iclk",
1606 .user = OCP_USER_MPU | OCP_USER_SDMA,
1607};
1608
1609/* mpu -> l4_abe */
1610static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1611 .master = &omap54xx_mpu_hwmod,
1612 .slave = &omap54xx_l4_abe_hwmod,
1613 .clk = "abe_iclk",
1614 .user = OCP_USER_MPU | OCP_USER_SDMA,
1615};
1616
1617/* l3_main_1 -> l4_cfg */
1618static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1619 .master = &omap54xx_l3_main_1_hwmod,
1620 .slave = &omap54xx_l4_cfg_hwmod,
1621 .clk = "l4_root_clk_div",
1622 .user = OCP_USER_MPU | OCP_USER_SDMA,
1623};
1624
1625/* l3_main_2 -> l4_per */
1626static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1627 .master = &omap54xx_l3_main_2_hwmod,
1628 .slave = &omap54xx_l4_per_hwmod,
1629 .clk = "l4_root_clk_div",
1630 .user = OCP_USER_MPU | OCP_USER_SDMA,
1631};
1632
1633/* l3_main_1 -> l4_wkup */
1634static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1635 .master = &omap54xx_l3_main_1_hwmod,
1636 .slave = &omap54xx_l4_wkup_hwmod,
1637 .clk = "wkupaon_iclk_mux",
1638 .user = OCP_USER_MPU | OCP_USER_SDMA,
1639};
1640
1641/* mpu -> mpu_private */
1642static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1643 .master = &omap54xx_mpu_hwmod,
1644 .slave = &omap54xx_mpu_private_hwmod,
1645 .clk = "l3_iclk_div",
1646 .user = OCP_USER_MPU | OCP_USER_SDMA,
1647};
1648
1649/* l4_wkup -> counter_32k */
1650static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1651 .master = &omap54xx_l4_wkup_hwmod,
1652 .slave = &omap54xx_counter_32k_hwmod,
1653 .clk = "wkupaon_iclk_mux",
1654 .user = OCP_USER_MPU | OCP_USER_SDMA,
1655};
1656
1657static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1658 {
1659 .pa_start = 0x4a056000,
1660 .pa_end = 0x4a056fff,
1661 .flags = ADDR_TYPE_RT
1662 },
1663 { }
1664};
1665
1666/* l4_cfg -> dma_system */
1667static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1668 .master = &omap54xx_l4_cfg_hwmod,
1669 .slave = &omap54xx_dma_system_hwmod,
1670 .clk = "l4_root_clk_div",
1671 .addr = omap54xx_dma_system_addrs,
1672 .user = OCP_USER_MPU | OCP_USER_SDMA,
1673};
1674
1675/* l4_abe -> dmic */
1676static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1677 .master = &omap54xx_l4_abe_hwmod,
1678 .slave = &omap54xx_dmic_hwmod,
1679 .clk = "abe_iclk",
1680 .user = OCP_USER_MPU,
1681};
1682
1683/* mpu -> emif1 */
1684static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1685 .master = &omap54xx_mpu_hwmod,
1686 .slave = &omap54xx_emif1_hwmod,
1687 .clk = "dpll_core_h11x2_ck",
1688 .user = OCP_USER_MPU | OCP_USER_SDMA,
1689};
1690
1691/* mpu -> emif2 */
1692static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1693 .master = &omap54xx_mpu_hwmod,
1694 .slave = &omap54xx_emif2_hwmod,
1695 .clk = "dpll_core_h11x2_ck",
1696 .user = OCP_USER_MPU | OCP_USER_SDMA,
1697};
1698
1699/* l4_wkup -> gpio1 */
1700static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1701 .master = &omap54xx_l4_wkup_hwmod,
1702 .slave = &omap54xx_gpio1_hwmod,
1703 .clk = "wkupaon_iclk_mux",
1704 .user = OCP_USER_MPU | OCP_USER_SDMA,
1705};
1706
1707/* l4_per -> gpio2 */
1708static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1709 .master = &omap54xx_l4_per_hwmod,
1710 .slave = &omap54xx_gpio2_hwmod,
1711 .clk = "l4_root_clk_div",
1712 .user = OCP_USER_MPU | OCP_USER_SDMA,
1713};
1714
1715/* l4_per -> gpio3 */
1716static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1717 .master = &omap54xx_l4_per_hwmod,
1718 .slave = &omap54xx_gpio3_hwmod,
1719 .clk = "l4_root_clk_div",
1720 .user = OCP_USER_MPU | OCP_USER_SDMA,
1721};
1722
1723/* l4_per -> gpio4 */
1724static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1725 .master = &omap54xx_l4_per_hwmod,
1726 .slave = &omap54xx_gpio4_hwmod,
1727 .clk = "l4_root_clk_div",
1728 .user = OCP_USER_MPU | OCP_USER_SDMA,
1729};
1730
1731/* l4_per -> gpio5 */
1732static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1733 .master = &omap54xx_l4_per_hwmod,
1734 .slave = &omap54xx_gpio5_hwmod,
1735 .clk = "l4_root_clk_div",
1736 .user = OCP_USER_MPU | OCP_USER_SDMA,
1737};
1738
1739/* l4_per -> gpio6 */
1740static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1741 .master = &omap54xx_l4_per_hwmod,
1742 .slave = &omap54xx_gpio6_hwmod,
1743 .clk = "l4_root_clk_div",
1744 .user = OCP_USER_MPU | OCP_USER_SDMA,
1745};
1746
1747/* l4_per -> gpio7 */
1748static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1749 .master = &omap54xx_l4_per_hwmod,
1750 .slave = &omap54xx_gpio7_hwmod,
1751 .clk = "l4_root_clk_div",
1752 .user = OCP_USER_MPU | OCP_USER_SDMA,
1753};
1754
1755/* l4_per -> gpio8 */
1756static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1757 .master = &omap54xx_l4_per_hwmod,
1758 .slave = &omap54xx_gpio8_hwmod,
1759 .clk = "l4_root_clk_div",
1760 .user = OCP_USER_MPU | OCP_USER_SDMA,
1761};
1762
1763/* l4_per -> i2c1 */
1764static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1765 .master = &omap54xx_l4_per_hwmod,
1766 .slave = &omap54xx_i2c1_hwmod,
1767 .clk = "l4_root_clk_div",
1768 .user = OCP_USER_MPU | OCP_USER_SDMA,
1769};
1770
1771/* l4_per -> i2c2 */
1772static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1773 .master = &omap54xx_l4_per_hwmod,
1774 .slave = &omap54xx_i2c2_hwmod,
1775 .clk = "l4_root_clk_div",
1776 .user = OCP_USER_MPU | OCP_USER_SDMA,
1777};
1778
1779/* l4_per -> i2c3 */
1780static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1781 .master = &omap54xx_l4_per_hwmod,
1782 .slave = &omap54xx_i2c3_hwmod,
1783 .clk = "l4_root_clk_div",
1784 .user = OCP_USER_MPU | OCP_USER_SDMA,
1785};
1786
1787/* l4_per -> i2c4 */
1788static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
1789 .master = &omap54xx_l4_per_hwmod,
1790 .slave = &omap54xx_i2c4_hwmod,
1791 .clk = "l4_root_clk_div",
1792 .user = OCP_USER_MPU | OCP_USER_SDMA,
1793};
1794
1795/* l4_per -> i2c5 */
1796static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
1797 .master = &omap54xx_l4_per_hwmod,
1798 .slave = &omap54xx_i2c5_hwmod,
1799 .clk = "l4_root_clk_div",
1800 .user = OCP_USER_MPU | OCP_USER_SDMA,
1801};
1802
1803/* l4_wkup -> kbd */
1804static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1805 .master = &omap54xx_l4_wkup_hwmod,
1806 .slave = &omap54xx_kbd_hwmod,
1807 .clk = "wkupaon_iclk_mux",
1808 .user = OCP_USER_MPU | OCP_USER_SDMA,
1809};
1810
1811/* l4_abe -> mcbsp1 */
1812static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
1813 .master = &omap54xx_l4_abe_hwmod,
1814 .slave = &omap54xx_mcbsp1_hwmod,
1815 .clk = "abe_iclk",
1816 .user = OCP_USER_MPU,
1817};
1818
1819/* l4_abe -> mcbsp2 */
1820static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
1821 .master = &omap54xx_l4_abe_hwmod,
1822 .slave = &omap54xx_mcbsp2_hwmod,
1823 .clk = "abe_iclk",
1824 .user = OCP_USER_MPU,
1825};
1826
1827/* l4_abe -> mcbsp3 */
1828static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
1829 .master = &omap54xx_l4_abe_hwmod,
1830 .slave = &omap54xx_mcbsp3_hwmod,
1831 .clk = "abe_iclk",
1832 .user = OCP_USER_MPU,
1833};
1834
1835/* l4_abe -> mcpdm */
1836static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
1837 .master = &omap54xx_l4_abe_hwmod,
1838 .slave = &omap54xx_mcpdm_hwmod,
1839 .clk = "abe_iclk",
1840 .user = OCP_USER_MPU,
1841};
1842
1843/* l4_per -> mcspi1 */
1844static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
1845 .master = &omap54xx_l4_per_hwmod,
1846 .slave = &omap54xx_mcspi1_hwmod,
1847 .clk = "l4_root_clk_div",
1848 .user = OCP_USER_MPU | OCP_USER_SDMA,
1849};
1850
1851/* l4_per -> mcspi2 */
1852static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
1853 .master = &omap54xx_l4_per_hwmod,
1854 .slave = &omap54xx_mcspi2_hwmod,
1855 .clk = "l4_root_clk_div",
1856 .user = OCP_USER_MPU | OCP_USER_SDMA,
1857};
1858
1859/* l4_per -> mcspi3 */
1860static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
1861 .master = &omap54xx_l4_per_hwmod,
1862 .slave = &omap54xx_mcspi3_hwmod,
1863 .clk = "l4_root_clk_div",
1864 .user = OCP_USER_MPU | OCP_USER_SDMA,
1865};
1866
1867/* l4_per -> mcspi4 */
1868static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
1869 .master = &omap54xx_l4_per_hwmod,
1870 .slave = &omap54xx_mcspi4_hwmod,
1871 .clk = "l4_root_clk_div",
1872 .user = OCP_USER_MPU | OCP_USER_SDMA,
1873};
1874
1875/* l4_per -> mmc1 */
1876static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
1877 .master = &omap54xx_l4_per_hwmod,
1878 .slave = &omap54xx_mmc1_hwmod,
1879 .clk = "l3_iclk_div",
1880 .user = OCP_USER_MPU | OCP_USER_SDMA,
1881};
1882
1883/* l4_per -> mmc2 */
1884static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
1885 .master = &omap54xx_l4_per_hwmod,
1886 .slave = &omap54xx_mmc2_hwmod,
1887 .clk = "l3_iclk_div",
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889};
1890
1891/* l4_per -> mmc3 */
1892static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
1893 .master = &omap54xx_l4_per_hwmod,
1894 .slave = &omap54xx_mmc3_hwmod,
1895 .clk = "l4_root_clk_div",
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897};
1898
1899/* l4_per -> mmc4 */
1900static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
1901 .master = &omap54xx_l4_per_hwmod,
1902 .slave = &omap54xx_mmc4_hwmod,
1903 .clk = "l4_root_clk_div",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905};
1906
1907/* l4_per -> mmc5 */
1908static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
1909 .master = &omap54xx_l4_per_hwmod,
1910 .slave = &omap54xx_mmc5_hwmod,
1911 .clk = "l4_root_clk_div",
1912 .user = OCP_USER_MPU | OCP_USER_SDMA,
1913};
1914
1915/* l4_cfg -> mpu */
1916static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
1917 .master = &omap54xx_l4_cfg_hwmod,
1918 .slave = &omap54xx_mpu_hwmod,
1919 .clk = "l4_root_clk_div",
1920 .user = OCP_USER_MPU | OCP_USER_SDMA,
1921};
1922
1923/* l4_wkup -> timer1 */
1924static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
1925 .master = &omap54xx_l4_wkup_hwmod,
1926 .slave = &omap54xx_timer1_hwmod,
1927 .clk = "wkupaon_iclk_mux",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929};
1930
1931/* l4_per -> timer2 */
1932static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
1933 .master = &omap54xx_l4_per_hwmod,
1934 .slave = &omap54xx_timer2_hwmod,
1935 .clk = "l4_root_clk_div",
1936 .user = OCP_USER_MPU | OCP_USER_SDMA,
1937};
1938
1939/* l4_per -> timer3 */
1940static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
1941 .master = &omap54xx_l4_per_hwmod,
1942 .slave = &omap54xx_timer3_hwmod,
1943 .clk = "l4_root_clk_div",
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945};
1946
1947/* l4_per -> timer4 */
1948static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
1949 .master = &omap54xx_l4_per_hwmod,
1950 .slave = &omap54xx_timer4_hwmod,
1951 .clk = "l4_root_clk_div",
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1953};
1954
1955/* l4_abe -> timer5 */
1956static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
1957 .master = &omap54xx_l4_abe_hwmod,
1958 .slave = &omap54xx_timer5_hwmod,
1959 .clk = "abe_iclk",
1960 .user = OCP_USER_MPU,
1961};
1962
1963/* l4_abe -> timer6 */
1964static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
1965 .master = &omap54xx_l4_abe_hwmod,
1966 .slave = &omap54xx_timer6_hwmod,
1967 .clk = "abe_iclk",
1968 .user = OCP_USER_MPU,
1969};
1970
1971/* l4_abe -> timer7 */
1972static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
1973 .master = &omap54xx_l4_abe_hwmod,
1974 .slave = &omap54xx_timer7_hwmod,
1975 .clk = "abe_iclk",
1976 .user = OCP_USER_MPU,
1977};
1978
1979/* l4_abe -> timer8 */
1980static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
1981 .master = &omap54xx_l4_abe_hwmod,
1982 .slave = &omap54xx_timer8_hwmod,
1983 .clk = "abe_iclk",
1984 .user = OCP_USER_MPU,
1985};
1986
1987/* l4_per -> timer9 */
1988static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
1989 .master = &omap54xx_l4_per_hwmod,
1990 .slave = &omap54xx_timer9_hwmod,
1991 .clk = "l4_root_clk_div",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993};
1994
1995/* l4_per -> timer10 */
1996static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
1997 .master = &omap54xx_l4_per_hwmod,
1998 .slave = &omap54xx_timer10_hwmod,
1999 .clk = "l4_root_clk_div",
2000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001};
2002
2003/* l4_per -> timer11 */
2004static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2005 .master = &omap54xx_l4_per_hwmod,
2006 .slave = &omap54xx_timer11_hwmod,
2007 .clk = "l4_root_clk_div",
2008 .user = OCP_USER_MPU | OCP_USER_SDMA,
2009};
2010
2011/* l4_per -> uart1 */
2012static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2013 .master = &omap54xx_l4_per_hwmod,
2014 .slave = &omap54xx_uart1_hwmod,
2015 .clk = "l4_root_clk_div",
2016 .user = OCP_USER_MPU | OCP_USER_SDMA,
2017};
2018
2019/* l4_per -> uart2 */
2020static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2021 .master = &omap54xx_l4_per_hwmod,
2022 .slave = &omap54xx_uart2_hwmod,
2023 .clk = "l4_root_clk_div",
2024 .user = OCP_USER_MPU | OCP_USER_SDMA,
2025};
2026
2027/* l4_per -> uart3 */
2028static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2029 .master = &omap54xx_l4_per_hwmod,
2030 .slave = &omap54xx_uart3_hwmod,
2031 .clk = "l4_root_clk_div",
2032 .user = OCP_USER_MPU | OCP_USER_SDMA,
2033};
2034
2035/* l4_per -> uart4 */
2036static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2037 .master = &omap54xx_l4_per_hwmod,
2038 .slave = &omap54xx_uart4_hwmod,
2039 .clk = "l4_root_clk_div",
2040 .user = OCP_USER_MPU | OCP_USER_SDMA,
2041};
2042
2043/* l4_per -> uart5 */
2044static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2045 .master = &omap54xx_l4_per_hwmod,
2046 .slave = &omap54xx_uart5_hwmod,
2047 .clk = "l4_root_clk_div",
2048 .user = OCP_USER_MPU | OCP_USER_SDMA,
2049};
2050
2051/* l4_per -> uart6 */
2052static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2053 .master = &omap54xx_l4_per_hwmod,
2054 .slave = &omap54xx_uart6_hwmod,
2055 .clk = "l4_root_clk_div",
2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057};
2058
2059/* l4_cfg -> usb_otg_ss */
2060static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2061 .master = &omap54xx_l4_cfg_hwmod,
2062 .slave = &omap54xx_usb_otg_ss_hwmod,
2063 .clk = "dpll_core_h13x2_ck",
2064 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065};
2066
2067/* l4_wkup -> wd_timer2 */
2068static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2069 .master = &omap54xx_l4_wkup_hwmod,
2070 .slave = &omap54xx_wd_timer2_hwmod,
2071 .clk = "wkupaon_iclk_mux",
2072 .user = OCP_USER_MPU | OCP_USER_SDMA,
2073};
2074
2075static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2076 &omap54xx_l3_main_1__dmm,
2077 &omap54xx_l3_main_3__l3_instr,
2078 &omap54xx_l3_main_2__l3_main_1,
2079 &omap54xx_l4_cfg__l3_main_1,
2080 &omap54xx_mpu__l3_main_1,
2081 &omap54xx_l3_main_1__l3_main_2,
2082 &omap54xx_l4_cfg__l3_main_2,
2083 &omap54xx_l3_main_1__l3_main_3,
2084 &omap54xx_l3_main_2__l3_main_3,
2085 &omap54xx_l4_cfg__l3_main_3,
2086 &omap54xx_l3_main_1__l4_abe,
2087 &omap54xx_mpu__l4_abe,
2088 &omap54xx_l3_main_1__l4_cfg,
2089 &omap54xx_l3_main_2__l4_per,
2090 &omap54xx_l3_main_1__l4_wkup,
2091 &omap54xx_mpu__mpu_private,
2092 &omap54xx_l4_wkup__counter_32k,
2093 &omap54xx_l4_cfg__dma_system,
2094 &omap54xx_l4_abe__dmic,
2095 &omap54xx_mpu__emif1,
2096 &omap54xx_mpu__emif2,
2097 &omap54xx_l4_wkup__gpio1,
2098 &omap54xx_l4_per__gpio2,
2099 &omap54xx_l4_per__gpio3,
2100 &omap54xx_l4_per__gpio4,
2101 &omap54xx_l4_per__gpio5,
2102 &omap54xx_l4_per__gpio6,
2103 &omap54xx_l4_per__gpio7,
2104 &omap54xx_l4_per__gpio8,
2105 &omap54xx_l4_per__i2c1,
2106 &omap54xx_l4_per__i2c2,
2107 &omap54xx_l4_per__i2c3,
2108 &omap54xx_l4_per__i2c4,
2109 &omap54xx_l4_per__i2c5,
2110 &omap54xx_l4_wkup__kbd,
2111 &omap54xx_l4_abe__mcbsp1,
2112 &omap54xx_l4_abe__mcbsp2,
2113 &omap54xx_l4_abe__mcbsp3,
2114 &omap54xx_l4_abe__mcpdm,
2115 &omap54xx_l4_per__mcspi1,
2116 &omap54xx_l4_per__mcspi2,
2117 &omap54xx_l4_per__mcspi3,
2118 &omap54xx_l4_per__mcspi4,
2119 &omap54xx_l4_per__mmc1,
2120 &omap54xx_l4_per__mmc2,
2121 &omap54xx_l4_per__mmc3,
2122 &omap54xx_l4_per__mmc4,
2123 &omap54xx_l4_per__mmc5,
2124 &omap54xx_l4_cfg__mpu,
2125 &omap54xx_l4_wkup__timer1,
2126 &omap54xx_l4_per__timer2,
2127 &omap54xx_l4_per__timer3,
2128 &omap54xx_l4_per__timer4,
2129 &omap54xx_l4_abe__timer5,
2130 &omap54xx_l4_abe__timer6,
2131 &omap54xx_l4_abe__timer7,
2132 &omap54xx_l4_abe__timer8,
2133 &omap54xx_l4_per__timer9,
2134 &omap54xx_l4_per__timer10,
2135 &omap54xx_l4_per__timer11,
2136 &omap54xx_l4_per__uart1,
2137 &omap54xx_l4_per__uart2,
2138 &omap54xx_l4_per__uart3,
2139 &omap54xx_l4_per__uart4,
2140 &omap54xx_l4_per__uart5,
2141 &omap54xx_l4_per__uart6,
2142 &omap54xx_l4_cfg__usb_otg_ss,
2143 &omap54xx_l4_wkup__wd_timer2,
2144 NULL,
2145};
2146
2147int __init omap54xx_hwmod_init(void)
2148{
2149 omap_hwmod_init();
2150 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2151}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git