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ARM: AM33xx: hwmod_data: add the sysc configuration for spinlock
[thirdparty/kernel/stable.git] / arch / arm / mach-omap2 / omap_hwmod_54xx_data.c
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08e4830d
BC		 1/*
2 * Hardware modules present on the OMAP54xx chips
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
5 *
6 * Paul Walmsley
7 * Benoit Cousson
8 *
9 * This file is automatically generated from the OMAP hardware databases.
10 * We respectfully ask that any modifications to this file be coordinated
11 * with the public linux-omap@vger.kernel.org mailing list and the
12 * authors above to ensure that the autogeneration scripts are kept
13 * up-to-date with the file contents.
14 *
15 * This program is free software; you can redistribute it and/or modify
16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation.
18 */
19
20#include <linux/io.h>
21#include <linux/platform_data/gpio-omap.h>
22#include <linux/power/smartreflex.h>
08e4830d
BC		 23#include <linux/i2c-omap.h>
24
25#include <linux/omap-dma.h>
26#include <linux/platform_data/spi-omap2-mcspi.h>
27#include <linux/platform_data/asoc-ti-mcbsp.h>
28#include <plat/dmtimer.h>
29
30#include "omap_hwmod.h"
31#include "omap_hwmod_common_data.h"
32#include "cm1_54xx.h"
33#include "cm2_54xx.h"
34#include "prm54xx.h"
08e4830d
BC		 35#include "i2c.h"
36#include "mmc.h"
37#include "wd_timer.h"
38
39/* Base offset for all OMAP5 interrupts external to MPUSS */
40#define OMAP54XX_IRQ_GIC_START 32
41
42/* Base offset for all OMAP5 dma requests */
43#define OMAP54XX_DMA_REQ_START 1
44
45
46/*
47 * IP blocks
48 */
49
50/*
51 * 'dmm' class
52 * instance(s): dmm
53 */
54static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
55 .name = "dmm",
56};
57
58/* dmm */
59static struct omap_hwmod omap54xx_dmm_hwmod = {
60 .name = "dmm",
61 .class = &omap54xx_dmm_hwmod_class,
62 .clkdm_name = "emif_clkdm",
63 .prcm = {
64 .omap4 = {
65 .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
66 .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
67 },
68 },
69};
70
71/*
72 * 'l3' class
73 * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
74 */
75static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
76 .name = "l3",
77};
78
79/* l3_instr */
80static struct omap_hwmod omap54xx_l3_instr_hwmod = {
81 .name = "l3_instr",
82 .class = &omap54xx_l3_hwmod_class,
83 .clkdm_name = "l3instr_clkdm",
84 .prcm = {
85 .omap4 = {
86 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
87 .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
88 .modulemode = MODULEMODE_HWCTRL,
89 },
90 },
91};
92
93/* l3_main_1 */
94static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
95 .name = "l3_main_1",
96 .class = &omap54xx_l3_hwmod_class,
97 .clkdm_name = "l3main1_clkdm",
98 .prcm = {
99 .omap4 = {
100 .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
101 .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
102 },
103 },
104};
105
106/* l3_main_2 */
107static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
108 .name = "l3_main_2",
109 .class = &omap54xx_l3_hwmod_class,
110 .clkdm_name = "l3main2_clkdm",
111 .prcm = {
112 .omap4 = {
113 .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
114 .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
115 },
116 },
117};
118
119/* l3_main_3 */
120static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
121 .name = "l3_main_3",
122 .class = &omap54xx_l3_hwmod_class,
123 .clkdm_name = "l3instr_clkdm",
124 .prcm = {
125 .omap4 = {
126 .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
127 .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
128 .modulemode = MODULEMODE_HWCTRL,
129 },
130 },
131};
132
133/*
134 * 'l4' class
135 * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
136 */
137static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
138 .name = "l4",
139};
140
141/* l4_abe */
142static struct omap_hwmod omap54xx_l4_abe_hwmod = {
143 .name = "l4_abe",
144 .class = &omap54xx_l4_hwmod_class,
145 .clkdm_name = "abe_clkdm",
146 .prcm = {
147 .omap4 = {
148 .clkctrl_offs = OMAP54XX_CM_ABE_L4_ABE_CLKCTRL_OFFSET,
149 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
150 },
151 },
152};
153
154/* l4_cfg */
155static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
156 .name = "l4_cfg",
157 .class = &omap54xx_l4_hwmod_class,
158 .clkdm_name = "l4cfg_clkdm",
159 .prcm = {
160 .omap4 = {
161 .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
162 .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
163 },
164 },
165};
166
167/* l4_per */
168static struct omap_hwmod omap54xx_l4_per_hwmod = {
169 .name = "l4_per",
170 .class = &omap54xx_l4_hwmod_class,
171 .clkdm_name = "l4per_clkdm",
172 .prcm = {
173 .omap4 = {
174 .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
175 .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
176 },
177 },
178};
179
180/* l4_wkup */
181static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
182 .name = "l4_wkup",
183 .class = &omap54xx_l4_hwmod_class,
184 .clkdm_name = "wkupaon_clkdm",
185 .prcm = {
186 .omap4 = {
187 .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
188 .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
189 },
190 },
191};
192
193/*
194 * 'mpu_bus' class
195 * instance(s): mpu_private
196 */
197static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
198 .name = "mpu_bus",
199};
200
201/* mpu_private */
202static struct omap_hwmod omap54xx_mpu_private_hwmod = {
203 .name = "mpu_private",
204 .class = &omap54xx_mpu_bus_hwmod_class,
205 .clkdm_name = "mpu_clkdm",
206 .prcm = {
207 .omap4 = {
208 .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
209 },
210 },
211};
212
213/*
214 * 'counter' class
215 * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
216 */
217
218static struct omap_hwmod_class_sysconfig omap54xx_counter_sysc = {
219 .rev_offs = 0x0000,
220 .sysc_offs = 0x0010,
221 .sysc_flags = SYSC_HAS_SIDLEMODE,
222 .idlemodes = (SIDLE_FORCE | SIDLE_NO),
223 .sysc_fields = &omap_hwmod_sysc_type1,
224};
225
226static struct omap_hwmod_class omap54xx_counter_hwmod_class = {
227 .name = "counter",
228 .sysc = &omap54xx_counter_sysc,
229};
230
231/* counter_32k */
232static struct omap_hwmod omap54xx_counter_32k_hwmod = {
233 .name = "counter_32k",
234 .class = &omap54xx_counter_hwmod_class,
235 .clkdm_name = "wkupaon_clkdm",
236 .flags = HWMOD_SWSUP_SIDLE,
237 .main_clk = "wkupaon_iclk_mux",
238 .prcm = {
239 .omap4 = {
240 .clkctrl_offs = OMAP54XX_CM_WKUPAON_COUNTER_32K_CLKCTRL_OFFSET,
241 .context_offs = OMAP54XX_RM_WKUPAON_COUNTER_32K_CONTEXT_OFFSET,
242 },
243 },
244};
245
246/*
247 * 'dma' class
248 * dma controller for data exchange between memory to memory (i.e. internal or
249 * external memory) and gp peripherals to memory or memory to gp peripherals
250 */
251
252static struct omap_hwmod_class_sysconfig omap54xx_dma_sysc = {
253 .rev_offs = 0x0000,
254 .sysc_offs = 0x002c,
255 .syss_offs = 0x0028,
256 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
257 SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
258 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
259 SYSS_HAS_RESET_STATUS),
260 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
261 MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART),
262 .sysc_fields = &omap_hwmod_sysc_type1,
263};
264
265static struct omap_hwmod_class omap54xx_dma_hwmod_class = {
266 .name = "dma",
267 .sysc = &omap54xx_dma_sysc,
268};
269
270/* dma dev_attr */
271static struct omap_dma_dev_attr dma_dev_attr = {
272 .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY |
273 IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY,
274 .lch_count = 32,
275};
276
277/* dma_system */
278static struct omap_hwmod_irq_info omap54xx_dma_system_irqs[] = {
279 { .name = "0", .irq = 12 + OMAP54XX_IRQ_GIC_START },
280 { .name = "1", .irq = 13 + OMAP54XX_IRQ_GIC_START },
281 { .name = "2", .irq = 14 + OMAP54XX_IRQ_GIC_START },
282 { .name = "3", .irq = 15 + OMAP54XX_IRQ_GIC_START },
283 { .irq = -1 }
284};
285
286static struct omap_hwmod omap54xx_dma_system_hwmod = {
287 .name = "dma_system",
288 .class = &omap54xx_dma_hwmod_class,
289 .clkdm_name = "dma_clkdm",
290 .mpu_irqs = omap54xx_dma_system_irqs,
291 .main_clk = "l3_iclk_div",
292 .prcm = {
293 .omap4 = {
294 .clkctrl_offs = OMAP54XX_CM_DMA_DMA_SYSTEM_CLKCTRL_OFFSET,
295 .context_offs = OMAP54XX_RM_DMA_DMA_SYSTEM_CONTEXT_OFFSET,
296 },
297 },
298 .dev_attr = &dma_dev_attr,
299};
300
301/*
302 * 'dmic' class
303 * digital microphone controller
304 */
305
306static struct omap_hwmod_class_sysconfig omap54xx_dmic_sysc = {
307 .rev_offs = 0x0000,
308 .sysc_offs = 0x0010,
309 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
310 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
311 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
312 SIDLE_SMART_WKUP),
313 .sysc_fields = &omap_hwmod_sysc_type2,
314};
315
316static struct omap_hwmod_class omap54xx_dmic_hwmod_class = {
317 .name = "dmic",
318 .sysc = &omap54xx_dmic_sysc,
319};
320
321/* dmic */
322static struct omap_hwmod omap54xx_dmic_hwmod = {
323 .name = "dmic",
324 .class = &omap54xx_dmic_hwmod_class,
325 .clkdm_name = "abe_clkdm",
326 .main_clk = "dmic_gfclk",
327 .prcm = {
328 .omap4 = {
329 .clkctrl_offs = OMAP54XX_CM_ABE_DMIC_CLKCTRL_OFFSET,
330 .context_offs = OMAP54XX_RM_ABE_DMIC_CONTEXT_OFFSET,
331 .modulemode = MODULEMODE_SWCTRL,
332 },
333 },
334};
335
336/*
337 * 'emif' class
338 * external memory interface no1 (wrapper)
339 */
340
341static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
342 .rev_offs = 0x0000,
343};
344
345static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
346 .name = "emif",
347 .sysc = &omap54xx_emif_sysc,
348};
349
350/* emif1 */
351static struct omap_hwmod omap54xx_emif1_hwmod = {
352 .name = "emif1",
353 .class = &omap54xx_emif_hwmod_class,
354 .clkdm_name = "emif_clkdm",
355 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
356 .main_clk = "dpll_core_h11x2_ck",
357 .prcm = {
358 .omap4 = {
359 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
360 .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
361 .modulemode = MODULEMODE_HWCTRL,
362 },
363 },
364};
365
366/* emif2 */
367static struct omap_hwmod omap54xx_emif2_hwmod = {
368 .name = "emif2",
369 .class = &omap54xx_emif_hwmod_class,
370 .clkdm_name = "emif_clkdm",
371 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
372 .main_clk = "dpll_core_h11x2_ck",
373 .prcm = {
374 .omap4 = {
375 .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
376 .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
377 .modulemode = MODULEMODE_HWCTRL,
378 },
379 },
380};
381
382/*
383 * 'gpio' class
384 * general purpose io module
385 */
386
387static struct omap_hwmod_class_sysconfig omap54xx_gpio_sysc = {
388 .rev_offs = 0x0000,
389 .sysc_offs = 0x0010,
390 .syss_offs = 0x0114,
391 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
392 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
393 SYSS_HAS_RESET_STATUS),
394 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
395 SIDLE_SMART_WKUP),
396 .sysc_fields = &omap_hwmod_sysc_type1,
397};
398
399static struct omap_hwmod_class omap54xx_gpio_hwmod_class = {
400 .name = "gpio",
401 .sysc = &omap54xx_gpio_sysc,
402 .rev = 2,
403};
404
405/* gpio dev_attr */
406static struct omap_gpio_dev_attr gpio_dev_attr = {
407 .bank_width = 32,
408 .dbck_flag = true,
409};
410
411/* gpio1 */
412static struct omap_hwmod_opt_clk gpio1_opt_clks[] = {
413 { .role = "dbclk", .clk = "gpio1_dbclk" },
414};
415
416static struct omap_hwmod omap54xx_gpio1_hwmod = {
417 .name = "gpio1",
418 .class = &omap54xx_gpio_hwmod_class,
419 .clkdm_name = "wkupaon_clkdm",
420 .main_clk = "wkupaon_iclk_mux",
421 .prcm = {
422 .omap4 = {
423 .clkctrl_offs = OMAP54XX_CM_WKUPAON_GPIO1_CLKCTRL_OFFSET,
424 .context_offs = OMAP54XX_RM_WKUPAON_GPIO1_CONTEXT_OFFSET,
425 .modulemode = MODULEMODE_HWCTRL,
426 },
427 },
428 .opt_clks = gpio1_opt_clks,
429 .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
430 .dev_attr = &gpio_dev_attr,
431};
432
433/* gpio2 */
434static struct omap_hwmod_opt_clk gpio2_opt_clks[] = {
435 { .role = "dbclk", .clk = "gpio2_dbclk" },
436};
437
438static struct omap_hwmod omap54xx_gpio2_hwmod = {
439 .name = "gpio2",
440 .class = &omap54xx_gpio_hwmod_class,
441 .clkdm_name = "l4per_clkdm",
442 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
443 .main_clk = "l4_root_clk_div",
444 .prcm = {
445 .omap4 = {
446 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO2_CLKCTRL_OFFSET,
447 .context_offs = OMAP54XX_RM_L4PER_GPIO2_CONTEXT_OFFSET,
448 .modulemode = MODULEMODE_HWCTRL,
449 },
450 },
451 .opt_clks = gpio2_opt_clks,
452 .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
453 .dev_attr = &gpio_dev_attr,
454};
455
456/* gpio3 */
457static struct omap_hwmod_opt_clk gpio3_opt_clks[] = {
458 { .role = "dbclk", .clk = "gpio3_dbclk" },
459};
460
461static struct omap_hwmod omap54xx_gpio3_hwmod = {
462 .name = "gpio3",
463 .class = &omap54xx_gpio_hwmod_class,
464 .clkdm_name = "l4per_clkdm",
465 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
466 .main_clk = "l4_root_clk_div",
467 .prcm = {
468 .omap4 = {
469 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO3_CLKCTRL_OFFSET,
470 .context_offs = OMAP54XX_RM_L4PER_GPIO3_CONTEXT_OFFSET,
471 .modulemode = MODULEMODE_HWCTRL,
472 },
473 },
474 .opt_clks = gpio3_opt_clks,
475 .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
476 .dev_attr = &gpio_dev_attr,
477};
478
479/* gpio4 */
480static struct omap_hwmod_opt_clk gpio4_opt_clks[] = {
481 { .role = "dbclk", .clk = "gpio4_dbclk" },
482};
483
484static struct omap_hwmod omap54xx_gpio4_hwmod = {
485 .name = "gpio4",
486 .class = &omap54xx_gpio_hwmod_class,
487 .clkdm_name = "l4per_clkdm",
488 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
489 .main_clk = "l4_root_clk_div",
490 .prcm = {
491 .omap4 = {
492 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO4_CLKCTRL_OFFSET,
493 .context_offs = OMAP54XX_RM_L4PER_GPIO4_CONTEXT_OFFSET,
494 .modulemode = MODULEMODE_HWCTRL,
495 },
496 },
497 .opt_clks = gpio4_opt_clks,
498 .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
499 .dev_attr = &gpio_dev_attr,
500};
501
502/* gpio5 */
503static struct omap_hwmod_opt_clk gpio5_opt_clks[] = {
504 { .role = "dbclk", .clk = "gpio5_dbclk" },
505};
506
507static struct omap_hwmod omap54xx_gpio5_hwmod = {
508 .name = "gpio5",
509 .class = &omap54xx_gpio_hwmod_class,
510 .clkdm_name = "l4per_clkdm",
511 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
512 .main_clk = "l4_root_clk_div",
513 .prcm = {
514 .omap4 = {
515 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO5_CLKCTRL_OFFSET,
516 .context_offs = OMAP54XX_RM_L4PER_GPIO5_CONTEXT_OFFSET,
517 .modulemode = MODULEMODE_HWCTRL,
518 },
519 },
520 .opt_clks = gpio5_opt_clks,
521 .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
522 .dev_attr = &gpio_dev_attr,
523};
524
525/* gpio6 */
526static struct omap_hwmod_opt_clk gpio6_opt_clks[] = {
527 { .role = "dbclk", .clk = "gpio6_dbclk" },
528};
529
530static struct omap_hwmod omap54xx_gpio6_hwmod = {
531 .name = "gpio6",
532 .class = &omap54xx_gpio_hwmod_class,
533 .clkdm_name = "l4per_clkdm",
534 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
535 .main_clk = "l4_root_clk_div",
536 .prcm = {
537 .omap4 = {
538 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO6_CLKCTRL_OFFSET,
539 .context_offs = OMAP54XX_RM_L4PER_GPIO6_CONTEXT_OFFSET,
540 .modulemode = MODULEMODE_HWCTRL,
541 },
542 },
543 .opt_clks = gpio6_opt_clks,
544 .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
545 .dev_attr = &gpio_dev_attr,
546};
547
548/* gpio7 */
549static struct omap_hwmod_opt_clk gpio7_opt_clks[] = {
550 { .role = "dbclk", .clk = "gpio7_dbclk" },
551};
552
553static struct omap_hwmod omap54xx_gpio7_hwmod = {
554 .name = "gpio7",
555 .class = &omap54xx_gpio_hwmod_class,
556 .clkdm_name = "l4per_clkdm",
557 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
558 .main_clk = "l4_root_clk_div",
559 .prcm = {
560 .omap4 = {
561 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO7_CLKCTRL_OFFSET,
562 .context_offs = OMAP54XX_RM_L4PER_GPIO7_CONTEXT_OFFSET,
563 .modulemode = MODULEMODE_HWCTRL,
564 },
565 },
566 .opt_clks = gpio7_opt_clks,
567 .opt_clks_cnt = ARRAY_SIZE(gpio7_opt_clks),
568 .dev_attr = &gpio_dev_attr,
569};
570
571/* gpio8 */
572static struct omap_hwmod_opt_clk gpio8_opt_clks[] = {
573 { .role = "dbclk", .clk = "gpio8_dbclk" },
574};
575
576static struct omap_hwmod omap54xx_gpio8_hwmod = {
577 .name = "gpio8",
578 .class = &omap54xx_gpio_hwmod_class,
579 .clkdm_name = "l4per_clkdm",
580 .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET,
581 .main_clk = "l4_root_clk_div",
582 .prcm = {
583 .omap4 = {
584 .clkctrl_offs = OMAP54XX_CM_L4PER_GPIO8_CLKCTRL_OFFSET,
585 .context_offs = OMAP54XX_RM_L4PER_GPIO8_CONTEXT_OFFSET,
586 .modulemode = MODULEMODE_HWCTRL,
587 },
588 },
589 .opt_clks = gpio8_opt_clks,
590 .opt_clks_cnt = ARRAY_SIZE(gpio8_opt_clks),
591 .dev_attr = &gpio_dev_attr,
592};
593
594/*
595 * 'i2c' class
596 * multimaster high-speed i2c controller
597 */
598
599static struct omap_hwmod_class_sysconfig omap54xx_i2c_sysc = {
600 .sysc_offs = 0x0010,
601 .syss_offs = 0x0090,
602 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
603 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
604 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
605 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
606 SIDLE_SMART_WKUP),
607 .clockact = CLOCKACT_TEST_ICLK,
608 .sysc_fields = &omap_hwmod_sysc_type1,
609};
610
611static struct omap_hwmod_class omap54xx_i2c_hwmod_class = {
612 .name = "i2c",
613 .sysc = &omap54xx_i2c_sysc,
614 .reset = &omap_i2c_reset,
615 .rev = OMAP_I2C_IP_VERSION_2,
616};
617
618/* i2c dev_attr */
619static struct omap_i2c_dev_attr i2c_dev_attr = {
620 .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE,
621};
622
623/* i2c1 */
624static struct omap_hwmod omap54xx_i2c1_hwmod = {
625 .name = "i2c1",
626 .class = &omap54xx_i2c_hwmod_class,
627 .clkdm_name = "l4per_clkdm",
628 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
629 .main_clk = "func_96m_fclk",
630 .prcm = {
631 .omap4 = {
632 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C1_CLKCTRL_OFFSET,
633 .context_offs = OMAP54XX_RM_L4PER_I2C1_CONTEXT_OFFSET,
634 .modulemode = MODULEMODE_SWCTRL,
635 },
636 },
637 .dev_attr = &i2c_dev_attr,
638};
639
640/* i2c2 */
641static struct omap_hwmod omap54xx_i2c2_hwmod = {
642 .name = "i2c2",
643 .class = &omap54xx_i2c_hwmod_class,
644 .clkdm_name = "l4per_clkdm",
645 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
646 .main_clk = "func_96m_fclk",
647 .prcm = {
648 .omap4 = {
649 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C2_CLKCTRL_OFFSET,
650 .context_offs = OMAP54XX_RM_L4PER_I2C2_CONTEXT_OFFSET,
651 .modulemode = MODULEMODE_SWCTRL,
652 },
653 },
654 .dev_attr = &i2c_dev_attr,
655};
656
657/* i2c3 */
658static struct omap_hwmod omap54xx_i2c3_hwmod = {
659 .name = "i2c3",
660 .class = &omap54xx_i2c_hwmod_class,
661 .clkdm_name = "l4per_clkdm",
662 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
663 .main_clk = "func_96m_fclk",
664 .prcm = {
665 .omap4 = {
666 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C3_CLKCTRL_OFFSET,
667 .context_offs = OMAP54XX_RM_L4PER_I2C3_CONTEXT_OFFSET,
668 .modulemode = MODULEMODE_SWCTRL,
669 },
670 },
671 .dev_attr = &i2c_dev_attr,
672};
673
674/* i2c4 */
675static struct omap_hwmod omap54xx_i2c4_hwmod = {
676 .name = "i2c4",
677 .class = &omap54xx_i2c_hwmod_class,
678 .clkdm_name = "l4per_clkdm",
679 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
680 .main_clk = "func_96m_fclk",
681 .prcm = {
682 .omap4 = {
683 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C4_CLKCTRL_OFFSET,
684 .context_offs = OMAP54XX_RM_L4PER_I2C4_CONTEXT_OFFSET,
685 .modulemode = MODULEMODE_SWCTRL,
686 },
687 },
688 .dev_attr = &i2c_dev_attr,
689};
690
691/* i2c5 */
692static struct omap_hwmod omap54xx_i2c5_hwmod = {
693 .name = "i2c5",
694 .class = &omap54xx_i2c_hwmod_class,
695 .clkdm_name = "l4per_clkdm",
696 .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT,
697 .main_clk = "func_96m_fclk",
698 .prcm = {
699 .omap4 = {
700 .clkctrl_offs = OMAP54XX_CM_L4PER_I2C5_CLKCTRL_OFFSET,
701 .context_offs = OMAP54XX_RM_L4PER_I2C5_CONTEXT_OFFSET,
702 .modulemode = MODULEMODE_SWCTRL,
703 },
704 },
705 .dev_attr = &i2c_dev_attr,
706};
707
708/*
709 * 'kbd' class
710 * keyboard controller
711 */
712
713static struct omap_hwmod_class_sysconfig omap54xx_kbd_sysc = {
714 .rev_offs = 0x0000,
715 .sysc_offs = 0x0010,
716 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
717 SYSC_HAS_SOFTRESET),
718 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
719 .sysc_fields = &omap_hwmod_sysc_type1,
720};
721
722static struct omap_hwmod_class omap54xx_kbd_hwmod_class = {
723 .name = "kbd",
724 .sysc = &omap54xx_kbd_sysc,
725};
726
727/* kbd */
728static struct omap_hwmod omap54xx_kbd_hwmod = {
729 .name = "kbd",
730 .class = &omap54xx_kbd_hwmod_class,
731 .clkdm_name = "wkupaon_clkdm",
732 .main_clk = "sys_32k_ck",
733 .prcm = {
734 .omap4 = {
735 .clkctrl_offs = OMAP54XX_CM_WKUPAON_KBD_CLKCTRL_OFFSET,
736 .context_offs = OMAP54XX_RM_WKUPAON_KBD_CONTEXT_OFFSET,
737 .modulemode = MODULEMODE_SWCTRL,
738 },
739 },
740};
741
03ab349e
SA		 742/*
743 * 'mailbox' class
744 * mailbox module allowing communication between the on-chip processors using a
745 * queued mailbox-interrupt mechanism.
746 */
747
748static struct omap_hwmod_class_sysconfig omap54xx_mailbox_sysc = {
749 .rev_offs = 0x0000,
750 .sysc_offs = 0x0010,
751 .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
752 SYSC_HAS_SOFTRESET),
753 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
754 .sysc_fields = &omap_hwmod_sysc_type2,
755};
756
757static struct omap_hwmod_class omap54xx_mailbox_hwmod_class = {
758 .name = "mailbox",
759 .sysc = &omap54xx_mailbox_sysc,
760};
761
762/* mailbox */
763static struct omap_hwmod omap54xx_mailbox_hwmod = {
764 .name = "mailbox",
765 .class = &omap54xx_mailbox_hwmod_class,
766 .clkdm_name = "l4cfg_clkdm",
767 .prcm = {
768 .omap4 = {
769 .clkctrl_offs = OMAP54XX_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET,
770 .context_offs = OMAP54XX_RM_L4CFG_MAILBOX_CONTEXT_OFFSET,
771 },
772 },
773};
774
08e4830d
BC		 775/*
776 * 'mcbsp' class
777 * multi channel buffered serial port controller
778 */
779
780static struct omap_hwmod_class_sysconfig omap54xx_mcbsp_sysc = {
781 .sysc_offs = 0x008c,
782 .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP |
783 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
784 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
785 .sysc_fields = &omap_hwmod_sysc_type1,
786};
787
788static struct omap_hwmod_class omap54xx_mcbsp_hwmod_class = {
789 .name = "mcbsp",
790 .sysc = &omap54xx_mcbsp_sysc,
791 .rev = MCBSP_CONFIG_TYPE4,
792};
793
794/* mcbsp1 */
795static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = {
796 { .role = "pad_fck", .clk = "pad_clks_ck" },
797 { .role = "prcm_fck", .clk = "mcbsp1_sync_mux_ck" },
798};
799
800static struct omap_hwmod omap54xx_mcbsp1_hwmod = {
801 .name = "mcbsp1",
802 .class = &omap54xx_mcbsp_hwmod_class,
803 .clkdm_name = "abe_clkdm",
804 .main_clk = "mcbsp1_gfclk",
805 .prcm = {
806 .omap4 = {
807 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP1_CLKCTRL_OFFSET,
808 .context_offs = OMAP54XX_RM_ABE_MCBSP1_CONTEXT_OFFSET,
809 .modulemode = MODULEMODE_SWCTRL,
810 },
811 },
812 .opt_clks = mcbsp1_opt_clks,
813 .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks),
814};
815
816/* mcbsp2 */
817static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = {
818 { .role = "pad_fck", .clk = "pad_clks_ck" },
819 { .role = "prcm_fck", .clk = "mcbsp2_sync_mux_ck" },
820};
821
822static struct omap_hwmod omap54xx_mcbsp2_hwmod = {
823 .name = "mcbsp2",
824 .class = &omap54xx_mcbsp_hwmod_class,
825 .clkdm_name = "abe_clkdm",
826 .main_clk = "mcbsp2_gfclk",
827 .prcm = {
828 .omap4 = {
829 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP2_CLKCTRL_OFFSET,
830 .context_offs = OMAP54XX_RM_ABE_MCBSP2_CONTEXT_OFFSET,
831 .modulemode = MODULEMODE_SWCTRL,
832 },
833 },
834 .opt_clks = mcbsp2_opt_clks,
835 .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks),
836};
837
838/* mcbsp3 */
839static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = {
840 { .role = "pad_fck", .clk = "pad_clks_ck" },
841 { .role = "prcm_fck", .clk = "mcbsp3_sync_mux_ck" },
842};
843
844static struct omap_hwmod omap54xx_mcbsp3_hwmod = {
845 .name = "mcbsp3",
846 .class = &omap54xx_mcbsp_hwmod_class,
847 .clkdm_name = "abe_clkdm",
848 .main_clk = "mcbsp3_gfclk",
849 .prcm = {
850 .omap4 = {
851 .clkctrl_offs = OMAP54XX_CM_ABE_MCBSP3_CLKCTRL_OFFSET,
852 .context_offs = OMAP54XX_RM_ABE_MCBSP3_CONTEXT_OFFSET,
853 .modulemode = MODULEMODE_SWCTRL,
854 },
855 },
856 .opt_clks = mcbsp3_opt_clks,
857 .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks),
858};
859
860/*
861 * 'mcpdm' class
862 * multi channel pdm controller (proprietary interface with phoenix power
863 * ic)
864 */
865
866static struct omap_hwmod_class_sysconfig omap54xx_mcpdm_sysc = {
867 .rev_offs = 0x0000,
868 .sysc_offs = 0x0010,
869 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
870 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
871 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
872 SIDLE_SMART_WKUP),
873 .sysc_fields = &omap_hwmod_sysc_type2,
874};
875
876static struct omap_hwmod_class omap54xx_mcpdm_hwmod_class = {
877 .name = "mcpdm",
878 .sysc = &omap54xx_mcpdm_sysc,
879};
880
881/* mcpdm */
882static struct omap_hwmod omap54xx_mcpdm_hwmod = {
883 .name = "mcpdm",
884 .class = &omap54xx_mcpdm_hwmod_class,
885 .clkdm_name = "abe_clkdm",
886 /*
887 * It's suspected that the McPDM requires an off-chip main
888 * functional clock, controlled via I2C. This IP block is
889 * currently reset very early during boot, before I2C is
890 * available, so it doesn't seem that we have any choice in
891 * the kernel other than to avoid resetting it. XXX This is
892 * really a hardware issue workaround: every IP block should
893 * be able to source its main functional clock from either
894 * on-chip or off-chip sources. McPDM seems to be the only
895 * current exception.
896 */
897
898 .flags = HWMOD_EXT_OPT_MAIN_CLK,
899 .main_clk = "pad_clks_ck",
900 .prcm = {
901 .omap4 = {
902 .clkctrl_offs = OMAP54XX_CM_ABE_MCPDM_CLKCTRL_OFFSET,
903 .context_offs = OMAP54XX_RM_ABE_MCPDM_CONTEXT_OFFSET,
904 .modulemode = MODULEMODE_SWCTRL,
905 },
906 },
907};
908
909/*
910 * 'mcspi' class
911 * multichannel serial port interface (mcspi) / master/slave synchronous serial
912 * bus
913 */
914
915static struct omap_hwmod_class_sysconfig omap54xx_mcspi_sysc = {
916 .rev_offs = 0x0000,
917 .sysc_offs = 0x0010,
918 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
919 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
920 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
921 SIDLE_SMART_WKUP),
922 .sysc_fields = &omap_hwmod_sysc_type2,
923};
924
925static struct omap_hwmod_class omap54xx_mcspi_hwmod_class = {
926 .name = "mcspi",
927 .sysc = &omap54xx_mcspi_sysc,
928 .rev = OMAP4_MCSPI_REV,
929};
930
931/* mcspi1 */
932/* mcspi1 dev_attr */
933static struct omap2_mcspi_dev_attr mcspi1_dev_attr = {
934 .num_chipselect = 4,
935};
936
937static struct omap_hwmod omap54xx_mcspi1_hwmod = {
938 .name = "mcspi1",
939 .class = &omap54xx_mcspi_hwmod_class,
940 .clkdm_name = "l4per_clkdm",
941 .main_clk = "func_48m_fclk",
942 .prcm = {
943 .omap4 = {
944 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI1_CLKCTRL_OFFSET,
945 .context_offs = OMAP54XX_RM_L4PER_MCSPI1_CONTEXT_OFFSET,
946 .modulemode = MODULEMODE_SWCTRL,
947 },
948 },
949 .dev_attr = &mcspi1_dev_attr,
950};
951
952/* mcspi2 */
953/* mcspi2 dev_attr */
954static struct omap2_mcspi_dev_attr mcspi2_dev_attr = {
955 .num_chipselect = 2,
956};
957
958static struct omap_hwmod omap54xx_mcspi2_hwmod = {
959 .name = "mcspi2",
960 .class = &omap54xx_mcspi_hwmod_class,
961 .clkdm_name = "l4per_clkdm",
962 .main_clk = "func_48m_fclk",
963 .prcm = {
964 .omap4 = {
965 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI2_CLKCTRL_OFFSET,
966 .context_offs = OMAP54XX_RM_L4PER_MCSPI2_CONTEXT_OFFSET,
967 .modulemode = MODULEMODE_SWCTRL,
968 },
969 },
970 .dev_attr = &mcspi2_dev_attr,
971};
972
973/* mcspi3 */
974/* mcspi3 dev_attr */
975static struct omap2_mcspi_dev_attr mcspi3_dev_attr = {
976 .num_chipselect = 2,
977};
978
979static struct omap_hwmod omap54xx_mcspi3_hwmod = {
980 .name = "mcspi3",
981 .class = &omap54xx_mcspi_hwmod_class,
982 .clkdm_name = "l4per_clkdm",
983 .main_clk = "func_48m_fclk",
984 .prcm = {
985 .omap4 = {
986 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI3_CLKCTRL_OFFSET,
987 .context_offs = OMAP54XX_RM_L4PER_MCSPI3_CONTEXT_OFFSET,
988 .modulemode = MODULEMODE_SWCTRL,
989 },
990 },
991 .dev_attr = &mcspi3_dev_attr,
992};
993
994/* mcspi4 */
995/* mcspi4 dev_attr */
996static struct omap2_mcspi_dev_attr mcspi4_dev_attr = {
997 .num_chipselect = 1,
998};
999
1000static struct omap_hwmod omap54xx_mcspi4_hwmod = {
1001 .name = "mcspi4",
1002 .class = &omap54xx_mcspi_hwmod_class,
1003 .clkdm_name = "l4per_clkdm",
1004 .main_clk = "func_48m_fclk",
1005 .prcm = {
1006 .omap4 = {
1007 .clkctrl_offs = OMAP54XX_CM_L4PER_MCSPI4_CLKCTRL_OFFSET,
1008 .context_offs = OMAP54XX_RM_L4PER_MCSPI4_CONTEXT_OFFSET,
1009 .modulemode = MODULEMODE_SWCTRL,
1010 },
1011 },
1012 .dev_attr = &mcspi4_dev_attr,
1013};
1014
1015/*
1016 * 'mmc' class
1017 * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller
1018 */
1019
1020static struct omap_hwmod_class_sysconfig omap54xx_mmc_sysc = {
1021 .rev_offs = 0x0000,
1022 .sysc_offs = 0x0010,
1023 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE |
1024 SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE |
1025 SYSC_HAS_SOFTRESET),
1026 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1027 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1028 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1029 .sysc_fields = &omap_hwmod_sysc_type2,
1030};
1031
1032static struct omap_hwmod_class omap54xx_mmc_hwmod_class = {
1033 .name = "mmc",
1034 .sysc = &omap54xx_mmc_sysc,
1035};
1036
1037/* mmc1 */
1038static struct omap_hwmod_opt_clk mmc1_opt_clks[] = {
1039 { .role = "32khz_clk", .clk = "mmc1_32khz_clk" },
1040};
1041
1042/* mmc1 dev_attr */
1043static struct omap_mmc_dev_attr mmc1_dev_attr = {
1044 .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT,
1045};
1046
1047static struct omap_hwmod omap54xx_mmc1_hwmod = {
1048 .name = "mmc1",
1049 .class = &omap54xx_mmc_hwmod_class,
1050 .clkdm_name = "l3init_clkdm",
1051 .main_clk = "mmc1_fclk",
1052 .prcm = {
1053 .omap4 = {
1054 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC1_CLKCTRL_OFFSET,
1055 .context_offs = OMAP54XX_RM_L3INIT_MMC1_CONTEXT_OFFSET,
1056 .modulemode = MODULEMODE_SWCTRL,
1057 },
1058 },
1059 .opt_clks = mmc1_opt_clks,
1060 .opt_clks_cnt = ARRAY_SIZE(mmc1_opt_clks),
1061 .dev_attr = &mmc1_dev_attr,
1062};
1063
1064/* mmc2 */
1065static struct omap_hwmod omap54xx_mmc2_hwmod = {
1066 .name = "mmc2",
1067 .class = &omap54xx_mmc_hwmod_class,
1068 .clkdm_name = "l3init_clkdm",
1069 .main_clk = "mmc2_fclk",
1070 .prcm = {
1071 .omap4 = {
1072 .clkctrl_offs = OMAP54XX_CM_L3INIT_MMC2_CLKCTRL_OFFSET,
1073 .context_offs = OMAP54XX_RM_L3INIT_MMC2_CONTEXT_OFFSET,
1074 .modulemode = MODULEMODE_SWCTRL,
1075 },
1076 },
1077};
1078
1079/* mmc3 */
1080static struct omap_hwmod omap54xx_mmc3_hwmod = {
1081 .name = "mmc3",
1082 .class = &omap54xx_mmc_hwmod_class,
1083 .clkdm_name = "l4per_clkdm",
1084 .main_clk = "func_48m_fclk",
1085 .prcm = {
1086 .omap4 = {
1087 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC3_CLKCTRL_OFFSET,
1088 .context_offs = OMAP54XX_RM_L4PER_MMC3_CONTEXT_OFFSET,
1089 .modulemode = MODULEMODE_SWCTRL,
1090 },
1091 },
1092};
1093
1094/* mmc4 */
1095static struct omap_hwmod omap54xx_mmc4_hwmod = {
1096 .name = "mmc4",
1097 .class = &omap54xx_mmc_hwmod_class,
1098 .clkdm_name = "l4per_clkdm",
1099 .main_clk = "func_48m_fclk",
1100 .prcm = {
1101 .omap4 = {
1102 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC4_CLKCTRL_OFFSET,
1103 .context_offs = OMAP54XX_RM_L4PER_MMC4_CONTEXT_OFFSET,
1104 .modulemode = MODULEMODE_SWCTRL,
1105 },
1106 },
1107};
1108
1109/* mmc5 */
1110static struct omap_hwmod omap54xx_mmc5_hwmod = {
1111 .name = "mmc5",
1112 .class = &omap54xx_mmc_hwmod_class,
1113 .clkdm_name = "l4per_clkdm",
1114 .main_clk = "func_96m_fclk",
1115 .prcm = {
1116 .omap4 = {
1117 .clkctrl_offs = OMAP54XX_CM_L4PER_MMC5_CLKCTRL_OFFSET,
1118 .context_offs = OMAP54XX_RM_L4PER_MMC5_CONTEXT_OFFSET,
1119 .modulemode = MODULEMODE_SWCTRL,
1120 },
1121 },
1122};
1123
1124/*
1125 * 'mpu' class
1126 * mpu sub-system
1127 */
1128
1129static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
1130 .name = "mpu",
1131};
1132
1133/* mpu */
1134static struct omap_hwmod omap54xx_mpu_hwmod = {
1135 .name = "mpu",
1136 .class = &omap54xx_mpu_hwmod_class,
1137 .clkdm_name = "mpu_clkdm",
1138 .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
1139 .main_clk = "dpll_mpu_m2_ck",
1140 .prcm = {
1141 .omap4 = {
1142 .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
1143 .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
1144 },
1145 },
1146};
1147
325529d1
SA		 1148/*
1149 * 'spinlock' class
1150 * spinlock provides hardware assistance for synchronizing the processes
1151 * running on multiple processors
1152 */
1153
1154static struct omap_hwmod_class_sysconfig omap54xx_spinlock_sysc = {
1155 .rev_offs = 0x0000,
1156 .sysc_offs = 0x0010,
1157 .syss_offs = 0x0014,
1158 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1159 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1160 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1161 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1162 .sysc_fields = &omap_hwmod_sysc_type1,
1163};
1164
1165static struct omap_hwmod_class omap54xx_spinlock_hwmod_class = {
1166 .name = "spinlock",
1167 .sysc = &omap54xx_spinlock_sysc,
1168};
1169
1170/* spinlock */
1171static struct omap_hwmod omap54xx_spinlock_hwmod = {
1172 .name = "spinlock",
1173 .class = &omap54xx_spinlock_hwmod_class,
1174 .clkdm_name = "l4cfg_clkdm",
1175 .prcm = {
1176 .omap4 = {
1177 .clkctrl_offs = OMAP54XX_CM_L4CFG_SPINLOCK_CLKCTRL_OFFSET,
1178 .context_offs = OMAP54XX_RM_L4CFG_SPINLOCK_CONTEXT_OFFSET,
1179 },
1180 },
1181};
1182
08e4830d
BC		 1183/*
1184 * 'timer' class
1185 * general purpose timer module with accurate 1ms tick
1186 * This class contains several variants: ['timer_1ms', 'timer']
1187 */
1188
1189static struct omap_hwmod_class_sysconfig omap54xx_timer_1ms_sysc = {
1190 .rev_offs = 0x0000,
1191 .sysc_offs = 0x0010,
1192 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1193 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1194 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1195 SIDLE_SMART_WKUP),
1196 .sysc_fields = &omap_hwmod_sysc_type2,
1197 .clockact = CLOCKACT_TEST_ICLK,
1198};
1199
1200static struct omap_hwmod_class omap54xx_timer_1ms_hwmod_class = {
1201 .name = "timer",
1202 .sysc = &omap54xx_timer_1ms_sysc,
1203};
1204
1205static struct omap_hwmod_class_sysconfig omap54xx_timer_sysc = {
1206 .rev_offs = 0x0000,
1207 .sysc_offs = 0x0010,
1208 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS |
1209 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1210 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1211 SIDLE_SMART_WKUP),
1212 .sysc_fields = &omap_hwmod_sysc_type2,
1213};
1214
1215static struct omap_hwmod_class omap54xx_timer_hwmod_class = {
1216 .name = "timer",
1217 .sysc = &omap54xx_timer_sysc,
1218};
1219
1220/* timer1 */
1221static struct omap_hwmod omap54xx_timer1_hwmod = {
1222 .name = "timer1",
1223 .class = &omap54xx_timer_1ms_hwmod_class,
1224 .clkdm_name = "wkupaon_clkdm",
1225 .main_clk = "timer1_gfclk_mux",
1226 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1227 .prcm = {
1228 .omap4 = {
1229 .clkctrl_offs = OMAP54XX_CM_WKUPAON_TIMER1_CLKCTRL_OFFSET,
1230 .context_offs = OMAP54XX_RM_WKUPAON_TIMER1_CONTEXT_OFFSET,
1231 .modulemode = MODULEMODE_SWCTRL,
1232 },
1233 },
1234};
1235
1236/* timer2 */
1237static struct omap_hwmod omap54xx_timer2_hwmod = {
1238 .name = "timer2",
1239 .class = &omap54xx_timer_1ms_hwmod_class,
1240 .clkdm_name = "l4per_clkdm",
1241 .main_clk = "timer2_gfclk_mux",
1242 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1243 .prcm = {
1244 .omap4 = {
1245 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER2_CLKCTRL_OFFSET,
1246 .context_offs = OMAP54XX_RM_L4PER_TIMER2_CONTEXT_OFFSET,
1247 .modulemode = MODULEMODE_SWCTRL,
1248 },
1249 },
1250};
1251
1252/* timer3 */
1253static struct omap_hwmod omap54xx_timer3_hwmod = {
1254 .name = "timer3",
1255 .class = &omap54xx_timer_hwmod_class,
1256 .clkdm_name = "l4per_clkdm",
1257 .main_clk = "timer3_gfclk_mux",
1258 .prcm = {
1259 .omap4 = {
1260 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER3_CLKCTRL_OFFSET,
1261 .context_offs = OMAP54XX_RM_L4PER_TIMER3_CONTEXT_OFFSET,
1262 .modulemode = MODULEMODE_SWCTRL,
1263 },
1264 },
1265};
1266
1267/* timer4 */
1268static struct omap_hwmod omap54xx_timer4_hwmod = {
1269 .name = "timer4",
1270 .class = &omap54xx_timer_hwmod_class,
1271 .clkdm_name = "l4per_clkdm",
1272 .main_clk = "timer4_gfclk_mux",
1273 .prcm = {
1274 .omap4 = {
1275 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER4_CLKCTRL_OFFSET,
1276 .context_offs = OMAP54XX_RM_L4PER_TIMER4_CONTEXT_OFFSET,
1277 .modulemode = MODULEMODE_SWCTRL,
1278 },
1279 },
1280};
1281
1282/* timer5 */
1283static struct omap_hwmod omap54xx_timer5_hwmod = {
1284 .name = "timer5",
1285 .class = &omap54xx_timer_hwmod_class,
1286 .clkdm_name = "abe_clkdm",
1287 .main_clk = "timer5_gfclk_mux",
1288 .prcm = {
1289 .omap4 = {
1290 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER5_CLKCTRL_OFFSET,
1291 .context_offs = OMAP54XX_RM_ABE_TIMER5_CONTEXT_OFFSET,
1292 .modulemode = MODULEMODE_SWCTRL,
1293 },
1294 },
1295};
1296
1297/* timer6 */
1298static struct omap_hwmod omap54xx_timer6_hwmod = {
1299 .name = "timer6",
1300 .class = &omap54xx_timer_hwmod_class,
1301 .clkdm_name = "abe_clkdm",
1302 .main_clk = "timer6_gfclk_mux",
1303 .prcm = {
1304 .omap4 = {
1305 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER6_CLKCTRL_OFFSET,
1306 .context_offs = OMAP54XX_RM_ABE_TIMER6_CONTEXT_OFFSET,
1307 .modulemode = MODULEMODE_SWCTRL,
1308 },
1309 },
1310};
1311
1312/* timer7 */
1313static struct omap_hwmod omap54xx_timer7_hwmod = {
1314 .name = "timer7",
1315 .class = &omap54xx_timer_hwmod_class,
1316 .clkdm_name = "abe_clkdm",
1317 .main_clk = "timer7_gfclk_mux",
1318 .prcm = {
1319 .omap4 = {
1320 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER7_CLKCTRL_OFFSET,
1321 .context_offs = OMAP54XX_RM_ABE_TIMER7_CONTEXT_OFFSET,
1322 .modulemode = MODULEMODE_SWCTRL,
1323 },
1324 },
1325};
1326
1327/* timer8 */
1328static struct omap_hwmod omap54xx_timer8_hwmod = {
1329 .name = "timer8",
1330 .class = &omap54xx_timer_hwmod_class,
1331 .clkdm_name = "abe_clkdm",
1332 .main_clk = "timer8_gfclk_mux",
1333 .prcm = {
1334 .omap4 = {
1335 .clkctrl_offs = OMAP54XX_CM_ABE_TIMER8_CLKCTRL_OFFSET,
1336 .context_offs = OMAP54XX_RM_ABE_TIMER8_CONTEXT_OFFSET,
1337 .modulemode = MODULEMODE_SWCTRL,
1338 },
1339 },
1340};
1341
1342/* timer9 */
1343static struct omap_hwmod omap54xx_timer9_hwmod = {
1344 .name = "timer9",
1345 .class = &omap54xx_timer_hwmod_class,
1346 .clkdm_name = "l4per_clkdm",
1347 .main_clk = "timer9_gfclk_mux",
1348 .prcm = {
1349 .omap4 = {
1350 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER9_CLKCTRL_OFFSET,
1351 .context_offs = OMAP54XX_RM_L4PER_TIMER9_CONTEXT_OFFSET,
1352 .modulemode = MODULEMODE_SWCTRL,
1353 },
1354 },
1355};
1356
1357/* timer10 */
1358static struct omap_hwmod omap54xx_timer10_hwmod = {
1359 .name = "timer10",
1360 .class = &omap54xx_timer_1ms_hwmod_class,
1361 .clkdm_name = "l4per_clkdm",
1362 .main_clk = "timer10_gfclk_mux",
1363 .flags = HWMOD_SET_DEFAULT_CLOCKACT,
1364 .prcm = {
1365 .omap4 = {
1366 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER10_CLKCTRL_OFFSET,
1367 .context_offs = OMAP54XX_RM_L4PER_TIMER10_CONTEXT_OFFSET,
1368 .modulemode = MODULEMODE_SWCTRL,
1369 },
1370 },
1371};
1372
1373/* timer11 */
1374static struct omap_hwmod omap54xx_timer11_hwmod = {
1375 .name = "timer11",
1376 .class = &omap54xx_timer_hwmod_class,
1377 .clkdm_name = "l4per_clkdm",
1378 .main_clk = "timer11_gfclk_mux",
1379 .prcm = {
1380 .omap4 = {
1381 .clkctrl_offs = OMAP54XX_CM_L4PER_TIMER11_CLKCTRL_OFFSET,
1382 .context_offs = OMAP54XX_RM_L4PER_TIMER11_CONTEXT_OFFSET,
1383 .modulemode = MODULEMODE_SWCTRL,
1384 },
1385 },
1386};
1387
1388/*
1389 * 'uart' class
1390 * universal asynchronous receiver/transmitter (uart)
1391 */
1392
1393static struct omap_hwmod_class_sysconfig omap54xx_uart_sysc = {
1394 .rev_offs = 0x0050,
1395 .sysc_offs = 0x0054,
1396 .syss_offs = 0x0058,
1397 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP |
1398 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
1399 SYSS_HAS_RESET_STATUS),
1400 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1401 SIDLE_SMART_WKUP),
1402 .sysc_fields = &omap_hwmod_sysc_type1,
1403};
1404
1405static struct omap_hwmod_class omap54xx_uart_hwmod_class = {
1406 .name = "uart",
1407 .sysc = &omap54xx_uart_sysc,
1408};
1409
1410/* uart1 */
1411static struct omap_hwmod omap54xx_uart1_hwmod = {
1412 .name = "uart1",
1413 .class = &omap54xx_uart_hwmod_class,
1414 .clkdm_name = "l4per_clkdm",
1415 .main_clk = "func_48m_fclk",
1416 .prcm = {
1417 .omap4 = {
1418 .clkctrl_offs = OMAP54XX_CM_L4PER_UART1_CLKCTRL_OFFSET,
1419 .context_offs = OMAP54XX_RM_L4PER_UART1_CONTEXT_OFFSET,
1420 .modulemode = MODULEMODE_SWCTRL,
1421 },
1422 },
1423};
1424
1425/* uart2 */
1426static struct omap_hwmod omap54xx_uart2_hwmod = {
1427 .name = "uart2",
1428 .class = &omap54xx_uart_hwmod_class,
1429 .clkdm_name = "l4per_clkdm",
1430 .main_clk = "func_48m_fclk",
1431 .prcm = {
1432 .omap4 = {
1433 .clkctrl_offs = OMAP54XX_CM_L4PER_UART2_CLKCTRL_OFFSET,
1434 .context_offs = OMAP54XX_RM_L4PER_UART2_CONTEXT_OFFSET,
1435 .modulemode = MODULEMODE_SWCTRL,
1436 },
1437 },
1438};
1439
1440/* uart3 */
1441static struct omap_hwmod omap54xx_uart3_hwmod = {
1442 .name = "uart3",
1443 .class = &omap54xx_uart_hwmod_class,
1444 .clkdm_name = "l4per_clkdm",
7dedd346 1445 .flags = DEBUG_OMAP4UART3_FLAGS,
08e4830d
BC		 1446 .main_clk = "func_48m_fclk",
1447 .prcm = {
1448 .omap4 = {
1449 .clkctrl_offs = OMAP54XX_CM_L4PER_UART3_CLKCTRL_OFFSET,
1450 .context_offs = OMAP54XX_RM_L4PER_UART3_CONTEXT_OFFSET,
1451 .modulemode = MODULEMODE_SWCTRL,
1452 },
1453 },
1454};
1455
1456/* uart4 */
1457static struct omap_hwmod omap54xx_uart4_hwmod = {
1458 .name = "uart4",
1459 .class = &omap54xx_uart_hwmod_class,
1460 .clkdm_name = "l4per_clkdm",
7dedd346 1461 .flags = DEBUG_OMAP4UART4_FLAGS,
08e4830d
BC		 1462 .main_clk = "func_48m_fclk",
1463 .prcm = {
1464 .omap4 = {
1465 .clkctrl_offs = OMAP54XX_CM_L4PER_UART4_CLKCTRL_OFFSET,
1466 .context_offs = OMAP54XX_RM_L4PER_UART4_CONTEXT_OFFSET,
1467 .modulemode = MODULEMODE_SWCTRL,
1468 },
1469 },
1470};
1471
1472/* uart5 */
1473static struct omap_hwmod omap54xx_uart5_hwmod = {
1474 .name = "uart5",
1475 .class = &omap54xx_uart_hwmod_class,
1476 .clkdm_name = "l4per_clkdm",
1477 .main_clk = "func_48m_fclk",
1478 .prcm = {
1479 .omap4 = {
1480 .clkctrl_offs = OMAP54XX_CM_L4PER_UART5_CLKCTRL_OFFSET,
1481 .context_offs = OMAP54XX_RM_L4PER_UART5_CONTEXT_OFFSET,
1482 .modulemode = MODULEMODE_SWCTRL,
1483 },
1484 },
1485};
1486
1487/* uart6 */
1488static struct omap_hwmod omap54xx_uart6_hwmod = {
1489 .name = "uart6",
1490 .class = &omap54xx_uart_hwmod_class,
1491 .clkdm_name = "l4per_clkdm",
1492 .main_clk = "func_48m_fclk",
1493 .prcm = {
1494 .omap4 = {
1495 .clkctrl_offs = OMAP54XX_CM_L4PER_UART6_CLKCTRL_OFFSET,
1496 .context_offs = OMAP54XX_RM_L4PER_UART6_CONTEXT_OFFSET,
1497 .modulemode = MODULEMODE_SWCTRL,
1498 },
1499 },
1500};
1501
e01478b0
RQ		 1502/*
1503 * 'usb_host_hs' class
1504 * high-speed multi-port usb host controller
1505 */
1506
1507static struct omap_hwmod_class_sysconfig omap54xx_usb_host_hs_sysc = {
1508 .rev_offs = 0x0000,
1509 .sysc_offs = 0x0010,
1510 .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
1511 SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
1512 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1513 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1514 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1515 .sysc_fields = &omap_hwmod_sysc_type2,
1516};
1517
1518static struct omap_hwmod_class omap54xx_usb_host_hs_hwmod_class = {
1519 .name = "usb_host_hs",
1520 .sysc = &omap54xx_usb_host_hs_sysc,
1521};
1522
1523static struct omap_hwmod omap54xx_usb_host_hs_hwmod = {
1524 .name = "usb_host_hs",
1525 .class = &omap54xx_usb_host_hs_hwmod_class,
1526 .clkdm_name = "l3init_clkdm",
1527 /*
1528 * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
1529 * id: i660
1530 *
1531 * Description:
1532 * In the following configuration :
1533 * - USBHOST module is set to smart-idle mode
1534 * - PRCM asserts idle_req to the USBHOST module ( This typically
1535 * happens when the system is going to a low power mode : all ports
1536 * have been suspended, the master part of the USBHOST module has
1537 * entered the standby state, and SW has cut the functional clocks)
1538 * - an USBHOST interrupt occurs before the module is able to answer
1539 * idle_ack, typically a remote wakeup IRQ.
1540 * Then the USB HOST module will enter a deadlock situation where it
1541 * is no more accessible nor functional.
1542 *
1543 * Workaround:
1544 * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE
1545 */
1546
1547 /*
1548 * Errata: USB host EHCI may stall when entering smart-standby mode
1549 * Id: i571
1550 *
1551 * Description:
1552 * When the USBHOST module is set to smart-standby mode, and when it is
1553 * ready to enter the standby state (i.e. all ports are suspended and
1554 * all attached devices are in suspend mode), then it can wrongly assert
1555 * the Mstandby signal too early while there are still some residual OCP
1556 * transactions ongoing. If this condition occurs, the internal state
1557 * machine may go to an undefined state and the USB link may be stuck
1558 * upon the next resume.
1559 *
1560 * Workaround:
1561 * Don't use smart standby; use only force standby,
1562 * hence HWMOD_SWSUP_MSTANDBY
1563 */
1564
1565 /*
1566 * During system boot; If the hwmod framework resets the module
1567 * the module will have smart idle settings; which can lead to deadlock
1568 * (above Errata Id:i660); so, dont reset the module during boot;
1569 * Use HWMOD_INIT_NO_RESET.
1570 */
1571
1572 .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY |
1573 HWMOD_INIT_NO_RESET,
1574 .main_clk = "l3init_60m_fclk",
1575 .prcm = {
1576 .omap4 = {
1577 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_HOST_HS_CLKCTRL_OFFSET,
1578 .context_offs = OMAP54XX_RM_L3INIT_USB_HOST_HS_CONTEXT_OFFSET,
1579 .modulemode = MODULEMODE_SWCTRL,
1580 },
1581 },
1582};
1583
1584/*
1585 * 'usb_tll_hs' class
1586 * usb_tll_hs module is the adapter on the usb_host_hs ports
1587 */
1588
1589static struct omap_hwmod_class_sysconfig omap54xx_usb_tll_hs_sysc = {
1590 .rev_offs = 0x0000,
1591 .sysc_offs = 0x0010,
1592 .syss_offs = 0x0014,
1593 .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY |
1594 SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE |
1595 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1596 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
1597 .sysc_fields = &omap_hwmod_sysc_type1,
1598};
1599
1600static struct omap_hwmod_class omap54xx_usb_tll_hs_hwmod_class = {
1601 .name = "usb_tll_hs",
1602 .sysc = &omap54xx_usb_tll_hs_sysc,
1603};
1604
1605static struct omap_hwmod omap54xx_usb_tll_hs_hwmod = {
1606 .name = "usb_tll_hs",
1607 .class = &omap54xx_usb_tll_hs_hwmod_class,
1608 .clkdm_name = "l3init_clkdm",
1609 .main_clk = "l4_root_clk_div",
1610 .prcm = {
1611 .omap4 = {
1612 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_TLL_HS_CLKCTRL_OFFSET,
1613 .context_offs = OMAP54XX_RM_L3INIT_USB_TLL_HS_CONTEXT_OFFSET,
1614 .modulemode = MODULEMODE_HWCTRL,
1615 },
1616 },
1617};
1618
08e4830d
BC		 1619/*
1620 * 'usb_otg_ss' class
1621 * 2.0 super speed (usb_otg_ss) controller
1622 */
1623
1624static struct omap_hwmod_class_sysconfig omap54xx_usb_otg_ss_sysc = {
1625 .rev_offs = 0x0000,
1626 .sysc_offs = 0x0010,
1627 .sysc_flags = (SYSC_HAS_DMADISABLE | SYSC_HAS_MIDLEMODE |
1628 SYSC_HAS_SIDLEMODE),
1629 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1630 SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
1631 MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
1632 .sysc_fields = &omap_hwmod_sysc_type2,
1633};
1634
1635static struct omap_hwmod_class omap54xx_usb_otg_ss_hwmod_class = {
1636 .name = "usb_otg_ss",
1637 .sysc = &omap54xx_usb_otg_ss_sysc,
1638};
1639
1640/* usb_otg_ss */
1641static struct omap_hwmod_opt_clk usb_otg_ss_opt_clks[] = {
1642 { .role = "refclk960m", .clk = "usb_otg_ss_refclk960m" },
1643};
1644
1645static struct omap_hwmod omap54xx_usb_otg_ss_hwmod = {
1646 .name = "usb_otg_ss",
1647 .class = &omap54xx_usb_otg_ss_hwmod_class,
1648 .clkdm_name = "l3init_clkdm",
1649 .flags = HWMOD_SWSUP_SIDLE,
1650 .main_clk = "dpll_core_h13x2_ck",
1651 .prcm = {
1652 .omap4 = {
1653 .clkctrl_offs = OMAP54XX_CM_L3INIT_USB_OTG_SS_CLKCTRL_OFFSET,
1654 .context_offs = OMAP54XX_RM_L3INIT_USB_OTG_SS_CONTEXT_OFFSET,
1655 .modulemode = MODULEMODE_HWCTRL,
1656 },
1657 },
1658 .opt_clks = usb_otg_ss_opt_clks,
1659 .opt_clks_cnt = ARRAY_SIZE(usb_otg_ss_opt_clks),
1660};
1661
1662/*
1663 * 'wd_timer' class
1664 * 32-bit watchdog upward counter that generates a pulse on the reset pin on
1665 * overflow condition
1666 */
1667
1668static struct omap_hwmod_class_sysconfig omap54xx_wd_timer_sysc = {
1669 .rev_offs = 0x0000,
1670 .sysc_offs = 0x0010,
1671 .syss_offs = 0x0014,
1672 .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE |
1673 SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
1674 .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
1675 SIDLE_SMART_WKUP),
1676 .sysc_fields = &omap_hwmod_sysc_type1,
1677};
1678
1679static struct omap_hwmod_class omap54xx_wd_timer_hwmod_class = {
1680 .name = "wd_timer",
1681 .sysc = &omap54xx_wd_timer_sysc,
1682 .pre_shutdown = &omap2_wd_timer_disable,
1683};
1684
1685/* wd_timer2 */
1686static struct omap_hwmod omap54xx_wd_timer2_hwmod = {
1687 .name = "wd_timer2",
1688 .class = &omap54xx_wd_timer_hwmod_class,
1689 .clkdm_name = "wkupaon_clkdm",
1690 .main_clk = "sys_32k_ck",
1691 .prcm = {
1692 .omap4 = {
1693 .clkctrl_offs = OMAP54XX_CM_WKUPAON_WD_TIMER2_CLKCTRL_OFFSET,
1694 .context_offs = OMAP54XX_RM_WKUPAON_WD_TIMER2_CONTEXT_OFFSET,
1695 .modulemode = MODULEMODE_SWCTRL,
1696 },
1697 },
1698};
1699
1700
1701/*
1702 * Interfaces
1703 */
1704
1705/* l3_main_1 -> dmm */
1706static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
1707 .master = &omap54xx_l3_main_1_hwmod,
1708 .slave = &omap54xx_dmm_hwmod,
1709 .clk = "l3_iclk_div",
1710 .user = OCP_USER_SDMA,
1711};
1712
1713/* l3_main_3 -> l3_instr */
1714static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
1715 .master = &omap54xx_l3_main_3_hwmod,
1716 .slave = &omap54xx_l3_instr_hwmod,
1717 .clk = "l3_iclk_div",
1718 .user = OCP_USER_MPU | OCP_USER_SDMA,
1719};
1720
1721/* l3_main_2 -> l3_main_1 */
1722static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
1723 .master = &omap54xx_l3_main_2_hwmod,
1724 .slave = &omap54xx_l3_main_1_hwmod,
1725 .clk = "l3_iclk_div",
1726 .user = OCP_USER_MPU | OCP_USER_SDMA,
1727};
1728
1729/* l4_cfg -> l3_main_1 */
1730static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
1731 .master = &omap54xx_l4_cfg_hwmod,
1732 .slave = &omap54xx_l3_main_1_hwmod,
1733 .clk = "l3_iclk_div",
1734 .user = OCP_USER_MPU | OCP_USER_SDMA,
1735};
1736
1737/* mpu -> l3_main_1 */
1738static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
1739 .master = &omap54xx_mpu_hwmod,
1740 .slave = &omap54xx_l3_main_1_hwmod,
1741 .clk = "l3_iclk_div",
1742 .user = OCP_USER_MPU,
1743};
1744
1745/* l3_main_1 -> l3_main_2 */
1746static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
1747 .master = &omap54xx_l3_main_1_hwmod,
1748 .slave = &omap54xx_l3_main_2_hwmod,
1749 .clk = "l3_iclk_div",
1750 .user = OCP_USER_MPU,
1751};
1752
1753/* l4_cfg -> l3_main_2 */
1754static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
1755 .master = &omap54xx_l4_cfg_hwmod,
1756 .slave = &omap54xx_l3_main_2_hwmod,
1757 .clk = "l3_iclk_div",
1758 .user = OCP_USER_MPU | OCP_USER_SDMA,
1759};
1760
1761/* l3_main_1 -> l3_main_3 */
1762static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
1763 .master = &omap54xx_l3_main_1_hwmod,
1764 .slave = &omap54xx_l3_main_3_hwmod,
1765 .clk = "l3_iclk_div",
1766 .user = OCP_USER_MPU,
1767};
1768
1769/* l3_main_2 -> l3_main_3 */
1770static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
1771 .master = &omap54xx_l3_main_2_hwmod,
1772 .slave = &omap54xx_l3_main_3_hwmod,
1773 .clk = "l3_iclk_div",
1774 .user = OCP_USER_MPU | OCP_USER_SDMA,
1775};
1776
1777/* l4_cfg -> l3_main_3 */
1778static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
1779 .master = &omap54xx_l4_cfg_hwmod,
1780 .slave = &omap54xx_l3_main_3_hwmod,
1781 .clk = "l3_iclk_div",
1782 .user = OCP_USER_MPU | OCP_USER_SDMA,
1783};
1784
1785/* l3_main_1 -> l4_abe */
1786static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_abe = {
1787 .master = &omap54xx_l3_main_1_hwmod,
1788 .slave = &omap54xx_l4_abe_hwmod,
1789 .clk = "abe_iclk",
1790 .user = OCP_USER_MPU | OCP_USER_SDMA,
1791};
1792
1793/* mpu -> l4_abe */
1794static struct omap_hwmod_ocp_if omap54xx_mpu__l4_abe = {
1795 .master = &omap54xx_mpu_hwmod,
1796 .slave = &omap54xx_l4_abe_hwmod,
1797 .clk = "abe_iclk",
1798 .user = OCP_USER_MPU | OCP_USER_SDMA,
1799};
1800
1801/* l3_main_1 -> l4_cfg */
1802static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
1803 .master = &omap54xx_l3_main_1_hwmod,
1804 .slave = &omap54xx_l4_cfg_hwmod,
1805 .clk = "l4_root_clk_div",
1806 .user = OCP_USER_MPU | OCP_USER_SDMA,
1807};
1808
1809/* l3_main_2 -> l4_per */
1810static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
1811 .master = &omap54xx_l3_main_2_hwmod,
1812 .slave = &omap54xx_l4_per_hwmod,
1813 .clk = "l4_root_clk_div",
1814 .user = OCP_USER_MPU | OCP_USER_SDMA,
1815};
1816
1817/* l3_main_1 -> l4_wkup */
1818static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
1819 .master = &omap54xx_l3_main_1_hwmod,
1820 .slave = &omap54xx_l4_wkup_hwmod,
1821 .clk = "wkupaon_iclk_mux",
1822 .user = OCP_USER_MPU | OCP_USER_SDMA,
1823};
1824
1825/* mpu -> mpu_private */
1826static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
1827 .master = &omap54xx_mpu_hwmod,
1828 .slave = &omap54xx_mpu_private_hwmod,
1829 .clk = "l3_iclk_div",
1830 .user = OCP_USER_MPU | OCP_USER_SDMA,
1831};
1832
1833/* l4_wkup -> counter_32k */
1834static struct omap_hwmod_ocp_if omap54xx_l4_wkup__counter_32k = {
1835 .master = &omap54xx_l4_wkup_hwmod,
1836 .slave = &omap54xx_counter_32k_hwmod,
1837 .clk = "wkupaon_iclk_mux",
1838 .user = OCP_USER_MPU | OCP_USER_SDMA,
1839};
1840
1841static struct omap_hwmod_addr_space omap54xx_dma_system_addrs[] = {
1842 {
1843 .pa_start = 0x4a056000,
1844 .pa_end = 0x4a056fff,
1845 .flags = ADDR_TYPE_RT
1846 },
1847 { }
1848};
1849
1850/* l4_cfg -> dma_system */
1851static struct omap_hwmod_ocp_if omap54xx_l4_cfg__dma_system = {
1852 .master = &omap54xx_l4_cfg_hwmod,
1853 .slave = &omap54xx_dma_system_hwmod,
1854 .clk = "l4_root_clk_div",
1855 .addr = omap54xx_dma_system_addrs,
1856 .user = OCP_USER_MPU | OCP_USER_SDMA,
1857};
1858
1859/* l4_abe -> dmic */
1860static struct omap_hwmod_ocp_if omap54xx_l4_abe__dmic = {
1861 .master = &omap54xx_l4_abe_hwmod,
1862 .slave = &omap54xx_dmic_hwmod,
1863 .clk = "abe_iclk",
1864 .user = OCP_USER_MPU,
1865};
1866
1867/* mpu -> emif1 */
1868static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
1869 .master = &omap54xx_mpu_hwmod,
1870 .slave = &omap54xx_emif1_hwmod,
1871 .clk = "dpll_core_h11x2_ck",
1872 .user = OCP_USER_MPU | OCP_USER_SDMA,
1873};
1874
1875/* mpu -> emif2 */
1876static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
1877 .master = &omap54xx_mpu_hwmod,
1878 .slave = &omap54xx_emif2_hwmod,
1879 .clk = "dpll_core_h11x2_ck",
1880 .user = OCP_USER_MPU | OCP_USER_SDMA,
1881};
1882
1883/* l4_wkup -> gpio1 */
1884static struct omap_hwmod_ocp_if omap54xx_l4_wkup__gpio1 = {
1885 .master = &omap54xx_l4_wkup_hwmod,
1886 .slave = &omap54xx_gpio1_hwmod,
1887 .clk = "wkupaon_iclk_mux",
1888 .user = OCP_USER_MPU | OCP_USER_SDMA,
1889};
1890
1891/* l4_per -> gpio2 */
1892static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio2 = {
1893 .master = &omap54xx_l4_per_hwmod,
1894 .slave = &omap54xx_gpio2_hwmod,
1895 .clk = "l4_root_clk_div",
1896 .user = OCP_USER_MPU | OCP_USER_SDMA,
1897};
1898
1899/* l4_per -> gpio3 */
1900static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio3 = {
1901 .master = &omap54xx_l4_per_hwmod,
1902 .slave = &omap54xx_gpio3_hwmod,
1903 .clk = "l4_root_clk_div",
1904 .user = OCP_USER_MPU | OCP_USER_SDMA,
1905};
1906
1907/* l4_per -> gpio4 */
1908static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio4 = {
1909 .master = &omap54xx_l4_per_hwmod,
1910 .slave = &omap54xx_gpio4_hwmod,
1911 .clk = "l4_root_clk_div",
1912 .user = OCP_USER_MPU | OCP_USER_SDMA,
1913};
1914
1915/* l4_per -> gpio5 */
1916static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio5 = {
1917 .master = &omap54xx_l4_per_hwmod,
1918 .slave = &omap54xx_gpio5_hwmod,
1919 .clk = "l4_root_clk_div",
1920 .user = OCP_USER_MPU | OCP_USER_SDMA,
1921};
1922
1923/* l4_per -> gpio6 */
1924static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio6 = {
1925 .master = &omap54xx_l4_per_hwmod,
1926 .slave = &omap54xx_gpio6_hwmod,
1927 .clk = "l4_root_clk_div",
1928 .user = OCP_USER_MPU | OCP_USER_SDMA,
1929};
1930
1931/* l4_per -> gpio7 */
1932static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio7 = {
1933 .master = &omap54xx_l4_per_hwmod,
1934 .slave = &omap54xx_gpio7_hwmod,
1935 .clk = "l4_root_clk_div",
1936 .user = OCP_USER_MPU | OCP_USER_SDMA,
1937};
1938
1939/* l4_per -> gpio8 */
1940static struct omap_hwmod_ocp_if omap54xx_l4_per__gpio8 = {
1941 .master = &omap54xx_l4_per_hwmod,
1942 .slave = &omap54xx_gpio8_hwmod,
1943 .clk = "l4_root_clk_div",
1944 .user = OCP_USER_MPU | OCP_USER_SDMA,
1945};
1946
1947/* l4_per -> i2c1 */
1948static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c1 = {
1949 .master = &omap54xx_l4_per_hwmod,
1950 .slave = &omap54xx_i2c1_hwmod,
1951 .clk = "l4_root_clk_div",
1952 .user = OCP_USER_MPU | OCP_USER_SDMA,
1953};
1954
1955/* l4_per -> i2c2 */
1956static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c2 = {
1957 .master = &omap54xx_l4_per_hwmod,
1958 .slave = &omap54xx_i2c2_hwmod,
1959 .clk = "l4_root_clk_div",
1960 .user = OCP_USER_MPU | OCP_USER_SDMA,
1961};
1962
1963/* l4_per -> i2c3 */
1964static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c3 = {
1965 .master = &omap54xx_l4_per_hwmod,
1966 .slave = &omap54xx_i2c3_hwmod,
1967 .clk = "l4_root_clk_div",
1968 .user = OCP_USER_MPU | OCP_USER_SDMA,
1969};
1970
1971/* l4_per -> i2c4 */
1972static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c4 = {
1973 .master = &omap54xx_l4_per_hwmod,
1974 .slave = &omap54xx_i2c4_hwmod,
1975 .clk = "l4_root_clk_div",
1976 .user = OCP_USER_MPU | OCP_USER_SDMA,
1977};
1978
1979/* l4_per -> i2c5 */
1980static struct omap_hwmod_ocp_if omap54xx_l4_per__i2c5 = {
1981 .master = &omap54xx_l4_per_hwmod,
1982 .slave = &omap54xx_i2c5_hwmod,
1983 .clk = "l4_root_clk_div",
1984 .user = OCP_USER_MPU | OCP_USER_SDMA,
1985};
1986
1987/* l4_wkup -> kbd */
1988static struct omap_hwmod_ocp_if omap54xx_l4_wkup__kbd = {
1989 .master = &omap54xx_l4_wkup_hwmod,
1990 .slave = &omap54xx_kbd_hwmod,
1991 .clk = "wkupaon_iclk_mux",
1992 .user = OCP_USER_MPU | OCP_USER_SDMA,
1993};
1994
03ab349e
SA		 1995/* l4_cfg -> mailbox */
1996static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mailbox = {
1997 .master = &omap54xx_l4_cfg_hwmod,
1998 .slave = &omap54xx_mailbox_hwmod,
1999 .clk = "l4_root_clk_div",
2000 .user = OCP_USER_MPU | OCP_USER_SDMA,
2001};
2002
08e4830d
BC		 2003/* l4_abe -> mcbsp1 */
2004static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp1 = {
2005 .master = &omap54xx_l4_abe_hwmod,
2006 .slave = &omap54xx_mcbsp1_hwmod,
2007 .clk = "abe_iclk",
2008 .user = OCP_USER_MPU,
2009};
2010
2011/* l4_abe -> mcbsp2 */
2012static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp2 = {
2013 .master = &omap54xx_l4_abe_hwmod,
2014 .slave = &omap54xx_mcbsp2_hwmod,
2015 .clk = "abe_iclk",
2016 .user = OCP_USER_MPU,
2017};
2018
2019/* l4_abe -> mcbsp3 */
2020static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcbsp3 = {
2021 .master = &omap54xx_l4_abe_hwmod,
2022 .slave = &omap54xx_mcbsp3_hwmod,
2023 .clk = "abe_iclk",
2024 .user = OCP_USER_MPU,
2025};
2026
2027/* l4_abe -> mcpdm */
2028static struct omap_hwmod_ocp_if omap54xx_l4_abe__mcpdm = {
2029 .master = &omap54xx_l4_abe_hwmod,
2030 .slave = &omap54xx_mcpdm_hwmod,
2031 .clk = "abe_iclk",
2032 .user = OCP_USER_MPU,
2033};
2034
2035/* l4_per -> mcspi1 */
2036static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi1 = {
2037 .master = &omap54xx_l4_per_hwmod,
2038 .slave = &omap54xx_mcspi1_hwmod,
2039 .clk = "l4_root_clk_div",
2040 .user = OCP_USER_MPU | OCP_USER_SDMA,
2041};
2042
2043/* l4_per -> mcspi2 */
2044static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi2 = {
2045 .master = &omap54xx_l4_per_hwmod,
2046 .slave = &omap54xx_mcspi2_hwmod,
2047 .clk = "l4_root_clk_div",
2048 .user = OCP_USER_MPU | OCP_USER_SDMA,
2049};
2050
2051/* l4_per -> mcspi3 */
2052static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi3 = {
2053 .master = &omap54xx_l4_per_hwmod,
2054 .slave = &omap54xx_mcspi3_hwmod,
2055 .clk = "l4_root_clk_div",
2056 .user = OCP_USER_MPU | OCP_USER_SDMA,
2057};
2058
2059/* l4_per -> mcspi4 */
2060static struct omap_hwmod_ocp_if omap54xx_l4_per__mcspi4 = {
2061 .master = &omap54xx_l4_per_hwmod,
2062 .slave = &omap54xx_mcspi4_hwmod,
2063 .clk = "l4_root_clk_div",
2064 .user = OCP_USER_MPU | OCP_USER_SDMA,
2065};
2066
2067/* l4_per -> mmc1 */
2068static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc1 = {
2069 .master = &omap54xx_l4_per_hwmod,
2070 .slave = &omap54xx_mmc1_hwmod,
2071 .clk = "l3_iclk_div",
2072 .user = OCP_USER_MPU | OCP_USER_SDMA,
2073};
2074
2075/* l4_per -> mmc2 */
2076static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc2 = {
2077 .master = &omap54xx_l4_per_hwmod,
2078 .slave = &omap54xx_mmc2_hwmod,
2079 .clk = "l3_iclk_div",
2080 .user = OCP_USER_MPU | OCP_USER_SDMA,
2081};
2082
2083/* l4_per -> mmc3 */
2084static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc3 = {
2085 .master = &omap54xx_l4_per_hwmod,
2086 .slave = &omap54xx_mmc3_hwmod,
2087 .clk = "l4_root_clk_div",
2088 .user = OCP_USER_MPU | OCP_USER_SDMA,
2089};
2090
2091/* l4_per -> mmc4 */
2092static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc4 = {
2093 .master = &omap54xx_l4_per_hwmod,
2094 .slave = &omap54xx_mmc4_hwmod,
2095 .clk = "l4_root_clk_div",
2096 .user = OCP_USER_MPU | OCP_USER_SDMA,
2097};
2098
2099/* l4_per -> mmc5 */
2100static struct omap_hwmod_ocp_if omap54xx_l4_per__mmc5 = {
2101 .master = &omap54xx_l4_per_hwmod,
2102 .slave = &omap54xx_mmc5_hwmod,
2103 .clk = "l4_root_clk_div",
2104 .user = OCP_USER_MPU | OCP_USER_SDMA,
2105};
2106
2107/* l4_cfg -> mpu */
2108static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
2109 .master = &omap54xx_l4_cfg_hwmod,
2110 .slave = &omap54xx_mpu_hwmod,
2111 .clk = "l4_root_clk_div",
2112 .user = OCP_USER_MPU | OCP_USER_SDMA,
2113};
2114
325529d1
SA		 2115/* l4_cfg -> spinlock */
2116static struct omap_hwmod_ocp_if omap54xx_l4_cfg__spinlock = {
2117 .master = &omap54xx_l4_cfg_hwmod,
2118 .slave = &omap54xx_spinlock_hwmod,
2119 .clk = "l4_root_clk_div",
2120 .user = OCP_USER_MPU | OCP_USER_SDMA,
2121};
2122
08e4830d
BC		 2123/* l4_wkup -> timer1 */
2124static struct omap_hwmod_ocp_if omap54xx_l4_wkup__timer1 = {
2125 .master = &omap54xx_l4_wkup_hwmod,
2126 .slave = &omap54xx_timer1_hwmod,
2127 .clk = "wkupaon_iclk_mux",
2128 .user = OCP_USER_MPU | OCP_USER_SDMA,
2129};
2130
2131/* l4_per -> timer2 */
2132static struct omap_hwmod_ocp_if omap54xx_l4_per__timer2 = {
2133 .master = &omap54xx_l4_per_hwmod,
2134 .slave = &omap54xx_timer2_hwmod,
2135 .clk = "l4_root_clk_div",
2136 .user = OCP_USER_MPU | OCP_USER_SDMA,
2137};
2138
2139/* l4_per -> timer3 */
2140static struct omap_hwmod_ocp_if omap54xx_l4_per__timer3 = {
2141 .master = &omap54xx_l4_per_hwmod,
2142 .slave = &omap54xx_timer3_hwmod,
2143 .clk = "l4_root_clk_div",
2144 .user = OCP_USER_MPU | OCP_USER_SDMA,
2145};
2146
2147/* l4_per -> timer4 */
2148static struct omap_hwmod_ocp_if omap54xx_l4_per__timer4 = {
2149 .master = &omap54xx_l4_per_hwmod,
2150 .slave = &omap54xx_timer4_hwmod,
2151 .clk = "l4_root_clk_div",
2152 .user = OCP_USER_MPU | OCP_USER_SDMA,
2153};
2154
2155/* l4_abe -> timer5 */
2156static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer5 = {
2157 .master = &omap54xx_l4_abe_hwmod,
2158 .slave = &omap54xx_timer5_hwmod,
2159 .clk = "abe_iclk",
2160 .user = OCP_USER_MPU,
2161};
2162
2163/* l4_abe -> timer6 */
2164static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer6 = {
2165 .master = &omap54xx_l4_abe_hwmod,
2166 .slave = &omap54xx_timer6_hwmod,
2167 .clk = "abe_iclk",
2168 .user = OCP_USER_MPU,
2169};
2170
2171/* l4_abe -> timer7 */
2172static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer7 = {
2173 .master = &omap54xx_l4_abe_hwmod,
2174 .slave = &omap54xx_timer7_hwmod,
2175 .clk = "abe_iclk",
2176 .user = OCP_USER_MPU,
2177};
2178
2179/* l4_abe -> timer8 */
2180static struct omap_hwmod_ocp_if omap54xx_l4_abe__timer8 = {
2181 .master = &omap54xx_l4_abe_hwmod,
2182 .slave = &omap54xx_timer8_hwmod,
2183 .clk = "abe_iclk",
2184 .user = OCP_USER_MPU,
2185};
2186
2187/* l4_per -> timer9 */
2188static struct omap_hwmod_ocp_if omap54xx_l4_per__timer9 = {
2189 .master = &omap54xx_l4_per_hwmod,
2190 .slave = &omap54xx_timer9_hwmod,
2191 .clk = "l4_root_clk_div",
2192 .user = OCP_USER_MPU | OCP_USER_SDMA,
2193};
2194
2195/* l4_per -> timer10 */
2196static struct omap_hwmod_ocp_if omap54xx_l4_per__timer10 = {
2197 .master = &omap54xx_l4_per_hwmod,
2198 .slave = &omap54xx_timer10_hwmod,
2199 .clk = "l4_root_clk_div",
2200 .user = OCP_USER_MPU | OCP_USER_SDMA,
2201};
2202
2203/* l4_per -> timer11 */
2204static struct omap_hwmod_ocp_if omap54xx_l4_per__timer11 = {
2205 .master = &omap54xx_l4_per_hwmod,
2206 .slave = &omap54xx_timer11_hwmod,
2207 .clk = "l4_root_clk_div",
2208 .user = OCP_USER_MPU | OCP_USER_SDMA,
2209};
2210
2211/* l4_per -> uart1 */
2212static struct omap_hwmod_ocp_if omap54xx_l4_per__uart1 = {
2213 .master = &omap54xx_l4_per_hwmod,
2214 .slave = &omap54xx_uart1_hwmod,
2215 .clk = "l4_root_clk_div",
2216 .user = OCP_USER_MPU | OCP_USER_SDMA,
2217};
2218
2219/* l4_per -> uart2 */
2220static struct omap_hwmod_ocp_if omap54xx_l4_per__uart2 = {
2221 .master = &omap54xx_l4_per_hwmod,
2222 .slave = &omap54xx_uart2_hwmod,
2223 .clk = "l4_root_clk_div",
2224 .user = OCP_USER_MPU | OCP_USER_SDMA,
2225};
2226
2227/* l4_per -> uart3 */
2228static struct omap_hwmod_ocp_if omap54xx_l4_per__uart3 = {
2229 .master = &omap54xx_l4_per_hwmod,
2230 .slave = &omap54xx_uart3_hwmod,
2231 .clk = "l4_root_clk_div",
2232 .user = OCP_USER_MPU | OCP_USER_SDMA,
2233};
2234
2235/* l4_per -> uart4 */
2236static struct omap_hwmod_ocp_if omap54xx_l4_per__uart4 = {
2237 .master = &omap54xx_l4_per_hwmod,
2238 .slave = &omap54xx_uart4_hwmod,
2239 .clk = "l4_root_clk_div",
2240 .user = OCP_USER_MPU | OCP_USER_SDMA,
2241};
2242
2243/* l4_per -> uart5 */
2244static struct omap_hwmod_ocp_if omap54xx_l4_per__uart5 = {
2245 .master = &omap54xx_l4_per_hwmod,
2246 .slave = &omap54xx_uart5_hwmod,
2247 .clk = "l4_root_clk_div",
2248 .user = OCP_USER_MPU | OCP_USER_SDMA,
2249};
2250
2251/* l4_per -> uart6 */
2252static struct omap_hwmod_ocp_if omap54xx_l4_per__uart6 = {
2253 .master = &omap54xx_l4_per_hwmod,
2254 .slave = &omap54xx_uart6_hwmod,
2255 .clk = "l4_root_clk_div",
2256 .user = OCP_USER_MPU | OCP_USER_SDMA,
2257};
2258
e01478b0
RQ		 2259/* l4_cfg -> usb_host_hs */
2260static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_host_hs = {
2261 .master = &omap54xx_l4_cfg_hwmod,
2262 .slave = &omap54xx_usb_host_hs_hwmod,
2263 .clk = "l3_iclk_div",
2264 .user = OCP_USER_MPU | OCP_USER_SDMA,
2265};
2266
2267/* l4_cfg -> usb_tll_hs */
2268static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_tll_hs = {
2269 .master = &omap54xx_l4_cfg_hwmod,
2270 .slave = &omap54xx_usb_tll_hs_hwmod,
2271 .clk = "l4_root_clk_div",
2272 .user = OCP_USER_MPU | OCP_USER_SDMA,
2273};
2274
08e4830d
BC		 2275/* l4_cfg -> usb_otg_ss */
2276static struct omap_hwmod_ocp_if omap54xx_l4_cfg__usb_otg_ss = {
2277 .master = &omap54xx_l4_cfg_hwmod,
2278 .slave = &omap54xx_usb_otg_ss_hwmod,
2279 .clk = "dpll_core_h13x2_ck",
2280 .user = OCP_USER_MPU | OCP_USER_SDMA,
2281};
2282
2283/* l4_wkup -> wd_timer2 */
2284static struct omap_hwmod_ocp_if omap54xx_l4_wkup__wd_timer2 = {
2285 .master = &omap54xx_l4_wkup_hwmod,
2286 .slave = &omap54xx_wd_timer2_hwmod,
2287 .clk = "wkupaon_iclk_mux",
2288 .user = OCP_USER_MPU | OCP_USER_SDMA,
2289};
2290
2291static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
2292 &omap54xx_l3_main_1__dmm,
2293 &omap54xx_l3_main_3__l3_instr,
2294 &omap54xx_l3_main_2__l3_main_1,
2295 &omap54xx_l4_cfg__l3_main_1,
2296 &omap54xx_mpu__l3_main_1,
2297 &omap54xx_l3_main_1__l3_main_2,
2298 &omap54xx_l4_cfg__l3_main_2,
2299 &omap54xx_l3_main_1__l3_main_3,
2300 &omap54xx_l3_main_2__l3_main_3,
2301 &omap54xx_l4_cfg__l3_main_3,
2302 &omap54xx_l3_main_1__l4_abe,
2303 &omap54xx_mpu__l4_abe,
2304 &omap54xx_l3_main_1__l4_cfg,
2305 &omap54xx_l3_main_2__l4_per,
2306 &omap54xx_l3_main_1__l4_wkup,
2307 &omap54xx_mpu__mpu_private,
2308 &omap54xx_l4_wkup__counter_32k,
2309 &omap54xx_l4_cfg__dma_system,
2310 &omap54xx_l4_abe__dmic,
2311 &omap54xx_mpu__emif1,
2312 &omap54xx_mpu__emif2,
2313 &omap54xx_l4_wkup__gpio1,
2314 &omap54xx_l4_per__gpio2,
2315 &omap54xx_l4_per__gpio3,
2316 &omap54xx_l4_per__gpio4,
2317 &omap54xx_l4_per__gpio5,
2318 &omap54xx_l4_per__gpio6,
2319 &omap54xx_l4_per__gpio7,
2320 &omap54xx_l4_per__gpio8,
2321 &omap54xx_l4_per__i2c1,
2322 &omap54xx_l4_per__i2c2,
2323 &omap54xx_l4_per__i2c3,
2324 &omap54xx_l4_per__i2c4,
2325 &omap54xx_l4_per__i2c5,
2326 &omap54xx_l4_wkup__kbd,
03ab349e 2327 &omap54xx_l4_cfg__mailbox,
08e4830d
BC		 2328 &omap54xx_l4_abe__mcbsp1,
2329 &omap54xx_l4_abe__mcbsp2,
2330 &omap54xx_l4_abe__mcbsp3,
2331 &omap54xx_l4_abe__mcpdm,
2332 &omap54xx_l4_per__mcspi1,
2333 &omap54xx_l4_per__mcspi2,
2334 &omap54xx_l4_per__mcspi3,
2335 &omap54xx_l4_per__mcspi4,
2336 &omap54xx_l4_per__mmc1,
2337 &omap54xx_l4_per__mmc2,
2338 &omap54xx_l4_per__mmc3,
2339 &omap54xx_l4_per__mmc4,
2340 &omap54xx_l4_per__mmc5,
2341 &omap54xx_l4_cfg__mpu,
325529d1 2342 &omap54xx_l4_cfg__spinlock,
08e4830d
BC		 2343 &omap54xx_l4_wkup__timer1,
2344 &omap54xx_l4_per__timer2,
2345 &omap54xx_l4_per__timer3,
2346 &omap54xx_l4_per__timer4,
2347 &omap54xx_l4_abe__timer5,
2348 &omap54xx_l4_abe__timer6,
2349 &omap54xx_l4_abe__timer7,
2350 &omap54xx_l4_abe__timer8,
2351 &omap54xx_l4_per__timer9,
2352 &omap54xx_l4_per__timer10,
2353 &omap54xx_l4_per__timer11,
2354 &omap54xx_l4_per__uart1,
2355 &omap54xx_l4_per__uart2,
2356 &omap54xx_l4_per__uart3,
2357 &omap54xx_l4_per__uart4,
2358 &omap54xx_l4_per__uart5,
2359 &omap54xx_l4_per__uart6,
e01478b0
RQ		 2360 &omap54xx_l4_cfg__usb_host_hs,
2361 &omap54xx_l4_cfg__usb_tll_hs,
08e4830d
BC		 2362 &omap54xx_l4_cfg__usb_otg_ss,
2363 &omap54xx_l4_wkup__wd_timer2,
2364 NULL,
2365};
2366
2367int __init omap54xx_hwmod_init(void)
2368{
2369 omap_hwmod_init();
2370 return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
2371}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git