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OMAP2+: powerdomain: add voltage domain lookup during register
[thirdparty/kernel/stable.git] / arch / arm / mach-omap2 / powerdomain.h
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ad67ef68 1/*
a64bb9cd 2 * OMAP2/3/4 powerdomain control
ad67ef68 3 *
72e06d08 4 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
694606c4 5 * Copyright (C) 2007-2011 Nokia Corporation
ad67ef68 6 *
72e06d08 7 * Paul Walmsley
ad67ef68
PW		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
6e01478a
PW		 12 *
13 * XXX This should be moved to the mach-omap2/ directory at the earliest
14 * opportunity.
ad67ef68
PW		 15 */
16
72e06d08
PW		 17#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
18#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
ad67ef68
PW		 19
20#include <linux/types.h>
21#include <linux/list.h>
22
72e06d08 23#include <linux/atomic.h>
ad67ef68 24
ce491cf8 25#include <plat/cpu.h>
ad67ef68 26
8f1bec24
KH		 27#include "voltage.h"
28
ad67ef68
PW		 29/* Powerdomain basic power states */
30#define PWRDM_POWER_OFF 0x0
31#define PWRDM_POWER_RET 0x1
32#define PWRDM_POWER_INACTIVE 0x2
33#define PWRDM_POWER_ON 0x3
34
2354eb5a
PW		 35#define PWRDM_MAX_PWRSTS 4
36
ad67ef68 37/* Powerdomain allowable state bitfields */
d3353e16 38#define PWRSTS_ON (1 << PWRDM_POWER_ON)
694606c4
PW		 39#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
40#define PWRSTS_RET (1 << PWRDM_POWER_RET)
bb722f33 41#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
ad67ef68 42
694606c4
PW		 43#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
44#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
45#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
46#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
ad67ef68
PW		 47
48
0b7cbfb5
PW		 49/* Powerdomain flags */
50#define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */
3863c74b
TG		 51#define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits
52 * in MEM bank 1 position. This is
53 * true for OMAP3430
54 */
90dbc7b0
RN		 55#define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /*
56 * support to transition from a
57 * sleep state to a lower sleep
58 * state without waking up the
59 * powerdomain
60 */
0b7cbfb5 61
ad67ef68 62/*
38900c27
AP		 63 * Number of memory banks that are power-controllable. On OMAP4430, the
64 * maximum is 5.
ad67ef68 65 */
38900c27 66#define PWRDM_MAX_MEM_BANKS 5
ad67ef68 67
8420bb13
PW		 68/*
69 * Maximum number of clockdomains that can be associated with a powerdomain.
38900c27 70 * CORE powerdomain on OMAP4 is the worst case
8420bb13 71 */
38900c27 72#define PWRDM_MAX_CLKDMS 9
8420bb13 73
ad67ef68
PW		 74/* XXX A completely arbitrary number. What is reasonable here? */
75#define PWRDM_TRANSITION_BAILOUT 100000
76
8420bb13 77struct clockdomain;
ad67ef68
PW		 78struct powerdomain;
79
f0271d65
PW		 80/**
81 * struct powerdomain - OMAP powerdomain
82 * @name: Powerdomain name
8f1bec24 83 * @voltdm: voltagedomain containing this powerdomain
f0271d65 84 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
a64bb9cd 85 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
f0271d65
PW		 86 * @pwrsts: Possible powerdomain power states
87 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
88 * @flags: Powerdomain flags
89 * @banks: Number of software-controllable memory banks in this powerdomain
90 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
91 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
92 * @pwrdm_clkdms: Clockdomains in this powerdomain
93 * @node: list_head linking all powerdomains
94 * @state:
95 * @state_counter:
96 * @timer:
97 * @state_timer:
a64bb9cd
PW		 98 *
99 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
f0271d65 100 */
ad67ef68 101struct powerdomain {
ad67ef68 102 const char *name;
8f1bec24
KH		 103 union {
104 const char *name;
105 struct voltagedomain *ptr;
106 } voltdm;
e0594b44 107 const s16 prcm_offs;
ad67ef68 108 const u8 pwrsts;
ad67ef68 109 const u8 pwrsts_logic_ret;
0b7cbfb5 110 const u8 flags;
ad67ef68 111 const u8 banks;
ad67ef68 112 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
ad67ef68 113 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
a64bb9cd 114 const u8 prcm_partition;
8420bb13 115 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
ad67ef68 116 struct list_head node;
ba20bb12 117 int state;
2354eb5a 118 unsigned state_counter[PWRDM_MAX_PWRSTS];
cde08f81
TG		 119 unsigned ret_logic_off_counter;
120 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
331b93f4
PDS		 121
122#ifdef CONFIG_PM_DEBUG
123 s64 timer;
2354eb5a 124 s64 state_timer[PWRDM_MAX_PWRSTS];
331b93f4 125#endif
ad67ef68
PW		 126};
127
3b1e8b21 128/**
25985edc 129 * struct pwrdm_ops - Arch specific function implementations
3b1e8b21
RN		 130 * @pwrdm_set_next_pwrst: Set the target power state for a pd
131 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
132 * @pwrdm_read_pwrst: Read the current power state of a pd
133 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
134 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
135 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
136 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
137 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
138 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
139 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
140 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
141 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
142 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
143 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
144 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
145 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
146 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
147 * @pwrdm_wait_transition: Wait for a pd state transition to complete
148 */
149struct pwrdm_ops {
150 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
151 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
152 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
153 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
154 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
155 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
156 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
157 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
158 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
159 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
160 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
161 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
162 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
163 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
164 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
165 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
166 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
167 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
168};
ad67ef68 169
129c65ee
PW		 170int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
171int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
172int pwrdm_complete_init(void);
ad67ef68 173
ad67ef68
PW		 174struct powerdomain *pwrdm_lookup(const char *name);
175
a23456e9
PDS		 176int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
177 void *user);
ee894b18
AB		 178int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
179 void *user);
ad67ef68 180
8420bb13
PW		 181int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
182int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
183int pwrdm_for_each_clkdm(struct powerdomain *pwrdm,
184 int (*fn)(struct powerdomain *pwrdm,
185 struct clockdomain *clkdm));
048a7034 186struct voltagedomain *pwrdm_get_voltdm(struct powerdomain *pwrdm);
8420bb13 187
ad67ef68
PW		 188int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
189
190int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
191int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
fecb494b 192int pwrdm_read_pwrst(struct powerdomain *pwrdm);
ad67ef68
PW		 193int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
194int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
195
196int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
197int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
198int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
199
200int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
201int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
1e3d0d2b 202int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
ad67ef68
PW		 203int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
204int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
1e3d0d2b 205int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
ad67ef68 206
0b7cbfb5
PW		 207int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
208int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
209bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
210
ad67ef68
PW		 211int pwrdm_wait_transition(struct powerdomain *pwrdm);
212
ba20bb12
PDS		 213int pwrdm_state_switch(struct powerdomain *pwrdm);
214int pwrdm_clkdm_state_switch(struct clockdomain *clkdm);
215int pwrdm_pre_transition(void);
216int pwrdm_post_transition(void);
04aeae77 217int pwrdm_set_lowpwrstchange(struct powerdomain *pwrdm);
7f595674 218u32 pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
694606c4 219bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
ba20bb12 220
8179488a
PW		 221extern void omap242x_powerdomains_init(void);
222extern void omap243x_powerdomains_init(void);
6e01478a
PW		 223extern void omap3xxx_powerdomains_init(void);
224extern void omap44xx_powerdomains_init(void);
225
72e06d08
PW		 226extern struct pwrdm_ops omap2_pwrdm_operations;
227extern struct pwrdm_ops omap3_pwrdm_operations;
228extern struct pwrdm_ops omap4_pwrdm_operations;
229
230/* Common Internal functions used across OMAP rev's */
231extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
232extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
233extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
234
235extern struct powerdomain wkup_omap2_pwrdm;
236extern struct powerdomain gfx_omap2_pwrdm;
237
238
ad67ef68 239#endif
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git