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[thirdparty/kernel/stable.git] / arch / arm / mach-omap2 / powerdomain.h
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d2912cb1 1/* SPDX-License-Identifier: GPL-2.0-only */
ad67ef68 2/*
a64bb9cd 3 * OMAP2/3/4 powerdomain control
ad67ef68 4 *
72e06d08 5 * Copyright (C) 2007-2008, 2010 Texas Instruments, Inc.
694606c4 6 * Copyright (C) 2007-2011 Nokia Corporation
ad67ef68 7 *
72e06d08 8 * Paul Walmsley
ad67ef68 9 *
6e01478a
PW		 10 * XXX This should be moved to the mach-omap2/ directory at the earliest
11 * opportunity.
ad67ef68
PW		 12 */
13
72e06d08
PW		 14#ifndef __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
15#define __ARCH_ARM_MACH_OMAP2_POWERDOMAIN_H
ad67ef68
PW		 16
17#include <linux/types.h>
18#include <linux/list.h>
3a090284 19#include <linux/spinlock.h>
ad67ef68 20
ad67ef68
PW		 21/* Powerdomain basic power states */
22#define PWRDM_POWER_OFF 0x0
23#define PWRDM_POWER_RET 0x1
24#define PWRDM_POWER_INACTIVE 0x2
25#define PWRDM_POWER_ON 0x3
26
2354eb5a
PW		 27#define PWRDM_MAX_PWRSTS 4
28
ad67ef68 29/* Powerdomain allowable state bitfields */
d3353e16 30#define PWRSTS_ON (1 << PWRDM_POWER_ON)
694606c4
PW		 31#define PWRSTS_INACTIVE (1 << PWRDM_POWER_INACTIVE)
32#define PWRSTS_RET (1 << PWRDM_POWER_RET)
bb722f33 33#define PWRSTS_OFF (1 << PWRDM_POWER_OFF)
ad67ef68 34
694606c4
PW		 35#define PWRSTS_OFF_ON (PWRSTS_OFF | PWRSTS_ON)
36#define PWRSTS_OFF_RET (PWRSTS_OFF | PWRSTS_RET)
37#define PWRSTS_RET_ON (PWRSTS_RET | PWRSTS_ON)
38#define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | PWRSTS_ON)
cafc8cb5 39#define PWRSTS_INA_ON (PWRSTS_INACTIVE | PWRSTS_ON)
ad67ef68
PW		 40
41
562e54d1
PW		 42/*
43 * Powerdomain flags (struct powerdomain.flags)
44 *
45 * PWRDM_HAS_HDWR_SAR - powerdomain has hardware save-and-restore support
46 *
47 * PWRDM_HAS_MPU_QUIRK - MPU pwr domain has MEM bank 0 bits in MEM
48 * bank 1 position. This is true for OMAP3430
49 *
50 * PWRDM_HAS_LOWPOWERSTATECHANGE - can transition from a sleep state
51 * to a lower sleep state without waking up the powerdomain
52 */
53#define PWRDM_HAS_HDWR_SAR BIT(0)
54#define PWRDM_HAS_MPU_QUIRK BIT(1)
55#define PWRDM_HAS_LOWPOWERSTATECHANGE BIT(2)
0b7cbfb5 56
ad67ef68 57/*
38900c27
AP		 58 * Number of memory banks that are power-controllable. On OMAP4430, the
59 * maximum is 5.
ad67ef68 60 */
38900c27 61#define PWRDM_MAX_MEM_BANKS 5
ad67ef68 62
8420bb13
PW		 63/*
64 * Maximum number of clockdomains that can be associated with a powerdomain.
3f0ea764 65 * PER powerdomain on AM33XX is the worst case
8420bb13 66 */
3f0ea764 67#define PWRDM_MAX_CLKDMS 11
8420bb13 68
ad67ef68
PW		 69/* XXX A completely arbitrary number. What is reasonable here? */
70#define PWRDM_TRANSITION_BAILOUT 100000
71
8420bb13 72struct clockdomain;
ad67ef68 73struct powerdomain;
4794208c 74struct voltagedomain;
ad67ef68 75
f0271d65
PW		 76/**
77 * struct powerdomain - OMAP powerdomain
78 * @name: Powerdomain name
8f1bec24 79 * @voltdm: voltagedomain containing this powerdomain
f0271d65 80 * @prcm_offs: the address offset from CM_BASE/PRM_BASE
a64bb9cd 81 * @prcm_partition: (OMAP4 only) the PRCM partition ID containing @prcm_offs
f0271d65
PW		 82 * @pwrsts: Possible powerdomain power states
83 * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION
84 * @flags: Powerdomain flags
85 * @banks: Number of software-controllable memory banks in this powerdomain
86 * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION
87 * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON
88 * @pwrdm_clkdms: Clockdomains in this powerdomain
89 * @node: list_head linking all powerdomains
e69c22b1 90 * @voltdm_node: list_head linking all powerdomains in a voltagedomain
3f0ea764
VH		 91 * @pwrstctrl_offs: (AM33XX only) XXX_PWRSTCTRL reg offset from prcm_offs
92 * @pwrstst_offs: (AM33XX only) XXX_PWRSTST reg offset from prcm_offs
93 * @logicretstate_mask: (AM33XX only) mask for logic retention bitfield
94 * in @pwrstctrl_offs
95 * @mem_on_mask: (AM33XX only) mask for mem on bitfield in @pwrstctrl_offs
96 * @mem_ret_mask: (AM33XX only) mask for mem ret bitfield in @pwrstctrl_offs
97 * @mem_pwrst_mask: (AM33XX only) mask for mem state bitfield in @pwrstst_offs
98 * @mem_retst_mask: (AM33XX only) mask for mem retention state bitfield
99 * in @pwrstctrl_offs
f0271d65
PW		 100 * @state:
101 * @state_counter:
102 * @timer:
103 * @state_timer:
3a090284
PW		 104 * @_lock: spinlock used to serialize powerdomain and some clockdomain ops
105 * @_lock_flags: stored flags when @_lock is taken
a64bb9cd
PW		 106 *
107 * @prcm_partition possible values are defined in mach-omap2/prcm44xx.h.
f0271d65 108 */
ad67ef68 109struct powerdomain {
ad67ef68 110 const char *name;
8f1bec24
KH		 111 union {
112 const char *name;
113 struct voltagedomain *ptr;
114 } voltdm;
e0594b44 115 const s16 prcm_offs;
ad67ef68 116 const u8 pwrsts;
ad67ef68 117 const u8 pwrsts_logic_ret;
0b7cbfb5 118 const u8 flags;
ad67ef68 119 const u8 banks;
ad67ef68 120 const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS];
ad67ef68 121 const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS];
a64bb9cd 122 const u8 prcm_partition;
8420bb13 123 struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS];
ad67ef68 124 struct list_head node;
e69c22b1 125 struct list_head voltdm_node;
ba20bb12 126 int state;
2354eb5a 127 unsigned state_counter[PWRDM_MAX_PWRSTS];
cde08f81
TG		 128 unsigned ret_logic_off_counter;
129 unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS];
3a090284
PW		 130 spinlock_t _lock;
131 unsigned long _lock_flags;
3f0ea764
VH		 132 const u8 pwrstctrl_offs;
133 const u8 pwrstst_offs;
134 const u32 logicretstate_mask;
135 const u32 mem_on_mask[PWRDM_MAX_MEM_BANKS];
136 const u32 mem_ret_mask[PWRDM_MAX_MEM_BANKS];
137 const u32 mem_pwrst_mask[PWRDM_MAX_MEM_BANKS];
138 const u32 mem_retst_mask[PWRDM_MAX_MEM_BANKS];
139
331b93f4
PDS		 140#ifdef CONFIG_PM_DEBUG
141 s64 timer;
2354eb5a 142 s64 state_timer[PWRDM_MAX_PWRSTS];
331b93f4 143#endif
485995b0 144 u32 context;
ad67ef68
PW		 145};
146
3b1e8b21 147/**
25985edc 148 * struct pwrdm_ops - Arch specific function implementations
3b1e8b21
RN		 149 * @pwrdm_set_next_pwrst: Set the target power state for a pd
150 * @pwrdm_read_next_pwrst: Read the target power state set for a pd
151 * @pwrdm_read_pwrst: Read the current power state of a pd
152 * @pwrdm_read_prev_pwrst: Read the prev power state entered by the pd
153 * @pwrdm_set_logic_retst: Set the logic state in RET for a pd
154 * @pwrdm_set_mem_onst: Set the Memory state in ON for a pd
155 * @pwrdm_set_mem_retst: Set the Memory state in RET for a pd
156 * @pwrdm_read_logic_pwrst: Read the current logic state of a pd
157 * @pwrdm_read_prev_logic_pwrst: Read the previous logic state entered by a pd
158 * @pwrdm_read_logic_retst: Read the logic state in RET for a pd
159 * @pwrdm_read_mem_pwrst: Read the current memory state of a pd
160 * @pwrdm_read_prev_mem_pwrst: Read the previous memory state entered by a pd
161 * @pwrdm_read_mem_retst: Read the memory state in RET for a pd
162 * @pwrdm_clear_all_prev_pwrst: Clear all previous power states logged for a pd
163 * @pwrdm_enable_hdwr_sar: Enable Hardware Save-Restore feature for the pd
164 * @pwrdm_disable_hdwr_sar: Disable Hardware Save-Restore feature for a pd
165 * @pwrdm_set_lowpwrstchange: Enable pd transitions from a shallow to deep sleep
166 * @pwrdm_wait_transition: Wait for a pd state transition to complete
cd8abed1 167 * @pwrdm_has_voltdm: Check if a voltdm association is needed
c4978fba
PW		 168 *
169 * Regarding @pwrdm_set_lowpwrstchange: On the OMAP2 and 3-family
170 * chips, a powerdomain's power state is not allowed to directly
171 * transition from one low-power state (e.g., CSWR) to another
172 * low-power state (e.g., OFF) without first waking up the
173 * powerdomain. This wastes energy. So OMAP4 chips support the
174 * ability to transition a powerdomain power state directly from one
175 * low-power state to another. The function pointed to by
176 * @pwrdm_set_lowpwrstchange is intended to configure the OMAP4
177 * hardware powerdomain state machine to enable this feature.
3b1e8b21
RN		 178 */
179struct pwrdm_ops {
180 int (*pwrdm_set_next_pwrst)(struct powerdomain *pwrdm, u8 pwrst);
181 int (*pwrdm_read_next_pwrst)(struct powerdomain *pwrdm);
182 int (*pwrdm_read_pwrst)(struct powerdomain *pwrdm);
183 int (*pwrdm_read_prev_pwrst)(struct powerdomain *pwrdm);
184 int (*pwrdm_set_logic_retst)(struct powerdomain *pwrdm, u8 pwrst);
185 int (*pwrdm_set_mem_onst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
186 int (*pwrdm_set_mem_retst)(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
187 int (*pwrdm_read_logic_pwrst)(struct powerdomain *pwrdm);
188 int (*pwrdm_read_prev_logic_pwrst)(struct powerdomain *pwrdm);
189 int (*pwrdm_read_logic_retst)(struct powerdomain *pwrdm);
190 int (*pwrdm_read_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
191 int (*pwrdm_read_prev_mem_pwrst)(struct powerdomain *pwrdm, u8 bank);
192 int (*pwrdm_read_mem_retst)(struct powerdomain *pwrdm, u8 bank);
193 int (*pwrdm_clear_all_prev_pwrst)(struct powerdomain *pwrdm);
194 int (*pwrdm_enable_hdwr_sar)(struct powerdomain *pwrdm);
195 int (*pwrdm_disable_hdwr_sar)(struct powerdomain *pwrdm);
196 int (*pwrdm_set_lowpwrstchange)(struct powerdomain *pwrdm);
197 int (*pwrdm_wait_transition)(struct powerdomain *pwrdm);
cd8abed1 198 int (*pwrdm_has_voltdm)(void);
485995b0
RD		 199 void (*pwrdm_save_context)(struct powerdomain *pwrdm);
200 void (*pwrdm_restore_context)(struct powerdomain *pwrdm);
3b1e8b21 201};
ad67ef68 202
129c65ee
PW		 203int pwrdm_register_platform_funcs(struct pwrdm_ops *custom_funcs);
204int pwrdm_register_pwrdms(struct powerdomain **pwrdm_list);
205int pwrdm_complete_init(void);
ad67ef68 206
ad67ef68
PW		 207struct powerdomain *pwrdm_lookup(const char *name);
208
a23456e9
PDS		 209int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user),
210 void *user);
ee894b18
AB		 211int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user),
212 void *user);
ad67ef68 213
8420bb13 214int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm);
8420bb13 215
ad67ef68
PW		 216int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm);
217
bd002d7b
NM		 218u8 pwrdm_get_valid_lp_state(struct powerdomain *pwrdm,
219 bool is_logic_state, u8 req_state);
220
ad67ef68
PW		 221int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst);
222int pwrdm_read_next_pwrst(struct powerdomain *pwrdm);
fecb494b 223int pwrdm_read_pwrst(struct powerdomain *pwrdm);
ad67ef68
PW		 224int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm);
225int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm);
226
227int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst);
228int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
229int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst);
230
231int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm);
232int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm);
1e3d0d2b 233int pwrdm_read_logic_retst(struct powerdomain *pwrdm);
ad67ef68
PW		 234int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
235int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank);
1e3d0d2b 236int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank);
ad67ef68 237
0b7cbfb5
PW		 238int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm);
239int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm);
240bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm);
241
3a090284 242int pwrdm_state_switch_nolock(struct powerdomain *pwrdm);
ba20bb12 243int pwrdm_state_switch(struct powerdomain *pwrdm);
e0555489
KH		 244int pwrdm_pre_transition(struct powerdomain *pwrdm);
245int pwrdm_post_transition(struct powerdomain *pwrdm);
fc013873 246int pwrdm_get_context_loss_count(struct powerdomain *pwrdm);
694606c4 247bool pwrdm_can_ever_lose_context(struct powerdomain *pwrdm);
ba20bb12 248
c4978fba
PW		 249extern int omap_set_pwrdm_state(struct powerdomain *pwrdm, u8 state);
250
8179488a
PW		 251extern void omap242x_powerdomains_init(void);
252extern void omap243x_powerdomains_init(void);
6e01478a 253extern void omap3xxx_powerdomains_init(void);
3f0ea764 254extern void am33xx_powerdomains_init(void);
6e01478a 255extern void omap44xx_powerdomains_init(void);
411f968f 256extern void omap54xx_powerdomains_init(void);
97dd16b1 257extern void dra7xx_powerdomains_init(void);
eadc62fc 258void am43xx_powerdomains_init(void);
6e01478a 259
72e06d08
PW		 260extern struct pwrdm_ops omap2_pwrdm_operations;
261extern struct pwrdm_ops omap3_pwrdm_operations;
3f0ea764 262extern struct pwrdm_ops am33xx_pwrdm_operations;
72e06d08
PW		 263extern struct pwrdm_ops omap4_pwrdm_operations;
264
265/* Common Internal functions used across OMAP rev's */
266extern u32 omap2_pwrdm_get_mem_bank_onstate_mask(u8 bank);
267extern u32 omap2_pwrdm_get_mem_bank_retst_mask(u8 bank);
268extern u32 omap2_pwrdm_get_mem_bank_stst_mask(u8 bank);
269
270extern struct powerdomain wkup_omap2_pwrdm;
271extern struct powerdomain gfx_omap2_pwrdm;
272
3a090284
PW		 273extern void pwrdm_lock(struct powerdomain *pwrdm);
274extern void pwrdm_unlock(struct powerdomain *pwrdm);
72e06d08 275
485995b0
RD		 276extern void pwrdms_save_context(void);
277extern void pwrdms_restore_context(void);
278
279extern void pwrdms_lost_power(void);
ad67ef68 280#endif
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