[thirdparty/linux.git] / arch / arm / mach-orion5x / irq.c

/*
 * arch/arm/mach-orion5x/irq.c
 *
 * Core IRQ functions for Marvell Orion System On Chip
 *
 * Maintainer: Tzachi Perelstein <tzachi@marvell.com>
 *
 * This file is licensed under the terms of the GNU General Public
 * License version 2.  This program is licensed "as is" without any
 * warranty of any kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/gpio.h>
#include <mach/orion5x.h>
#include <plat/irq.h>
#include "common.h"

/*****************************************************************************
 * Orion GPIO IRQ
 *
 * GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
 * value of the line or the opposite value.
 *
 * Level IRQ handlers: DATA_IN is used directly as cause register.
 *                     Interrupt are masked by LEVEL_MASK registers.
 * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
 *                     Interrupt are masked by EDGE_MASK registers.
 * Both-edge handlers: Similar to regular Edge handlers, but also swaps
 *                     the polarity to catch the next line transaction.
 *                     This is a race condition that might not perfectly
 *                     work on some use cases.
 *
 * Every eight GPIO lines are grouped (OR'ed) before going up to main
 * cause register.
 *
 *                    EDGE  cause    mask
 *        data-in   /--------| |-----| |----\
 *     -----| |-----                         ---- to main cause reg
 *           X      \----------------| |----/
 *        polarity    LEVEL          mask
 *
 ****************************************************************************/
static void orion5x_gpio_irq_ack(u32 irq)
{
	int pin = irq_to_gpio(irq);
	if (irq_desc[irq].status & IRQ_LEVEL)
		/*
		 * Mask bit for level interrupt
		 */
		orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
	else
		/*
		 * Clear casue bit for egde interrupt
		 */
		orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
}

static void orion5x_gpio_irq_mask(u32 irq)
{
	int pin = irq_to_gpio(irq);
	if (irq_desc[irq].status & IRQ_LEVEL)
		orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
	else
		orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
}

static void orion5x_gpio_irq_unmask(u32 irq)
{
	int pin = irq_to_gpio(irq);
	if (irq_desc[irq].status & IRQ_LEVEL)
		orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
	else
		orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
}

static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
{
	int pin = irq_to_gpio(irq);
	struct irq_desc *desc;

	if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) {
		printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
				"(irq %d, pin %d).\n", irq, pin);
		return -EINVAL;
	}

	desc = irq_desc + irq;

	switch (type) {
	case IRQ_TYPE_LEVEL_HIGH:
		desc->handle_irq = handle_level_irq;
		desc->status |= IRQ_LEVEL;
		orion5x_clrbits(GPIO_IN_POL, (1 << pin));
		break;
	case IRQ_TYPE_LEVEL_LOW:
		desc->handle_irq = handle_level_irq;
		desc->status |= IRQ_LEVEL;
		orion5x_setbits(GPIO_IN_POL, (1 << pin));
		break;
	case IRQ_TYPE_EDGE_RISING:
		desc->handle_irq = handle_edge_irq;
		desc->status &= ~IRQ_LEVEL;
		orion5x_clrbits(GPIO_IN_POL, (1 << pin));
		break;
	case IRQ_TYPE_EDGE_FALLING:
		desc->handle_irq = handle_edge_irq;
		desc->status &= ~IRQ_LEVEL;
		orion5x_setbits(GPIO_IN_POL, (1 << pin));
		break;
	case IRQ_TYPE_EDGE_BOTH:
		desc->handle_irq = handle_edge_irq;
		desc->status &= ~IRQ_LEVEL;
		/*
		 * set initial polarity based on current input level
		 */
		if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN))
		    & (1 << pin))
			orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
		else
			orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */

		break;
	default:
		printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
		return -EINVAL;
	}

	desc->status &= ~IRQ_TYPE_SENSE_MASK;
	desc->status |= type & IRQ_TYPE_SENSE_MASK;

	return 0;
}

static struct irq_chip orion5x_gpio_irq_chip = {
	.name		= "Orion-IRQ-GPIO",
	.ack		= orion5x_gpio_irq_ack,
	.mask		= orion5x_gpio_irq_mask,
	.unmask		= orion5x_gpio_irq_unmask,
	.set_type	= orion5x_gpio_set_irq_type,
};

static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	u32 cause, offs, pin;

	BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 || irq > IRQ_ORION5X_GPIO_24_31);
	offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
	cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) |
		(readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK));

	for (pin = offs; pin < offs + 8; pin++) {
		if (cause & (1 << pin)) {
			irq = gpio_to_irq(pin);
			desc = irq_desc + irq;
			if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
				/* Swap polarity (race with GPIO line) */
				u32 polarity = readl(GPIO_IN_POL);
				polarity ^= 1 << pin;
				writel(polarity, GPIO_IN_POL);
			}
			desc_handle_irq(irq, desc);
		}
	}
}

static void __init orion5x_init_gpio_irq(void)
{
	int i;
	struct irq_desc *desc;

	/*
	 * Mask and clear GPIO IRQ interrupts
	 */
	writel(0x0, GPIO_LEVEL_MASK);
	writel(0x0, GPIO_EDGE_MASK);
	writel(0x0, GPIO_EDGE_CAUSE);

	/*
	 * Register chained level handlers for GPIO IRQs by default.
	 * User can use set_type() if he wants to use edge types handlers.
	 */
	for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
		set_irq_chip(i, &orion5x_gpio_irq_chip);
		set_irq_handler(i, handle_level_irq);
		desc = irq_desc + i;
		desc->status |= IRQ_LEVEL;
		set_irq_flags(i, IRQF_VALID);
	}
	set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler);
	set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler);
	set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler);
	set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler);
}

/*****************************************************************************
 * Orion Main IRQ
 ****************************************************************************/
static void __init orion5x_init_main_irq(void)
{
	orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
}

void __init orion5x_init_irq(void)
{
	orion5x_init_main_irq();
	orion5x_init_gpio_irq();
}
Commit	Line	Data
3085de6a	1	/*
9dd0b194	2	* arch/arm/mach-orion5x/irq.c
3085de6a TP	3	*
	4	* Core IRQ functions for Marvell Orion System On Chip
	5	*
	6	* Maintainer: Tzachi Perelstein <tzachi@marvell.com>
	7	*
	8	* This file is licensed under the terms of the GNU General Public
159ffb3a	9	* License version 2. This program is licensed "as is" without any
3085de6a TP	10	* warranty of any kind, whether express or implied.
	11	*/
	12
	13	#include <linux/kernel.h>
	14	#include <linux/init.h>
	15	#include <linux/irq.h>
fced80c7	16	#include <linux/io.h>
3085de6a	17	#include <asm/gpio.h>
a09e64fb	18	#include <mach/orion5x.h>
6f088f1d	19	#include <plat/irq.h>
3085de6a TP	20	#include "common.h"
	21
	22	/*****************************************************************************
	23	* Orion GPIO IRQ
f0066614 TP	24	*
	25	* GPIO_IN_POL register controlls whether GPIO_DATA_IN will hold the same
	26	* value of the line or the opposite value.
	27	*
	28	* Level IRQ handlers: DATA_IN is used directly as cause register.
	29	* Interrupt are masked by LEVEL_MASK registers.
	30	* Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE.
	31	* Interrupt are masked by EDGE_MASK registers.
	32	* Both-edge handlers: Similar to regular Edge handlers, but also swaps
	33	* the polarity to catch the next line transaction.
	34	* This is a race condition that might not perfectly
	35	* work on some use cases.
	36	*
	37	* Every eight GPIO lines are grouped (OR'ed) before going up to main
	38	* cause register.
	39	*
	40	* EDGE cause mask
	41	* data-in /--------\| \|-----\| \|----\
	42	* -----\| \|----- ---- to main cause reg
	43	* X \----------------\| \|----/
	44	* polarity LEVEL mask
	45	*
3085de6a	46	****************************************************************************/
9dd0b194	47	static void orion5x_gpio_irq_ack(u32 irq)
f0066614 TP	48	{
	49	int pin = irq_to_gpio(irq);
	50	if (irq_desc[irq].status & IRQ_LEVEL)
	51	/*
	52	* Mask bit for level interrupt
	53	*/
9dd0b194	54	orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
f0066614 TP	55	else
	56	/*
	57	* Clear casue bit for egde interrupt
	58	*/
9dd0b194	59	orion5x_clrbits(GPIO_EDGE_CAUSE, 1 << pin);
f0066614 TP	60	}
f0066614 TP	61
9dd0b194	62	static void orion5x_gpio_irq_mask(u32 irq)
3085de6a TP	63	{
3085de6a TP	64	int pin = irq_to_gpio(irq);
f0066614	65	if (irq_desc[irq].status & IRQ_LEVEL)
9dd0b194	66	orion5x_clrbits(GPIO_LEVEL_MASK, 1 << pin);
f0066614	67	else
9dd0b194	68	orion5x_clrbits(GPIO_EDGE_MASK, 1 << pin);
3085de6a TP	69	}
3085de6a TP	70
9dd0b194	71	static void orion5x_gpio_irq_unmask(u32 irq)
3085de6a TP	72	{
3085de6a TP	73	int pin = irq_to_gpio(irq);
f0066614	74	if (irq_desc[irq].status & IRQ_LEVEL)
9dd0b194	75	orion5x_setbits(GPIO_LEVEL_MASK, 1 << pin);
f0066614	76	else
9dd0b194	77	orion5x_setbits(GPIO_EDGE_MASK, 1 << pin);
3085de6a TP	78	}
3085de6a TP	79
9dd0b194	80	static int orion5x_gpio_set_irq_type(u32 irq, u32 type)
3085de6a TP	81	{
3085de6a TP	82	int pin = irq_to_gpio(irq);
f0066614	83	struct irq_desc *desc;
3085de6a	84
79e90dd5	85	if ((readl(GPIO_IO_CONF) & (1 << pin)) == 0) {
9dd0b194	86	printk(KERN_ERR "orion5x_gpio_set_irq_type failed "
3085de6a TP	87	"(irq %d, pin %d).\n", irq, pin);
	88	return -EINVAL;
	89	}
	90
f0066614 TP	91	desc = irq_desc + irq;
f0066614 TP	92
3085de6a	93	switch (type) {
6cab4860	94	case IRQ_TYPE_LEVEL_HIGH:
f0066614 TP	95	desc->handle_irq = handle_level_irq;
f0066614 TP	96	desc->status \|= IRQ_LEVEL;
9dd0b194	97	orion5x_clrbits(GPIO_IN_POL, (1 << pin));
3085de6a	98	break;
6cab4860	99	case IRQ_TYPE_LEVEL_LOW:
f0066614 TP	100	desc->handle_irq = handle_level_irq;
f0066614 TP	101	desc->status \|= IRQ_LEVEL;
9dd0b194	102	orion5x_setbits(GPIO_IN_POL, (1 << pin));
f0066614	103	break;
6cab4860	104	case IRQ_TYPE_EDGE_RISING:
f0066614 TP	105	desc->handle_irq = handle_edge_irq;
f0066614 TP	106	desc->status &= ~IRQ_LEVEL;
9dd0b194	107	orion5x_clrbits(GPIO_IN_POL, (1 << pin));
f0066614	108	break;
6cab4860	109	case IRQ_TYPE_EDGE_FALLING:
f0066614 TP	110	desc->handle_irq = handle_edge_irq;
f0066614 TP	111	desc->status &= ~IRQ_LEVEL;
9dd0b194	112	orion5x_setbits(GPIO_IN_POL, (1 << pin));
f0066614	113	break;
6cab4860	114	case IRQ_TYPE_EDGE_BOTH:
f0066614 TP	115	desc->handle_irq = handle_edge_irq;
	116	desc->status &= ~IRQ_LEVEL;
	117	/*
	118	* set initial polarity based on current input level
	119	*/
79e90dd5	120	if ((readl(GPIO_IN_POL) ^ readl(GPIO_DATA_IN))
f0066614	121	& (1 << pin))
9dd0b194	122	orion5x_setbits(GPIO_IN_POL, (1 << pin)); /* falling */
f0066614	123	else
9dd0b194	124	orion5x_clrbits(GPIO_IN_POL, (1 << pin)); /* rising */
f0066614	125
3085de6a TP	126	break;
	127	default:
	128	printk(KERN_ERR "failed to set irq=%d (type=%d)\n", irq, type);
	129	return -EINVAL;
	130	}
	131
f0066614 TP	132	desc->status &= ~IRQ_TYPE_SENSE_MASK;
	133	desc->status \|= type & IRQ_TYPE_SENSE_MASK;
	134
3085de6a TP	135	return 0;
	136	}
	137
9dd0b194	138	static struct irq_chip orion5x_gpio_irq_chip = {
3085de6a	139	.name = "Orion-IRQ-GPIO",
9dd0b194 LB	140	.ack = orion5x_gpio_irq_ack,
	141	.mask = orion5x_gpio_irq_mask,
	142	.unmask = orion5x_gpio_irq_unmask,
	143	.set_type = orion5x_gpio_set_irq_type,
3085de6a TP	144	};
3085de6a TP	145
9dd0b194	146	static void orion5x_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
3085de6a	147	{
f0066614	148	u32 cause, offs, pin;
3085de6a	149
9dd0b194 LB	150	BUG_ON(irq < IRQ_ORION5X_GPIO_0_7 \|\| irq > IRQ_ORION5X_GPIO_24_31);
9dd0b194 LB	151	offs = (irq - IRQ_ORION5X_GPIO_0_7) * 8;
79e90dd5 LB	152	cause = (readl(GPIO_DATA_IN) & readl(GPIO_LEVEL_MASK)) \|
79e90dd5 LB	153	(readl(GPIO_EDGE_CAUSE) & readl(GPIO_EDGE_MASK));
f0066614 TP	154
	155	for (pin = offs; pin < offs + 8; pin++) {
	156	if (cause & (1 << pin)) {
	157	irq = gpio_to_irq(pin);
	158	desc = irq_desc + irq;
6cab4860	159	if ((desc->status & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
f0066614	160	/* Swap polarity (race with GPIO line) */
79e90dd5	161	u32 polarity = readl(GPIO_IN_POL);
f0066614	162	polarity ^= 1 << pin;
79e90dd5	163	writel(polarity, GPIO_IN_POL);
3085de6a	164	}
f0066614	165	desc_handle_irq(irq, desc);
3085de6a TP	166	}
	167	}
	168	}
	169
9dd0b194	170	static void __init orion5x_init_gpio_irq(void)
3085de6a TP	171	{
3085de6a TP	172	int i;
f0066614	173	struct irq_desc *desc;
3085de6a TP	174
	175	/*
	176	* Mask and clear GPIO IRQ interrupts
	177	*/
79e90dd5 LB	178	writel(0x0, GPIO_LEVEL_MASK);
	179	writel(0x0, GPIO_EDGE_MASK);
	180	writel(0x0, GPIO_EDGE_CAUSE);
3085de6a TP	181
3085de6a TP	182	/*
f0066614 TP	183	* Register chained level handlers for GPIO IRQs by default.
f0066614 TP	184	* User can use set_type() if he wants to use edge types handlers.
3085de6a	185	*/
9dd0b194 LB	186	for (i = IRQ_ORION5X_GPIO_START; i < NR_IRQS; i++) {
9dd0b194 LB	187	set_irq_chip(i, &orion5x_gpio_irq_chip);
3085de6a	188	set_irq_handler(i, handle_level_irq);
f0066614 TP	189	desc = irq_desc + i;
f0066614 TP	190	desc->status \|= IRQ_LEVEL;
3085de6a TP	191	set_irq_flags(i, IRQF_VALID);
3085de6a TP	192	}
9dd0b194 LB	193	set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, orion5x_gpio_irq_handler);
	194	set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, orion5x_gpio_irq_handler);
	195	set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, orion5x_gpio_irq_handler);
	196	set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, orion5x_gpio_irq_handler);
3085de6a TP	197	}
	198
	199	/*****************************************************************************
	200	* Orion Main IRQ
	201	****************************************************************************/
9dd0b194	202	static void __init orion5x_init_main_irq(void)
3085de6a	203	{
01eb5698	204	orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
3085de6a TP	205	}
3085de6a TP	206
9dd0b194	207	void __init orion5x_init_irq(void)
3085de6a	208	{
9dd0b194 LB	209	orion5x_init_main_irq();
9dd0b194 LB	210	orion5x_init_gpio_irq();
3085de6a	211	}