projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 1d0e9278 NI |
1 | /* |
| 2 | * arch/arm/cpu/armv7/rmobile/lowlevel_init_ca15.S | |
| 3 | * This file is lager low level initialize. | |
| 4 | * | |
| 42c53ab0 | 5 | * Copyright (C) 2013, 2014 Renesas Electronics Corporation |
| 1d0e9278 NI |
6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0 | |
| 8 | */ | |
| 9 | ||
| 10 | #include <config.h> | |
| 11 | #include <linux/linkage.h> | |
| 12 | ||
| 13 | ENTRY(lowlevel_init) | |
| 14 | mrc p15, 0, r4, c0, c0, 5 /* mpidr */ | |
| 15 | orr r4, r4, r4, lsr #6 | |
| 16 | and r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */ | |
| 17 | ||
| 18 | b do_lowlevel_init | |
| 19 | ||
| 20 | .pool | |
| 21 | ||
| 22 | /* | |
| 23 | * CPU ID #1-#3 come here | |
| 24 | */ | |
| 25 | .align 4 | |
| 26 | do_cpu_waiting: | |
| 27 | ldr r1, =0xe6180000 /* sysc */ | |
| 28 | 1: ldr r0, [r1, #0x20] /* sbar */ | |
| 29 | tst r0, r0 | |
| 30 | beq 1b | |
| 31 | bx r0 | |
| 32 | ||
| 33 | /* | |
| 34 | * Only CPU ID #0 comes here | |
| 35 | */ | |
| 36 | .align 4 | |
| 37 | do_lowlevel_init: | |
| 88982893 NI |
38 | ldr r2, =0xFF000044 /* PRR */ |
| 39 | ldr r1, [r2] | |
| 40 | and r1, r1, #0x7F00 | |
| 41 | lsrs r1, r1, #8 | |
| 42 | cmp r1, #0x4C /* 0x4C is ID of r8a7794 */ | |
| 3eda55a3 | 43 | beq _enable_actlr_smp |
| 88982893 | 44 | |
| 1d0e9278 | 45 | /* surpress wfe if ca15 */ |
| 42c53ab0 | 46 | tst r4, #4 |
| 1d0e9278 NI |
47 | mrceq p15, 0, r0, c1, c0, 1 /* actlr */ |
| 48 | orreq r0, r0, #(1<<7) | |
| 49 | mcreq p15, 0, r0, c1, c0, 1 | |
| 42c53ab0 | 50 | |
| 1d0e9278 | 51 | /* and set l2 latency */ |
| 42c53ab0 NI |
52 | mrc p15, 0, r0, c0, c0, 5 /* r0 = MPIDR */ |
| 53 | and r0, r0, #0xf00 | |
| 54 | lsr r0, r0, #8 | |
| 55 | tst r0, #1 /* only need for cluster 0 */ | |
| 56 | bne _exit_init_l2_a15 | |
| 57 | ||
| 58 | mrc p15, 1, r0, c9, c0, 2 /* r0 = L2CTLR */ | |
| 59 | and r1, r0, #7 | |
| 60 | cmp r1, #3 /* has already been set up */ | |
| 61 | bicne r0, r0, #0xe7 | |
| 62 | orrne r0, r0, #0x83 /* L2CTLR[7:6] + L2CTLR[2:0] */ | |
| 3372a9a7 | 63 | #if defined(CONFIG_R8A7790) |
| 237faf09 | 64 | orrne r0, r0, #0x20 /* L2CTLR[5] */ |
| 3372a9a7 | 65 | #endif |
| 42c53ab0 | 66 | mcrne p15, 1, r0, c9, c0, 2 |
| 3eda55a3 NI |
67 | |
| 68 | b _exit_init_l2_a15 | |
| 69 | ||
| 70 | _enable_actlr_smp: /* R8A7794 only (CA7) */ | |
| 71 | #ifndef CONFIG_DCACHE_OFF | |
| 72 | mrc p15, 0, r0, c1, c0, 1 | |
| 73 | orr r0, r0, #0x40 | |
| 74 | mcr p15, 0, r0, c1, c0, 1 | |
| 75 | #endif | |
| 76 | ||
| 42c53ab0 | 77 | _exit_init_l2_a15: |
| 1d0e9278 NI |
78 | ldr r3, =(CONFIG_SYS_INIT_SP_ADDR) |
| 79 | sub sp, r3, #4 | |
| 80 | str lr, [sp] | |
| 81 | ||
| 82 | /* initialize system */ | |
| 83 | bl s_init | |
| 84 | ||
| 85 | ldr lr, [sp] | |
| 86 | mov pc, lr | |
| 87 | nop | |
| 88 | ENDPROC(lowlevel_init) | |
| 89 | .ltorg |