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fafcfc5a NI |
1 | /* |
2 | * arch/arm/cpu/armv7/rmobile/pfc-r8a7794.c | |
3 | * This file is r8a7794 processor support - PFC hardware block. | |
4 | * | |
5 | * Copyright (C) 2014 Renesas Electronics Corporation | |
6 | * | |
7 | * SPDX-License-Identifier: GPL-2.0 | |
8 | */ | |
9 | ||
10 | #include <common.h> | |
11 | #include <sh_pfc.h> | |
12 | #include <asm/gpio.h> | |
13 | ||
14 | #define CPU_32_PORT(fn, pfx, sfx) \ | |
15 | PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ | |
16 | PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ | |
17 | PORT_1(fn, pfx##31, sfx) | |
18 | ||
19 | #define CPU_26_PORT(fn, pfx, sfx) \ | |
20 | PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ | |
21 | PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ | |
22 | PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ | |
23 | PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx) | |
24 | ||
25 | #define CPU_28_PORT(fn, pfx, sfx) \ | |
26 | PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ | |
27 | PORT_1(fn, pfx##20, sfx), PORT_1(fn, pfx##21, sfx), \ | |
28 | PORT_1(fn, pfx##22, sfx), PORT_1(fn, pfx##23, sfx), \ | |
29 | PORT_1(fn, pfx##24, sfx), PORT_1(fn, pfx##25, sfx), \ | |
30 | PORT_1(fn, pfx##26, sfx), PORT_1(fn, pfx##27, sfx) | |
31 | ||
32 | /* | |
33 | * GP_0_0_DATA -> GP_6_25_DATA | |
34 | * (except for GP1[26],GP1[27],GP1[28],GP1[29]),GP1[30],GP1[31] | |
35 | * GP5[28],GP5[29]),GP5[30],GP5[31],GP6[26],GP6[27],GP6[28], | |
36 | * GP6[29]),GP6[30],GP6[31]) | |
37 | */ | |
38 | #define CPU_ALL_PORT(fn, pfx, sfx) \ | |
39 | CPU_32_PORT(fn, pfx##_0_, sfx), \ | |
40 | CPU_26_PORT(fn, pfx##_1_, sfx), \ | |
41 | CPU_32_PORT(fn, pfx##_2_, sfx), \ | |
42 | CPU_32_PORT(fn, pfx##_3_, sfx), \ | |
43 | CPU_32_PORT(fn, pfx##_4_, sfx), \ | |
44 | CPU_28_PORT(fn, pfx##_5_, sfx), \ | |
45 | CPU_26_PORT(fn, pfx##_6_, sfx) | |
46 | ||
47 | #define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) | |
48 | #define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ | |
49 | GP##pfx##_IN, GP##pfx##_OUT) | |
50 | ||
51 | #define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT | |
52 | #define _GP_INDT(pfx, sfx) GP##pfx##_DATA | |
53 | ||
54 | #define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) | |
55 | #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) | |
56 | #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) | |
57 | ||
58 | ||
59 | #define PORT_10_REV(fn, pfx, sfx) \ | |
60 | PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ | |
61 | PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ | |
62 | PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ | |
63 | PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ | |
64 | PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) | |
65 | ||
66 | #define CPU_32_PORT_REV(fn, pfx, sfx) \ | |
67 | PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ | |
68 | PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ | |
69 | PORT_10_REV(fn, pfx, sfx) | |
70 | ||
71 | #define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) | |
72 | #define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) | |
73 | ||
74 | #define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn) | |
75 | #define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ | |
76 | FN_##ipsr, FN_##fn) | |
77 | ||
78 | enum { | |
79 | PINMUX_RESERVED = 0, | |
80 | ||
81 | PINMUX_DATA_BEGIN, | |
82 | GP_ALL(DATA), | |
83 | PINMUX_DATA_END, | |
84 | ||
85 | PINMUX_INPUT_BEGIN, | |
86 | GP_ALL(IN), | |
87 | PINMUX_INPUT_END, | |
88 | ||
89 | PINMUX_OUTPUT_BEGIN, | |
90 | GP_ALL(OUT), | |
91 | PINMUX_OUTPUT_END, | |
92 | ||
93 | PINMUX_FUNCTION_BEGIN, | |
94 | GP_ALL(FN), | |
95 | ||
96 | /* GPSR0 */ | |
97 | FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28, | |
98 | FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, | |
99 | FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18, | |
100 | FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27, | |
101 | FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4, | |
102 | FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14, | |
103 | FN_IP2_17_16, | |
104 | ||
105 | /* GPSR1 */ | |
106 | FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30, | |
107 | FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10, | |
108 | FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18, | |
109 | FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31, | |
110 | FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0, | |
111 | ||
112 | /* GPSR2 */ | |
113 | FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12, | |
114 | FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23, | |
115 | FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2, | |
116 | FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14, | |
117 | FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24, | |
118 | FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2, | |
119 | FN_IP6_5_4, FN_IP6_7_6, | |
120 | ||
121 | /* GPSR3 */ | |
122 | FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13, | |
123 | FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20, | |
124 | FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, | |
125 | FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18, | |
126 | FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, | |
127 | FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17, | |
128 | FN_IP8_22_20, | |
129 | ||
130 | /* GPSR4 */ | |
131 | FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3, | |
132 | FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17, | |
133 | FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0, | |
134 | FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15, | |
135 | FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27, | |
136 | FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8, | |
137 | FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16, | |
138 | ||
139 | /* GPSR5 */ | |
140 | FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0, | |
141 | FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13, | |
142 | FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24, | |
143 | FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9, | |
144 | FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21, | |
145 | FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC, | |
146 | ||
147 | /* GPSR6 */ | |
148 | FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2, | |
149 | FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD, | |
150 | FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0, | |
151 | FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14, | |
152 | FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20, | |
153 | ||
25f9613f NI |
154 | /* IPSR0 */ |
155 | FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK, | |
156 | FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1, | |
157 | FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3, | |
158 | FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD, | |
159 | FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, | |
160 | FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B, | |
161 | FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4, | |
162 | FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, | |
163 | ||
fafcfc5a | 164 | /* |
25f9613f | 165 | * From IPSR1 to IPSR5 have been removed because they does not use. |
fafcfc5a NI |
166 | */ |
167 | ||
168 | /* IPSR6 */ | |
169 | FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, | |
170 | FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, | |
171 | FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB, | |
172 | FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0, | |
173 | FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2, | |
174 | FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4, | |
175 | FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6, | |
176 | FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB, | |
177 | FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD, | |
178 | FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N, | |
179 | FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N, | |
180 | FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, | |
181 | FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK, | |
182 | FN_ADIDATA, FN_AD_DI, | |
183 | ||
184 | /* IPSR7 */ | |
185 | FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0, | |
186 | FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, | |
187 | FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3, | |
188 | FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, | |
189 | FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3, | |
190 | FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, | |
191 | FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, | |
192 | FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, | |
193 | FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0, | |
194 | FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B, | |
195 | FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B, | |
196 | FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK, | |
197 | FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD, | |
198 | ||
199 | /* IPSR8 */ | |
200 | FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC, | |
201 | FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, | |
202 | FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX, | |
203 | FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B, | |
204 | FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, | |
205 | FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7, | |
206 | FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B, | |
207 | FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, | |
208 | FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK, | |
209 | FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, | |
210 | FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD, | |
211 | FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, | |
212 | FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B, | |
213 | FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, | |
214 | FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, | |
215 | ||
216 | /* | |
217 | * From IPSR9 to IPSR10 have been removed because they does not use. | |
218 | */ | |
219 | ||
220 | /* IPSR11 */ | |
221 | FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, | |
222 | FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, | |
223 | FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B, | |
224 | FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6, | |
225 | FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC, | |
226 | FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, | |
227 | FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78, | |
228 | FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78, | |
229 | FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7, | |
230 | FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N, | |
231 | FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, | |
232 | FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, | |
233 | FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, | |
234 | FN_ADICLK_B, FN_AD_CLK_B, | |
235 | ||
236 | /* | |
237 | * From IPSR12 to IPSR13 have been removed because they does not use. | |
238 | */ | |
239 | ||
240 | /* MOD_SEL */ | |
241 | FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, | |
242 | FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1, | |
243 | FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1, | |
244 | FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0, | |
245 | FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1, | |
246 | FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0, | |
247 | FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, | |
248 | FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1, | |
249 | FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0, | |
250 | FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4, | |
251 | FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, | |
252 | FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, | |
253 | FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1, | |
254 | FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1, | |
255 | ||
256 | /* MOD_SEL2 */ | |
257 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0, | |
258 | FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0, | |
259 | FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0, | |
260 | FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0, | |
261 | FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0, | |
262 | FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0, | |
263 | FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, | |
264 | FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, | |
265 | FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, | |
266 | FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1, | |
267 | FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, | |
268 | FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1, | |
269 | FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1, | |
270 | FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, | |
271 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1, | |
272 | FN_SEL_RDS_2, FN_SEL_RDS_3, | |
273 | ||
274 | /* MOD_SEL3 */ | |
275 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, | |
276 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0, | |
277 | FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, | |
278 | FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, | |
279 | FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, | |
280 | FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0, | |
281 | FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0, | |
282 | FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0, | |
283 | FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0, | |
284 | FN_SEL_SSI9_1, | |
285 | PINMUX_FUNCTION_END, | |
286 | ||
287 | PINMUX_MARK_BEGIN, | |
288 | A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK, | |
289 | ||
290 | USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK, | |
291 | ||
292 | SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK, | |
293 | SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK, | |
294 | ||
295 | SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK, | |
296 | SD1_DATA2_MARK, SD1_DATA3_MARK, | |
297 | ||
25f9613f NI |
298 | /* IPSR0 */ |
299 | SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK, | |
300 | MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK, | |
301 | SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK, | |
302 | SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK, | |
303 | MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK, | |
304 | CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK, | |
305 | CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK, | |
306 | SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK, | |
307 | SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK, | |
308 | SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK, | |
309 | ||
fafcfc5a | 310 | /* |
25f9613f | 311 | * From IPSR1 to IPSR5 have been removed because they does not use. |
fafcfc5a NI |
312 | */ |
313 | ||
314 | /* IPSR6 */ | |
315 | DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK, | |
316 | DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK, | |
317 | DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK, | |
318 | CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK, | |
319 | AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK, | |
320 | VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK, | |
321 | AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK, | |
322 | VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK, | |
323 | AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK, | |
324 | I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK, | |
325 | VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK, | |
326 | AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK, | |
327 | IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK, | |
328 | I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK, | |
329 | VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK, | |
330 | ADIDATA_MARK, AD_DI_MARK, | |
331 | ||
332 | /* IPSR7 */ | |
333 | ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK, | |
334 | AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK, | |
335 | MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK, | |
336 | AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK, | |
337 | CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK, | |
338 | ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK, | |
339 | AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK, | |
340 | MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK, | |
341 | ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK, | |
342 | SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK, | |
343 | IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK, | |
344 | VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK, | |
345 | SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK, | |
346 | AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK, | |
347 | SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK, | |
348 | DREQ0_N_MARK, SCIFB1_RXD_MARK, | |
349 | ||
350 | /* IPSR8 */ | |
351 | ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK, | |
352 | AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK, | |
353 | I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK, | |
354 | HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK, | |
355 | AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK, | |
356 | SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK, | |
357 | HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK, | |
358 | AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK, | |
359 | HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK, | |
360 | I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK, | |
361 | AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK, | |
362 | SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK, | |
363 | CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK, | |
364 | DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK, | |
365 | I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK, | |
366 | TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK, | |
367 | I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK, | |
368 | FMCLK_C_MARK, RDS_CLK_MARK, | |
369 | ||
370 | /* | |
371 | * From IPSR9 to IPSR10 have been removed because they does not use. | |
372 | */ | |
373 | ||
374 | /* IPSR11 */ | |
375 | SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK, | |
376 | CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK, | |
377 | DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK, | |
378 | SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK, | |
379 | SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK, | |
380 | DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK, | |
381 | SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, | |
382 | CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK, | |
383 | DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK, | |
384 | DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK, | |
385 | AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK, | |
386 | MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK, | |
387 | PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK, | |
388 | ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK, | |
389 | PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK, | |
390 | ||
391 | /* | |
392 | * From IPSR12 to IPSR13 have been removed because they does not use. | |
393 | */ | |
394 | ||
395 | PINMUX_MARK_END, | |
396 | }; | |
397 | ||
398 | static pinmux_enum_t pinmux_data[] = { | |
399 | PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ | |
400 | ||
401 | PINMUX_DATA(A2_MARK, FN_A2), | |
402 | PINMUX_DATA(WE0_N_MARK, FN_WE0_N), | |
403 | PINMUX_DATA(WE1_N_MARK, FN_WE1_N), | |
404 | PINMUX_DATA(DACK0_MARK, FN_DACK0), | |
405 | PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN), | |
406 | PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC), | |
407 | PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN), | |
408 | PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC), | |
409 | PINMUX_DATA(SD0_CLK_MARK, FN_SD0_CLK), | |
410 | PINMUX_DATA(SD0_CMD_MARK, FN_SD0_CMD), | |
411 | PINMUX_DATA(SD0_DATA0_MARK, FN_SD0_DATA0), | |
412 | PINMUX_DATA(SD0_DATA1_MARK, FN_SD0_DATA1), | |
413 | PINMUX_DATA(SD0_DATA2_MARK, FN_SD0_DATA2), | |
414 | PINMUX_DATA(SD0_DATA3_MARK, FN_SD0_DATA3), | |
415 | PINMUX_DATA(SD0_CD_MARK, FN_SD0_CD), | |
416 | PINMUX_DATA(SD0_WP_MARK, FN_SD0_WP), | |
417 | PINMUX_DATA(SD1_CLK_MARK, FN_SD1_CLK), | |
418 | PINMUX_DATA(SD1_CMD_MARK, FN_SD1_CMD), | |
419 | PINMUX_DATA(SD1_DATA0_MARK, FN_SD1_DATA0), | |
420 | PINMUX_DATA(SD1_DATA1_MARK, FN_SD1_DATA1), | |
421 | PINMUX_DATA(SD1_DATA2_MARK, FN_SD1_DATA2), | |
422 | PINMUX_DATA(SD1_DATA3_MARK, FN_SD1_DATA3), | |
423 | ||
25f9613f NI |
424 | /* IPSR0 */ |
425 | PINMUX_IPSR_DATA(IP0_0, SD1_CD), | |
426 | PINMUX_IPSR_MODSEL_DATA(IP0_0, CAN0_RX, SEL_CAN0_0), | |
427 | PINMUX_IPSR_DATA(IP0_9_8, SD1_WP), | |
428 | PINMUX_IPSR_DATA(IP0_9_8, IRQ7), | |
429 | PINMUX_IPSR_MODSEL_DATA(IP0_9_8, CAN0_TX, SEL_CAN0_0), | |
430 | PINMUX_IPSR_DATA(IP0_10, MMC_CLK), | |
431 | PINMUX_IPSR_DATA(IP0_10, SD2_CLK), | |
432 | PINMUX_IPSR_DATA(IP0_11, MMC_CMD), | |
433 | PINMUX_IPSR_DATA(IP0_11, SD2_CMD), | |
434 | PINMUX_IPSR_DATA(IP0_12, MMC_D0), | |
435 | PINMUX_IPSR_DATA(IP0_12, SD2_DATA0), | |
436 | PINMUX_IPSR_DATA(IP0_13, MMC_D1), | |
437 | PINMUX_IPSR_DATA(IP0_13, SD2_DATA1), | |
438 | PINMUX_IPSR_DATA(IP0_14, MMC_D2), | |
439 | PINMUX_IPSR_DATA(IP0_14, SD2_DATA2), | |
440 | PINMUX_IPSR_DATA(IP0_15, MMC_D3), | |
441 | PINMUX_IPSR_DATA(IP0_15, SD2_DATA3), | |
442 | PINMUX_IPSR_DATA(IP0_16, MMC_D4), | |
443 | PINMUX_IPSR_DATA(IP0_16, SD2_CD), | |
444 | PINMUX_IPSR_DATA(IP0_17, MMC_D5), | |
445 | PINMUX_IPSR_DATA(IP0_17, SD2_WP), | |
446 | PINMUX_IPSR_DATA(IP0_19_18, MMC_D6), | |
447 | PINMUX_IPSR_MODSEL_DATA(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0), | |
448 | PINMUX_IPSR_MODSEL_DATA(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1), | |
449 | PINMUX_IPSR_MODSEL_DATA(IP0_19_18, CAN1_RX, SEL_CAN1_0), | |
450 | PINMUX_IPSR_DATA(IP0_21_20, MMC_D7), | |
451 | PINMUX_IPSR_MODSEL_DATA(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0), | |
452 | PINMUX_IPSR_MODSEL_DATA(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1), | |
453 | PINMUX_IPSR_MODSEL_DATA(IP0_21_20, CAN1_TX, SEL_CAN1_0), | |
454 | PINMUX_IPSR_DATA(IP0_23_22, D0), | |
455 | PINMUX_IPSR_MODSEL_DATA(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1), | |
456 | PINMUX_IPSR_DATA(IP0_23_22, IRQ4), | |
457 | PINMUX_IPSR_DATA(IP0_24, D1), | |
458 | PINMUX_IPSR_MODSEL_DATA(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1), | |
459 | PINMUX_IPSR_DATA(IP0_25, D2), | |
460 | PINMUX_IPSR_MODSEL_DATA(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1), | |
461 | PINMUX_IPSR_DATA(IP0_27_26, D3), | |
462 | PINMUX_IPSR_MODSEL_DATA(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1), | |
463 | PINMUX_IPSR_MODSEL_DATA(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1), | |
464 | PINMUX_IPSR_DATA(IP0_29_28, D4), | |
465 | PINMUX_IPSR_MODSEL_DATA(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1), | |
466 | PINMUX_IPSR_MODSEL_DATA(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1), | |
467 | PINMUX_IPSR_DATA(IP0_31_30, D5), | |
468 | PINMUX_IPSR_MODSEL_DATA(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1), | |
469 | PINMUX_IPSR_MODSEL_DATA(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3), | |
470 | ||
fafcfc5a | 471 | /* |
25f9613f | 472 | * From IPSR1 to IPSR5 have been removed because they does not use. |
fafcfc5a NI |
473 | */ |
474 | ||
475 | /* IPSR6 */ | |
476 | PINMUX_IPSR_DATA(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC), | |
477 | PINMUX_IPSR_DATA(IP6_1_0, QSTB_QHE), | |
478 | PINMUX_IPSR_DATA(IP6_1_0, CC50_STATE28), | |
479 | PINMUX_IPSR_DATA(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE), | |
480 | PINMUX_IPSR_DATA(IP6_3_2, QCPV_QDE), | |
481 | PINMUX_IPSR_DATA(IP6_3_2, CC50_STATE29), | |
482 | PINMUX_IPSR_DATA(IP6_5_4, DU0_DISP), | |
483 | PINMUX_IPSR_DATA(IP6_5_4, QPOLA), | |
484 | PINMUX_IPSR_DATA(IP6_5_4, CC50_STATE30), | |
485 | PINMUX_IPSR_DATA(IP6_7_6, DU0_CDE), | |
486 | PINMUX_IPSR_DATA(IP6_7_6, QPOLB), | |
487 | PINMUX_IPSR_DATA(IP6_7_6, CC50_STATE31), | |
488 | PINMUX_IPSR_DATA(IP6_8, VI0_CLK), | |
489 | PINMUX_IPSR_DATA(IP6_8, AVB_RX_CLK), | |
490 | PINMUX_IPSR_DATA(IP6_9, VI0_DATA0_VI0_B0), | |
491 | PINMUX_IPSR_DATA(IP6_9, AVB_RX_DV), | |
492 | PINMUX_IPSR_DATA(IP6_10, VI0_DATA1_VI0_B1), | |
493 | PINMUX_IPSR_DATA(IP6_10, AVB_RXD0), | |
494 | PINMUX_IPSR_DATA(IP6_11, VI0_DATA2_VI0_B2), | |
495 | PINMUX_IPSR_DATA(IP6_11, AVB_RXD1), | |
496 | PINMUX_IPSR_DATA(IP6_12, VI0_DATA3_VI0_B3), | |
497 | PINMUX_IPSR_DATA(IP6_12, AVB_RXD2), | |
498 | PINMUX_IPSR_DATA(IP6_13, VI0_DATA4_VI0_B4), | |
499 | PINMUX_IPSR_DATA(IP6_13, AVB_RXD3), | |
500 | PINMUX_IPSR_DATA(IP6_14, VI0_DATA5_VI0_B5), | |
501 | PINMUX_IPSR_DATA(IP6_14, AVB_RXD4), | |
502 | PINMUX_IPSR_DATA(IP6_15, VI0_DATA6_VI0_B6), | |
503 | PINMUX_IPSR_DATA(IP6_15, AVB_RXD5), | |
504 | PINMUX_IPSR_DATA(IP6_16, VI0_DATA7_VI0_B7), | |
505 | PINMUX_IPSR_DATA(IP6_16, AVB_RXD6), | |
506 | PINMUX_IPSR_DATA(IP6_19_17, VI0_CLKENB), | |
507 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, I2C3_SCL, SEL_I2C03_0), | |
508 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2), | |
509 | PINMUX_IPSR_MODSEL_DATA(IP6_19_17, IETX_C, SEL_IEB_2), | |
510 | PINMUX_IPSR_DATA(IP6_19_17, AVB_RXD7), | |
511 | PINMUX_IPSR_DATA(IP6_22_20, VI0_FIELD), | |
512 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, I2C3_SDA, SEL_I2C03_0), | |
513 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2), | |
514 | PINMUX_IPSR_MODSEL_DATA(IP6_22_20, IECLK_C, SEL_IEB_2), | |
515 | PINMUX_IPSR_DATA(IP6_22_20, AVB_RX_ER), | |
516 | PINMUX_IPSR_DATA(IP6_25_23, VI0_HSYNC_N), | |
517 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1), | |
518 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2), | |
519 | PINMUX_IPSR_MODSEL_DATA(IP6_25_23, IERX_C, SEL_IEB_2), | |
520 | PINMUX_IPSR_DATA(IP6_25_23, AVB_COL), | |
521 | PINMUX_IPSR_DATA(IP6_28_26, VI0_VSYNC_N), | |
522 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1), | |
523 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2), | |
524 | PINMUX_IPSR_MODSEL_DATA(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1), | |
525 | PINMUX_IPSR_DATA(IP6_28_26, AVB_TX_EN), | |
526 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ETH_MDIO, SEL_ETH_0), | |
527 | PINMUX_IPSR_DATA(IP6_31_29, VI0_G0), | |
528 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1), | |
529 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3), | |
530 | PINMUX_IPSR_DATA(IP6_31_29, AVB_TX_CLK), | |
531 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, ADIDATA, SEL_RAD_0), | |
532 | PINMUX_IPSR_MODSEL_DATA(IP6_31_29, AD_DI, SEL_ADI_0), | |
533 | ||
534 | /* IPSR7 */ | |
535 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ETH_CRS_DV, SEL_ETH_0), | |
536 | PINMUX_IPSR_DATA(IP7_2_0, VI0_G1), | |
537 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1), | |
538 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3), | |
539 | PINMUX_IPSR_DATA(IP7_2_0, AVB_TXD0), | |
540 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, ADICS_SAMP, SEL_RAD_0), | |
541 | PINMUX_IPSR_MODSEL_DATA(IP7_2_0, AD_DO, SEL_ADI_0), | |
542 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ETH_RX_ER, SEL_ETH_0), | |
543 | PINMUX_IPSR_DATA(IP7_5_3, VI0_G2), | |
544 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1), | |
545 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, CAN0_RX_B, SEL_CAN0_1), | |
546 | PINMUX_IPSR_DATA(IP7_5_3, AVB_TXD1), | |
547 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, ADICLK, SEL_RAD_0), | |
548 | PINMUX_IPSR_MODSEL_DATA(IP7_5_3, AD_CLK, SEL_ADI_0), | |
549 | PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ETH_RXD0, SEL_ETH_0), | |
550 | PINMUX_IPSR_DATA(IP7_8_6, VI0_G3), | |
551 | PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1), | |
552 | PINMUX_IPSR_MODSEL_DATA(IP7_8_6, CAN0_TX_B, SEL_CAN0_1), | |
553 | PINMUX_IPSR_DATA(IP7_8_6, AVB_TXD2), | |
554 | PINMUX_IPSR_MODSEL_DATA(IP7_8_6, ADICHS0, SEL_RAD_0), | |
555 | PINMUX_IPSR_MODSEL_DATA(IP7_8_6, AD_NCS_N, SEL_ADI_0), | |
556 | PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ETH_RXD1, SEL_ETH_0), | |
557 | PINMUX_IPSR_DATA(IP7_11_9, VI0_G4), | |
558 | PINMUX_IPSR_MODSEL_DATA(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1), | |
559 | PINMUX_IPSR_MODSEL_DATA(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3), | |
560 | PINMUX_IPSR_DATA(IP7_11_9, AVB_TXD3), | |
561 | PINMUX_IPSR_MODSEL_DATA(IP7_11_9, ADICHS1, SEL_RAD_0), | |
562 | PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ETH_LINK, SEL_ETH_0), | |
563 | PINMUX_IPSR_DATA(IP7_14_12, VI0_G5), | |
564 | PINMUX_IPSR_MODSEL_DATA(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1), | |
565 | PINMUX_IPSR_MODSEL_DATA(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3), | |
566 | PINMUX_IPSR_DATA(IP7_14_12, AVB_TXD4), | |
567 | PINMUX_IPSR_MODSEL_DATA(IP7_14_12, ADICHS2, SEL_RAD_0), | |
568 | PINMUX_IPSR_MODSEL_DATA(IP7_17_15, ETH_REFCLK, SEL_ETH_0), | |
569 | PINMUX_IPSR_DATA(IP7_17_15, VI0_G6), | |
570 | PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2), | |
571 | PINMUX_IPSR_DATA(IP7_17_15, AVB_TXD5), | |
572 | PINMUX_IPSR_MODSEL_DATA(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1), | |
573 | PINMUX_IPSR_MODSEL_DATA(IP7_20_18, ETH_TXD1, SEL_ETH_0), | |
574 | PINMUX_IPSR_DATA(IP7_20_18, VI0_G7), | |
575 | PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2), | |
576 | PINMUX_IPSR_MODSEL_DATA(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3), | |
577 | PINMUX_IPSR_DATA(IP7_20_18, AVB_TXD6), | |
578 | PINMUX_IPSR_MODSEL_DATA(IP7_20_18, SSI_WS5_B, SEL_SSI5_1), | |
579 | PINMUX_IPSR_MODSEL_DATA(IP7_23_21, ETH_TX_EN, SEL_ETH_0), | |
580 | PINMUX_IPSR_DATA(IP7_23_21, VI0_R0), | |
581 | PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2), | |
582 | PINMUX_IPSR_MODSEL_DATA(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3), | |
583 | PINMUX_IPSR_DATA(IP7_23_21, AVB_TXD7), | |
584 | PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1), | |
585 | PINMUX_IPSR_MODSEL_DATA(IP7_26_24, ETH_MAGIC, SEL_ETH_0), | |
586 | PINMUX_IPSR_DATA(IP7_26_24, VI0_R1), | |
587 | PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1), | |
588 | PINMUX_IPSR_DATA(IP7_26_24, AVB_TX_ER), | |
589 | PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1), | |
590 | PINMUX_IPSR_MODSEL_DATA(IP7_29_27, ETH_TXD0, SEL_ETH_0), | |
591 | PINMUX_IPSR_DATA(IP7_29_27, VI0_R2), | |
592 | PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1), | |
593 | PINMUX_IPSR_MODSEL_DATA(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4), | |
594 | PINMUX_IPSR_DATA(IP7_29_27, AVB_GTX_CLK), | |
595 | PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_WS6_B, SEL_SSI6_1), | |
596 | PINMUX_IPSR_DATA(IP7_31, DREQ0_N), | |
597 | PINMUX_IPSR_DATA(IP7_31, SCIFB1_RXD), | |
598 | ||
599 | /* IPSR8 */ | |
600 | PINMUX_IPSR_MODSEL_DATA(IP8_2_0, ETH_MDC, SEL_ETH_0), | |
601 | PINMUX_IPSR_DATA(IP8_2_0, VI0_R3), | |
602 | PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1), | |
603 | PINMUX_IPSR_MODSEL_DATA(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4), | |
604 | PINMUX_IPSR_DATA(IP8_2_0, AVB_MDC), | |
605 | PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1), | |
606 | PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0), | |
607 | PINMUX_IPSR_DATA(IP8_5_3, VI0_R4), | |
608 | PINMUX_IPSR_MODSEL_DATA(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2), | |
609 | PINMUX_IPSR_MODSEL_DATA(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1), | |
610 | PINMUX_IPSR_DATA(IP8_5_3, AVB_MDIO), | |
611 | PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1), | |
612 | PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0), | |
613 | PINMUX_IPSR_DATA(IP8_8_6, VI0_R5), | |
614 | PINMUX_IPSR_MODSEL_DATA(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2), | |
615 | PINMUX_IPSR_MODSEL_DATA(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1), | |
616 | PINMUX_IPSR_DATA(IP8_5_3, AVB_LINK), | |
617 | PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_WS78_B, SEL_SSI7_1), | |
618 | PINMUX_IPSR_DATA(IP8_11_9, HSCIF0_HCTS_N), | |
619 | PINMUX_IPSR_DATA(IP8_11_9, VI0_R6), | |
620 | PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3), | |
621 | PINMUX_IPSR_MODSEL_DATA(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4), | |
622 | PINMUX_IPSR_DATA(IP8_11_9, AVB_MAGIC), | |
623 | PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1), | |
624 | PINMUX_IPSR_DATA(IP8_14_12, HSCIF0_HRTS_N), | |
625 | PINMUX_IPSR_DATA(IP8_14_12, VI0_R7), | |
626 | PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3), | |
627 | PINMUX_IPSR_MODSEL_DATA(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4), | |
628 | PINMUX_IPSR_DATA(IP8_14_12, AVB_PHY_INT), | |
629 | PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1), | |
630 | PINMUX_IPSR_MODSEL_DATA(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0), | |
631 | PINMUX_IPSR_MODSEL_DATA(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1), | |
632 | PINMUX_IPSR_DATA(IP8_16_15, AVB_CRS), | |
633 | PINMUX_IPSR_MODSEL_DATA(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1), | |
634 | PINMUX_IPSR_MODSEL_DATA(IP8_19_17, I2C0_SCL, SEL_I2C00_0), | |
635 | PINMUX_IPSR_MODSEL_DATA(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2), | |
636 | PINMUX_IPSR_DATA(IP8_19_17, PWM5), | |
637 | PINMUX_IPSR_MODSEL_DATA(IP8_19_17, TCLK1_B, SEL_TMU_1), | |
638 | PINMUX_IPSR_DATA(IP8_19_17, AVB_GTXREFCLK), | |
639 | PINMUX_IPSR_MODSEL_DATA(IP8_19_17, CAN1_RX_D, SEL_CAN1_3), | |
640 | PINMUX_IPSR_DATA(IP8_19_17, TPUTO0_B), | |
641 | PINMUX_IPSR_MODSEL_DATA(IP8_22_20, I2C0_SDA, SEL_I2C00_0), | |
642 | PINMUX_IPSR_MODSEL_DATA(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2), | |
643 | PINMUX_IPSR_DATA(IP8_22_20, TPUTO0), | |
644 | PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN_CLK, SEL_CAN_0), | |
645 | PINMUX_IPSR_DATA(IP8_22_20, DVC_MUTE), | |
646 | PINMUX_IPSR_MODSEL_DATA(IP8_22_20, CAN1_TX_D, SEL_CAN1_3), | |
647 | PINMUX_IPSR_MODSEL_DATA(IP8_25_23, I2C1_SCL, SEL_I2C01_0), | |
648 | PINMUX_IPSR_MODSEL_DATA(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0), | |
649 | PINMUX_IPSR_DATA(IP8_25_23, PWM5_B), | |
650 | PINMUX_IPSR_DATA(IP8_25_23, DU1_DR0), | |
651 | PINMUX_IPSR_MODSEL_DATA(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1), | |
652 | PINMUX_IPSR_MODSEL_DATA(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3), | |
653 | PINMUX_IPSR_DATA(IP8_25_23, TPUTO1_B), | |
654 | PINMUX_IPSR_MODSEL_DATA(IP8_28_26, I2C1_SDA, SEL_I2C01_0), | |
655 | PINMUX_IPSR_MODSEL_DATA(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0), | |
656 | PINMUX_IPSR_DATA(IP8_28_26, IRQ5), | |
657 | PINMUX_IPSR_DATA(IP8_28_26, DU1_DR1), | |
658 | PINMUX_IPSR_MODSEL_DATA(IP8_28_26, RIF1_CLK_B, SEL_DR2_1), | |
659 | PINMUX_IPSR_MODSEL_DATA(IP8_28_26, TS_SCK_D, SEL_TSIF0_3), | |
660 | PINMUX_IPSR_MODSEL_DATA(IP8_28_26, BPFCLK_C, SEL_DARC_2), | |
661 | PINMUX_IPSR_DATA(IP8_31_29, MSIOF0_RXD), | |
662 | PINMUX_IPSR_MODSEL_DATA(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0), | |
663 | PINMUX_IPSR_MODSEL_DATA(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2), | |
664 | PINMUX_IPSR_DATA(IP8_31_29, DU1_DR2), | |
665 | PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RIF1_D0_B, SEL_DR2_1), | |
666 | PINMUX_IPSR_MODSEL_DATA(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3), | |
667 | PINMUX_IPSR_MODSEL_DATA(IP8_31_29, FMCLK_C, SEL_DARC_2), | |
668 | PINMUX_IPSR_MODSEL_DATA(IP8_31_29, RDS_CLK, SEL_RDS_0), | |
669 | ||
670 | /* | |
671 | * From IPSR9 to IPSR10 have been removed because they does not use. | |
672 | */ | |
673 | ||
674 | /* IPSR11 */ | |
675 | PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SSI_WS5, SEL_SSI5_0), | |
676 | PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0), | |
677 | PINMUX_IPSR_MODSEL_DATA(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2), | |
678 | PINMUX_IPSR_DATA(IP11_2_0, DU1_DOTCLKOUT0), | |
679 | PINMUX_IPSR_DATA(IP11_2_0, CAN_DEBUGOUT11), | |
680 | PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SSI_SDATA5, SEL_SSI5_0), | |
681 | PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0), | |
682 | PINMUX_IPSR_MODSEL_DATA(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2), | |
683 | PINMUX_IPSR_DATA(IP11_5_3, DU1_DOTCLKOUT1), | |
684 | PINMUX_IPSR_DATA(IP11_5_3, CAN_DEBUGOUT12), | |
685 | PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SSI_SCK6, SEL_SSI6_0), | |
686 | PINMUX_IPSR_MODSEL_DATA(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1), | |
687 | PINMUX_IPSR_DATA(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC), | |
688 | PINMUX_IPSR_DATA(IP11_7_6, CAN_DEBUGOUT13), | |
689 | PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SSI_WS6, SEL_SSI6_0), | |
690 | PINMUX_IPSR_MODSEL_DATA(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1), | |
691 | PINMUX_IPSR_MODSEL_DATA(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2), | |
692 | PINMUX_IPSR_DATA(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC), | |
693 | PINMUX_IPSR_DATA(IP11_10_8, CAN_DEBUGOUT14), | |
694 | PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SSI_SDATA6, SEL_SSI6_0), | |
695 | PINMUX_IPSR_MODSEL_DATA(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1), | |
696 | PINMUX_IPSR_MODSEL_DATA(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2), | |
697 | PINMUX_IPSR_DATA(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE), | |
698 | PINMUX_IPSR_DATA(IP11_13_11, CAN_DEBUGOUT15), | |
699 | PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SSI_SCK78, SEL_SSI7_0), | |
700 | PINMUX_IPSR_MODSEL_DATA(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1), | |
701 | PINMUX_IPSR_MODSEL_DATA(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2), | |
702 | PINMUX_IPSR_DATA(IP11_15_14, DU1_DISP), | |
703 | PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SSI_WS78, SEL_SSI7_0), | |
704 | PINMUX_IPSR_MODSEL_DATA(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1), | |
705 | PINMUX_IPSR_MODSEL_DATA(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2), | |
706 | PINMUX_IPSR_DATA(IP11_17_16, DU1_CDE), | |
707 | PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SSI_SDATA7, SEL_SSI7_0), | |
708 | PINMUX_IPSR_MODSEL_DATA(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1), | |
709 | PINMUX_IPSR_DATA(IP11_20_18, IRQ8), | |
710 | PINMUX_IPSR_MODSEL_DATA(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3), | |
711 | PINMUX_IPSR_MODSEL_DATA(IP11_20_18, CAN_CLK_D, SEL_CAN_3), | |
712 | PINMUX_IPSR_DATA(IP11_20_18, PCMOE_N), | |
713 | PINMUX_IPSR_DATA(IP11_23_21, SSI_SCK0129), | |
714 | PINMUX_IPSR_MODSEL_DATA(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1), | |
715 | PINMUX_IPSR_MODSEL_DATA(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3), | |
716 | PINMUX_IPSR_MODSEL_DATA(IP11_23_21, ADIDATA_B, SEL_RAD_1), | |
717 | PINMUX_IPSR_MODSEL_DATA(IP11_23_21, AD_DI_B, SEL_ADI_1), | |
718 | PINMUX_IPSR_DATA(IP11_23_21, PCMWE_N), | |
719 | PINMUX_IPSR_DATA(IP11_26_24, SSI_WS0129), | |
720 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1), | |
721 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3), | |
722 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1), | |
723 | PINMUX_IPSR_MODSEL_DATA(IP11_26_24, AD_DO_B, SEL_ADI_1), | |
724 | PINMUX_IPSR_DATA(IP11_29_27, SSI_SDATA0), | |
725 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1), | |
726 | PINMUX_IPSR_DATA(IP11_29_27, PWM0_B), | |
727 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, ADICLK_B, SEL_RAD_1), | |
728 | PINMUX_IPSR_MODSEL_DATA(IP11_29_27, AD_CLK_B, SEL_ADI_1), | |
729 | ||
730 | /* | |
731 | * From IPSR12 to IPSR13 have been removed because they does not use. | |
732 | */ | |
733 | }; | |
734 | ||
735 | static struct pinmux_gpio pinmux_gpios[] = { | |
736 | PINMUX_GPIO_GP_ALL(), | |
737 | ||
738 | GPIO_FN(A2), GPIO_FN(WE0_N), GPIO_FN(WE1_N), GPIO_FN(DACK0), | |
739 | GPIO_FN(USB0_PWEN), GPIO_FN(USB0_OVC), GPIO_FN(USB1_PWEN), | |
740 | GPIO_FN(USB1_OVC), GPIO_FN(SD0_CLK), GPIO_FN(SD0_CMD), | |
741 | GPIO_FN(SD0_DATA0), GPIO_FN(SD0_DATA1), GPIO_FN(SD0_DATA2), | |
742 | GPIO_FN(SD0_DATA3), GPIO_FN(SD0_CD), GPIO_FN(SD0_WP), | |
743 | GPIO_FN(SD1_CLK), GPIO_FN(SD1_CMD), GPIO_FN(SD1_DATA0), | |
744 | GPIO_FN(SD1_DATA1), GPIO_FN(SD1_DATA2), GPIO_FN(SD1_DATA3), | |
745 | ||
25f9613f NI |
746 | /* IPSR0 */ |
747 | GPIO_FN(SD1_CD), GPIO_FN(CAN0_RX), GPIO_FN(SD1_WP), GPIO_FN(IRQ7), | |
748 | GPIO_FN(CAN0_TX), GPIO_FN(MMC_CLK), GPIO_FN(SD2_CLK), GPIO_FN(MMC_CMD), | |
749 | GPIO_FN(SD2_CMD), GPIO_FN(MMC_D0), GPIO_FN(SD2_DATA0), GPIO_FN(MMC_D1), | |
750 | GPIO_FN(SD2_DATA1), GPIO_FN(MMC_D2), GPIO_FN(SD2_DATA2), | |
751 | GPIO_FN(MMC_D3), GPIO_FN(SD2_DATA3), GPIO_FN(MMC_D4), | |
752 | GPIO_FN(SD2_CD), GPIO_FN(MMC_D5), GPIO_FN(SD2_WP), GPIO_FN(MMC_D6), | |
753 | GPIO_FN(SCIF0_RXD), GPIO_FN(I2C2_SCL_B), GPIO_FN(CAN1_RX), | |
754 | GPIO_FN(MMC_D7), GPIO_FN(SCIF0_TXD), GPIO_FN(I2C2_SDA_B), | |
755 | GPIO_FN(CAN1_TX), GPIO_FN(D0), GPIO_FN(SCIFA3_SCK_B), GPIO_FN(IRQ4), | |
756 | GPIO_FN(D1), GPIO_FN(SCIFA3_RXD_B), GPIO_FN(D2), GPIO_FN(SCIFA3_TXD_B), | |
757 | GPIO_FN(D3), GPIO_FN(I2C3_SCL_B), GPIO_FN(SCIF5_RXD_B), GPIO_FN(D4), | |
758 | GPIO_FN(I2C3_SDA_B), GPIO_FN(SCIF5_TXD_B), GPIO_FN(D5), | |
759 | GPIO_FN(SCIF4_RXD_B), GPIO_FN(I2C0_SCL_D), | |
760 | ||
fafcfc5a | 761 | /* |
25f9613f | 762 | * From IPSR1 to IPSR5 have been removed because they does not use. |
fafcfc5a NI |
763 | */ |
764 | ||
765 | /* IPSR6 */ | |
766 | GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(QSTB_QHE), | |
767 | GPIO_FN(CC50_STATE28), GPIO_FN(DU0_EXODDF_DU0_ODDF_DISP_CDE), | |
768 | GPIO_FN(QCPV_QDE), GPIO_FN(CC50_STATE29), GPIO_FN(DU0_DISP), | |
769 | GPIO_FN(QPOLA), GPIO_FN(CC50_STATE30), GPIO_FN(DU0_CDE), GPIO_FN(QPOLB), | |
770 | GPIO_FN(CC50_STATE31), GPIO_FN(VI0_CLK), GPIO_FN(AVB_RX_CLK), | |
771 | GPIO_FN(VI0_DATA0_VI0_B0), GPIO_FN(AVB_RX_DV), | |
772 | GPIO_FN(VI0_DATA1_VI0_B1), GPIO_FN(AVB_RXD0), GPIO_FN(VI0_DATA2_VI0_B2), | |
773 | GPIO_FN(AVB_RXD1), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(AVB_RXD2), | |
774 | GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(AVB_RXD3), GPIO_FN(VI0_DATA5_VI0_B5), | |
775 | GPIO_FN(AVB_RXD4), GPIO_FN(VI0_DATA6_VI0_B6), GPIO_FN(AVB_RXD5), | |
776 | GPIO_FN(VI0_DATA7_VI0_B7), GPIO_FN(AVB_RXD6), GPIO_FN(VI0_CLKENB), | |
777 | GPIO_FN(I2C3_SCL), GPIO_FN(SCIFA5_RXD_C), GPIO_FN(IETX_C), | |
778 | GPIO_FN(AVB_RXD7), GPIO_FN(VI0_FIELD), GPIO_FN(I2C3_SDA), | |
779 | GPIO_FN(SCIFA5_TXD_C), GPIO_FN(IECLK_C), GPIO_FN(AVB_RX_ER), | |
780 | GPIO_FN(VI0_HSYNC_N), GPIO_FN(SCIF0_RXD_B), GPIO_FN(I2C0_SCL_C), | |
781 | GPIO_FN(IERX_C), GPIO_FN(AVB_COL), GPIO_FN(VI0_VSYNC_N), | |
782 | GPIO_FN(SCIF0_TXD_B), GPIO_FN(I2C0_SDA_C), GPIO_FN(AUDIO_CLKOUT_B), | |
783 | GPIO_FN(AVB_TX_EN), GPIO_FN(ETH_MDIO), GPIO_FN(VI0_G0), | |
784 | GPIO_FN(MSIOF2_RXD_B), GPIO_FN(IIC0_SCL_D), GPIO_FN(AVB_TX_CLK), | |
785 | GPIO_FN(ADIDATA), GPIO_FN(AD_DI), | |
786 | ||
787 | /* IPSR7 */ | |
788 | GPIO_FN(ETH_CRS_DV), GPIO_FN(VI0_G1), GPIO_FN(MSIOF2_TXD_B), | |
789 | GPIO_FN(IIC0_SDA_D), GPIO_FN(AVB_TXD0), GPIO_FN(ADICS_SAMP), | |
790 | GPIO_FN(AD_DO), GPIO_FN(ETH_RX_ER), GPIO_FN(VI0_G2), | |
791 | GPIO_FN(MSIOF2_SCK_B), GPIO_FN(CAN0_RX_B), GPIO_FN(AVB_TXD1), | |
792 | GPIO_FN(ADICLK), GPIO_FN(AD_CLK), GPIO_FN(ETH_RXD0), GPIO_FN(VI0_G3), | |
793 | GPIO_FN(MSIOF2_SYNC_B), GPIO_FN(CAN0_TX_B), GPIO_FN(AVB_TXD2), | |
794 | GPIO_FN(ADICHS0), GPIO_FN(AD_NCS_N), GPIO_FN(ETH_RXD1), | |
795 | GPIO_FN(VI0_G4), GPIO_FN(MSIOF2_SS1_B), GPIO_FN(SCIF4_RXD_D), | |
796 | GPIO_FN(AVB_TXD3), GPIO_FN(ADICHS1), GPIO_FN(ETH_LINK), GPIO_FN(VI0_G5), | |
797 | GPIO_FN(MSIOF2_SS2_B), GPIO_FN(SCIF4_TXD_D), GPIO_FN(AVB_TXD4), | |
798 | GPIO_FN(ADICHS2), GPIO_FN(ETH_REFCLK), GPIO_FN(VI0_G6), | |
799 | GPIO_FN(SCIF2_SCK_C), GPIO_FN(AVB_TXD5), GPIO_FN(SSI_SCK5_B), | |
800 | GPIO_FN(ETH_TXD1), GPIO_FN(VI0_G7), GPIO_FN(SCIF2_RXD_C), | |
801 | GPIO_FN(IIC1_SCL_D), GPIO_FN(AVB_TXD6), GPIO_FN(SSI_WS5_B), | |
802 | GPIO_FN(ETH_TX_EN), GPIO_FN(VI0_R0), GPIO_FN(SCIF2_TXD_C), | |
803 | GPIO_FN(IIC1_SDA_D), GPIO_FN(AVB_TXD7), GPIO_FN(SSI_SDATA5_B), | |
804 | GPIO_FN(ETH_MAGIC), GPIO_FN(VI0_R1), GPIO_FN(SCIF3_SCK_B), | |
805 | GPIO_FN(AVB_TX_ER), GPIO_FN(SSI_SCK6_B), GPIO_FN(ETH_TXD0), | |
806 | GPIO_FN(VI0_R2), GPIO_FN(SCIF3_RXD_B), GPIO_FN(I2C4_SCL_E), | |
807 | GPIO_FN(AVB_GTX_CLK), GPIO_FN(SSI_WS6_B), GPIO_FN(DREQ0_N), | |
808 | GPIO_FN(SCIFB1_RXD), | |
809 | ||
810 | /* IPSR8 */ | |
811 | GPIO_FN(ETH_MDC), GPIO_FN(VI0_R3), GPIO_FN(SCIF3_TXD_B), | |
812 | GPIO_FN(I2C4_SDA_E), GPIO_FN(AVB_MDC), GPIO_FN(SSI_SDATA6_B), | |
813 | GPIO_FN(HSCIF0_HRX), GPIO_FN(VI0_R4), GPIO_FN(I2C1_SCL_C), | |
814 | GPIO_FN(AUDIO_CLKA_B), GPIO_FN(AVB_MDIO), GPIO_FN(SSI_SCK78_B), | |
815 | GPIO_FN(HSCIF0_HTX), GPIO_FN(VI0_R5), GPIO_FN(I2C1_SDA_C), | |
816 | GPIO_FN(AUDIO_CLKB_B), GPIO_FN(AVB_LINK), GPIO_FN(SSI_WS78_B), | |
817 | GPIO_FN(HSCIF0_HCTS_N), GPIO_FN(VI0_R6), GPIO_FN(SCIF0_RXD_D), | |
818 | GPIO_FN(I2C0_SCL_E), GPIO_FN(AVB_MAGIC), GPIO_FN(SSI_SDATA7_B), | |
819 | GPIO_FN(HSCIF0_HRTS_N), GPIO_FN(VI0_R7), GPIO_FN(SCIF0_TXD_D), | |
820 | GPIO_FN(I2C0_SDA_E), GPIO_FN(AVB_PHY_INT), GPIO_FN(SSI_SDATA8_B), | |
821 | GPIO_FN(HSCIF0_HSCK), GPIO_FN(SCIF_CLK_B), GPIO_FN(AVB_CRS), | |
822 | GPIO_FN(AUDIO_CLKC_B), GPIO_FN(I2C0_SCL), GPIO_FN(SCIF0_RXD_C), | |
823 | GPIO_FN(PWM5), GPIO_FN(TCLK1_B), GPIO_FN(AVB_GTXREFCLK), | |
824 | GPIO_FN(CAN1_RX_D), GPIO_FN(TPUTO0_B), GPIO_FN(I2C0_SDA), | |
825 | GPIO_FN(SCIF0_TXD_C), GPIO_FN(TPUTO0), GPIO_FN(CAN_CLK), | |
826 | GPIO_FN(DVC_MUTE), GPIO_FN(CAN1_TX_D), GPIO_FN(I2C1_SCL), | |
827 | GPIO_FN(SCIF4_RXD), GPIO_FN(PWM5_B), GPIO_FN(DU1_DR0), | |
828 | GPIO_FN(RIF1_SYNC_B), GPIO_FN(TS_SDATA_D), GPIO_FN(TPUTO1_B), | |
829 | GPIO_FN(I2C1_SDA), GPIO_FN(SCIF4_TXD), GPIO_FN(IRQ5), | |
830 | GPIO_FN(DU1_DR1), GPIO_FN(RIF1_CLK_B), GPIO_FN(TS_SCK_D), | |
831 | GPIO_FN(BPFCLK_C), GPIO_FN(MSIOF0_RXD), GPIO_FN(SCIF5_RXD), | |
832 | GPIO_FN(I2C2_SCL_C), GPIO_FN(DU1_DR2), GPIO_FN(RIF1_D0_B), | |
833 | GPIO_FN(TS_SDEN_D), GPIO_FN(FMCLK_C), GPIO_FN(RDS_CLK), | |
834 | ||
835 | /* | |
836 | * From IPSR9 to IPSR10 have been removed because they does not use. | |
837 | */ | |
838 | ||
839 | /* IPSR11 */ | |
840 | GPIO_FN(SSI_WS5), GPIO_FN(SCIFA3_RXD), GPIO_FN(I2C3_SCL_C), | |
841 | GPIO_FN(DU1_DOTCLKOUT0), GPIO_FN(CAN_DEBUGOUT11), GPIO_FN(SSI_SDATA5), | |
842 | GPIO_FN(SCIFA3_TXD), GPIO_FN(I2C3_SDA_C), GPIO_FN(DU1_DOTCLKOUT1), | |
843 | GPIO_FN(CAN_DEBUGOUT12), GPIO_FN(SSI_SCK6), GPIO_FN(SCIFA1_SCK_B), | |
844 | GPIO_FN(DU1_EXHSYNC_DU1_HSYNC), GPIO_FN(CAN_DEBUGOUT13), | |
845 | GPIO_FN(SSI_WS6), GPIO_FN(SCIFA1_RXD_B), GPIO_FN(I2C4_SCL_C), | |
846 | GPIO_FN(DU1_EXVSYNC_DU1_VSYNC), GPIO_FN(CAN_DEBUGOUT14), | |
847 | GPIO_FN(SSI_SDATA6), GPIO_FN(SCIFA1_TXD_B), GPIO_FN(I2C4_SDA_C), | |
848 | GPIO_FN(DU1_EXODDF_DU1_ODDF_DISP_CDE), GPIO_FN(CAN_DEBUGOUT15), | |
849 | GPIO_FN(SSI_SCK78), GPIO_FN(SCIFA2_SCK_B), GPIO_FN(IIC0_SDA_C), | |
850 | GPIO_FN(DU1_DISP), GPIO_FN(SSI_WS78), GPIO_FN(SCIFA2_RXD_B), | |
851 | GPIO_FN(IIC0_SCL_C), GPIO_FN(DU1_CDE), GPIO_FN(SSI_SDATA7), | |
852 | GPIO_FN(SCIFA2_TXD_B), GPIO_FN(IRQ8), GPIO_FN(AUDIO_CLKA_D), | |
853 | GPIO_FN(CAN_CLK_D), GPIO_FN(PCMOE_N), GPIO_FN(SSI_SCK0129), | |
854 | GPIO_FN(MSIOF1_RXD_B), GPIO_FN(SCIF5_RXD_D), GPIO_FN(ADIDATA_B), | |
855 | GPIO_FN(AD_DI_B), GPIO_FN(PCMWE_N), GPIO_FN(SSI_WS0129), | |
856 | GPIO_FN(MSIOF1_TXD_B), GPIO_FN(SCIF5_TXD_D), GPIO_FN(ADICS_SAMP_B), | |
857 | GPIO_FN(AD_DO_B), GPIO_FN(SSI_SDATA0), GPIO_FN(MSIOF1_SCK_B), | |
858 | GPIO_FN(PWM0_B), GPIO_FN(ADICLK_B), GPIO_FN(AD_CLK_B), | |
859 | ||
860 | /* | |
861 | * From IPSR12 to IPSR13 have been removed because they does not use. | |
862 | */ | |
863 | }; | |
864 | ||
865 | static struct pinmux_cfg_reg pinmux_config_regs[] = { | |
866 | { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { | |
867 | GP_0_31_FN, FN_IP2_17_16, | |
868 | GP_0_30_FN, FN_IP2_15_14, | |
869 | GP_0_29_FN, FN_IP2_13_12, | |
870 | GP_0_28_FN, FN_IP2_11_10, | |
871 | GP_0_27_FN, FN_IP2_9_8, | |
872 | GP_0_26_FN, FN_IP2_7_6, | |
873 | GP_0_25_FN, FN_IP2_5_4, | |
874 | GP_0_24_FN, FN_IP2_3_2, | |
875 | GP_0_23_FN, FN_IP2_1_0, | |
876 | GP_0_22_FN, FN_IP1_31_30, | |
877 | GP_0_21_FN, FN_IP1_29_28, | |
878 | GP_0_20_FN, FN_IP1_27, | |
879 | GP_0_19_FN, FN_IP1_26, | |
880 | GP_0_18_FN, FN_A2, | |
881 | GP_0_17_FN, FN_IP1_24, | |
882 | GP_0_16_FN, FN_IP1_23_22, | |
883 | GP_0_15_FN, FN_IP1_21_20, | |
884 | GP_0_14_FN, FN_IP1_19_18, | |
885 | GP_0_13_FN, FN_IP1_17_15, | |
886 | GP_0_12_FN, FN_IP1_14_13, | |
887 | GP_0_11_FN, FN_IP1_12_11, | |
888 | GP_0_10_FN, FN_IP1_10_8, | |
889 | GP_0_9_FN, FN_IP1_7_6, | |
890 | GP_0_8_FN, FN_IP1_5_4, | |
891 | GP_0_7_FN, FN_IP1_3_2, | |
892 | GP_0_6_FN, FN_IP1_1_0, | |
893 | GP_0_5_FN, FN_IP0_31_30, | |
894 | GP_0_4_FN, FN_IP0_29_28, | |
895 | GP_0_3_FN, FN_IP0_27_26, | |
896 | GP_0_2_FN, FN_IP0_25, | |
897 | GP_0_1_FN, FN_IP0_24, | |
898 | GP_0_0_FN, FN_IP0_23_22, } | |
899 | }, | |
900 | { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) { | |
901 | 0, 0, | |
902 | 0, 0, | |
903 | 0, 0, | |
904 | 0, 0, | |
905 | 0, 0, | |
906 | 0, 0, | |
907 | GP_1_25_FN, FN_DACK0, | |
908 | GP_1_24_FN, FN_IP7_31, | |
909 | GP_1_23_FN, FN_IP4_1_0, | |
910 | GP_1_22_FN, FN_WE1_N, | |
911 | GP_1_21_FN, FN_WE0_N, | |
912 | GP_1_20_FN, FN_IP3_31, | |
913 | GP_1_19_FN, FN_IP3_30, | |
914 | GP_1_18_FN, FN_IP3_29_27, | |
915 | GP_1_17_FN, FN_IP3_26_24, | |
916 | GP_1_16_FN, FN_IP3_23_21, | |
917 | GP_1_15_FN, FN_IP3_20_18, | |
918 | GP_1_14_FN, FN_IP3_17_15, | |
919 | GP_1_13_FN, FN_IP3_14_13, | |
920 | GP_1_12_FN, FN_IP3_12, | |
921 | GP_1_11_FN, FN_IP3_11, | |
922 | GP_1_10_FN, FN_IP3_10, | |
923 | GP_1_9_FN, FN_IP3_9_8, | |
924 | GP_1_8_FN, FN_IP3_7_6, | |
925 | GP_1_7_FN, FN_IP3_5_4, | |
926 | GP_1_6_FN, FN_IP3_3_2, | |
927 | GP_1_5_FN, FN_IP3_1_0, | |
928 | GP_1_4_FN, FN_IP2_31_30, | |
929 | GP_1_3_FN, FN_IP2_29_27, | |
930 | GP_1_2_FN, FN_IP2_26_24, | |
931 | GP_1_1_FN, FN_IP2_23_21, | |
932 | GP_1_0_FN, FN_IP2_20_18, } | |
933 | }, | |
934 | { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) { | |
935 | GP_2_31_FN, FN_IP6_7_6, | |
936 | GP_2_30_FN, FN_IP6_5_4, | |
937 | GP_2_29_FN, FN_IP6_3_2, | |
938 | GP_2_28_FN, FN_IP6_1_0, | |
939 | GP_2_27_FN, FN_IP5_31_30, | |
940 | GP_2_26_FN, FN_IP5_29_28, | |
941 | GP_2_25_FN, FN_IP5_27_26, | |
942 | GP_2_24_FN, FN_IP5_25_24, | |
943 | GP_2_23_FN, FN_IP5_23_22, | |
944 | GP_2_22_FN, FN_IP5_21_20, | |
945 | GP_2_21_FN, FN_IP5_19_18, | |
946 | GP_2_20_FN, FN_IP5_17_16, | |
947 | GP_2_19_FN, FN_IP5_15_14, | |
948 | GP_2_18_FN, FN_IP5_13_12, | |
949 | GP_2_17_FN, FN_IP5_11_9, | |
950 | GP_2_16_FN, FN_IP5_8_6, | |
951 | GP_2_15_FN, FN_IP5_5_4, | |
952 | GP_2_14_FN, FN_IP5_3_2, | |
953 | GP_2_13_FN, FN_IP5_1_0, | |
954 | GP_2_12_FN, FN_IP4_31_30, | |
955 | GP_2_11_FN, FN_IP4_29_28, | |
956 | GP_2_10_FN, FN_IP4_27_26, | |
957 | GP_2_9_FN, FN_IP4_25_23, | |
958 | GP_2_8_FN, FN_IP4_22_20, | |
959 | GP_2_7_FN, FN_IP4_19_18, | |
960 | GP_2_6_FN, FN_IP4_17_16, | |
961 | GP_2_5_FN, FN_IP4_15_14, | |
962 | GP_2_4_FN, FN_IP4_13_12, | |
963 | GP_2_3_FN, FN_IP4_11_10, | |
964 | GP_2_2_FN, FN_IP4_9_8, | |
965 | GP_2_1_FN, FN_IP4_7_5, | |
966 | GP_2_0_FN, FN_IP4_4_2 } | |
967 | }, | |
968 | { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) { | |
969 | GP_3_31_FN, FN_IP8_22_20, | |
970 | GP_3_30_FN, FN_IP8_19_17, | |
971 | GP_3_29_FN, FN_IP8_16_15, | |
972 | GP_3_28_FN, FN_IP8_14_12, | |
973 | GP_3_27_FN, FN_IP8_11_9, | |
974 | GP_3_26_FN, FN_IP8_8_6, | |
975 | GP_3_25_FN, FN_IP8_5_3, | |
976 | GP_3_24_FN, FN_IP8_2_0, | |
977 | GP_3_23_FN, FN_IP7_29_27, | |
978 | GP_3_22_FN, FN_IP7_26_24, | |
979 | GP_3_21_FN, FN_IP7_23_21, | |
980 | GP_3_20_FN, FN_IP7_20_18, | |
981 | GP_3_19_FN, FN_IP7_17_15, | |
982 | GP_3_18_FN, FN_IP7_14_12, | |
983 | GP_3_17_FN, FN_IP7_11_9, | |
984 | GP_3_16_FN, FN_IP7_8_6, | |
985 | GP_3_15_FN, FN_IP7_5_3, | |
986 | GP_3_14_FN, FN_IP7_2_0, | |
987 | GP_3_13_FN, FN_IP6_31_29, | |
988 | GP_3_12_FN, FN_IP6_28_26, | |
989 | GP_3_11_FN, FN_IP6_25_23, | |
990 | GP_3_10_FN, FN_IP6_22_20, | |
991 | GP_3_9_FN, FN_IP6_19_17, | |
992 | GP_3_8_FN, FN_IP6_16, | |
993 | GP_3_7_FN, FN_IP6_15, | |
994 | GP_3_6_FN, FN_IP6_14, | |
995 | GP_3_5_FN, FN_IP6_13, | |
996 | GP_3_4_FN, FN_IP6_12, | |
997 | GP_3_3_FN, FN_IP6_11, | |
998 | GP_3_2_FN, FN_IP6_10, | |
999 | GP_3_1_FN, FN_IP6_9, | |
1000 | GP_3_0_FN, FN_IP6_8 } | |
1001 | }, | |
1002 | { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) { | |
1003 | GP_4_31_FN, FN_IP11_17_16, | |
1004 | GP_4_30_FN, FN_IP11_15_14, | |
1005 | GP_4_29_FN, FN_IP11_13_11, | |
1006 | GP_4_28_FN, FN_IP11_10_8, | |
1007 | GP_4_27_FN, FN_IP11_7_6, | |
1008 | GP_4_26_FN, FN_IP11_5_3, | |
1009 | GP_4_25_FN, FN_IP11_2_0, | |
1010 | GP_4_24_FN, FN_IP10_31_30, | |
1011 | GP_4_23_FN, FN_IP10_29_27, | |
1012 | GP_4_22_FN, FN_IP10_26_24, | |
1013 | GP_4_21_FN, FN_IP10_23_21, | |
1014 | GP_4_20_FN, FN_IP10_20_18, | |
1015 | GP_4_19_FN, FN_IP10_17_15, | |
1016 | GP_4_18_FN, FN_IP10_14_12, | |
1017 | GP_4_17_FN, FN_IP10_11_9, | |
1018 | GP_4_16_FN, FN_IP10_8_6, | |
1019 | GP_4_15_FN, FN_IP10_5_3, | |
1020 | GP_4_14_FN, FN_IP10_2_0, | |
1021 | GP_4_13_FN, FN_IP9_30_28, | |
1022 | GP_4_12_FN, FN_IP9_27_25, | |
1023 | GP_4_11_FN, FN_IP9_24_22, | |
1024 | GP_4_10_FN, FN_IP9_21_19, | |
1025 | GP_4_9_FN, FN_IP9_18_17, | |
1026 | GP_4_8_FN, FN_IP9_16_15, | |
1027 | GP_4_7_FN, FN_IP9_14_12, | |
1028 | GP_4_6_FN, FN_IP9_11_9, | |
1029 | GP_4_5_FN, FN_IP9_8_6, | |
1030 | GP_4_4_FN, FN_IP9_5_3, | |
1031 | GP_4_3_FN, FN_IP9_2_0, | |
1032 | GP_4_2_FN, FN_IP8_31_29, | |
1033 | GP_4_1_FN, FN_IP8_28_26, | |
1034 | GP_4_0_FN, FN_IP8_25_23 } | |
1035 | }, | |
1036 | { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) { | |
1037 | 0, 0, | |
1038 | 0, 0, | |
1039 | 0, 0, | |
1040 | 0, 0, | |
1041 | GP_5_27_FN, FN_USB1_OVC, | |
1042 | GP_5_26_FN, FN_USB1_PWEN, | |
1043 | GP_5_25_FN, FN_USB0_OVC, | |
1044 | GP_5_24_FN, FN_USB0_PWEN, | |
1045 | GP_5_23_FN, FN_IP13_26_24, | |
1046 | GP_5_22_FN, FN_IP13_23_21, | |
1047 | GP_5_21_FN, FN_IP13_20_18, | |
1048 | GP_5_20_FN, FN_IP13_17_15, | |
1049 | GP_5_19_FN, FN_IP13_14_12, | |
1050 | GP_5_18_FN, FN_IP13_11_9, | |
1051 | GP_5_17_FN, FN_IP13_8_6, | |
1052 | GP_5_16_FN, FN_IP13_5_3, | |
1053 | GP_5_15_FN, FN_IP13_2_0, | |
1054 | GP_5_14_FN, FN_IP12_29_27, | |
1055 | GP_5_13_FN, FN_IP12_26_24, | |
1056 | GP_5_12_FN, FN_IP12_23_21, | |
1057 | GP_5_11_FN, FN_IP12_20_18, | |
1058 | GP_5_10_FN, FN_IP12_17_15, | |
1059 | GP_5_9_FN, FN_IP12_14_13, | |
1060 | GP_5_8_FN, FN_IP12_12_11, | |
1061 | GP_5_7_FN, FN_IP12_10_9, | |
1062 | GP_5_6_FN, FN_IP12_8_6, | |
1063 | GP_5_5_FN, FN_IP12_5_3, | |
1064 | GP_5_4_FN, FN_IP12_2_0, | |
1065 | GP_5_3_FN, FN_IP11_29_27, | |
1066 | GP_5_2_FN, FN_IP11_26_24, | |
1067 | GP_5_1_FN, FN_IP11_23_21, | |
1068 | GP_5_0_FN, FN_IP11_20_18 } | |
1069 | }, | |
1070 | { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) { | |
1071 | 0, 0, | |
1072 | 0, 0, | |
1073 | 0, 0, | |
1074 | 0, 0, | |
1075 | 0, 0, | |
1076 | 0, 0, | |
1077 | GP_6_25_FN, FN_IP0_21_20, | |
1078 | GP_6_24_FN, FN_IP0_19_18, | |
1079 | GP_6_23_FN, FN_IP0_17, | |
1080 | GP_6_22_FN, FN_IP0_16, | |
1081 | GP_6_21_FN, FN_IP0_15, | |
1082 | GP_6_20_FN, FN_IP0_14, | |
1083 | GP_6_19_FN, FN_IP0_13, | |
1084 | GP_6_18_FN, FN_IP0_12, | |
1085 | GP_6_17_FN, FN_IP0_11, | |
1086 | GP_6_16_FN, FN_IP0_10, | |
1087 | GP_6_15_FN, FN_IP0_9_8, | |
1088 | GP_6_14_FN, FN_IP0_0, | |
1089 | GP_6_13_FN, FN_SD1_DATA3, | |
1090 | GP_6_12_FN, FN_SD1_DATA2, | |
1091 | GP_6_11_FN, FN_SD1_DATA1, | |
1092 | GP_6_10_FN, FN_SD1_DATA0, | |
1093 | GP_6_9_FN, FN_SD1_CMD, | |
1094 | GP_6_8_FN, FN_SD1_CLK, | |
1095 | GP_6_7_FN, FN_SD0_WP, | |
1096 | GP_6_6_FN, FN_SD0_CD, | |
1097 | GP_6_5_FN, FN_SD0_DATA3, | |
1098 | GP_6_4_FN, FN_SD0_DATA2, | |
1099 | GP_6_3_FN, FN_SD0_DATA1, | |
1100 | GP_6_2_FN, FN_SD0_DATA0, | |
1101 | GP_6_1_FN, FN_SD0_CMD, | |
1102 | GP_6_0_FN, FN_SD0_CLK } | |
1103 | }, | |
25f9613f NI |
1104 | { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32, |
1105 | 2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, | |
1106 | 2, 1, 1, 1, 1, 1, 1, 1, 1) { | |
1107 | /* IP0_31_30 [2] */ | |
1108 | FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0, | |
1109 | /* IP0_29_28 [2] */ | |
1110 | FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0, | |
1111 | /* IP0_27_26 [2] */ | |
1112 | FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0, | |
1113 | /* IP0_25 [1] */ | |
1114 | FN_D2, FN_SCIFA3_TXD_B, | |
1115 | /* IP0_24 [1] */ | |
1116 | FN_D1, FN_SCIFA3_RXD_B, | |
1117 | /* IP0_23_22 [2] */ | |
1118 | FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0, | |
1119 | /* IP0_21_20 [2] */ | |
1120 | FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX, | |
1121 | /* IP0_19_18 [2] */ | |
1122 | FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX, | |
1123 | /* IP0_17 [1] */ | |
1124 | FN_MMC_D5, FN_SD2_WP, | |
1125 | /* IP0_16 [1] */ | |
1126 | FN_MMC_D4, FN_SD2_CD, | |
1127 | /* IP0_15 [1] */ | |
1128 | FN_MMC_D3, FN_SD2_DATA3, | |
1129 | /* IP0_14 [1] */ | |
1130 | FN_MMC_D2, FN_SD2_DATA2, | |
1131 | /* IP0_13 [1] */ | |
1132 | FN_MMC_D1, FN_SD2_DATA1, | |
1133 | /* IP0_12 [1] */ | |
1134 | FN_MMC_D0, FN_SD2_DATA0, | |
1135 | /* IP0_11 [1] */ | |
1136 | FN_MMC_CMD, FN_SD2_CMD, | |
1137 | /* IP0_10 [1] */ | |
1138 | FN_MMC_CLK, FN_SD2_CLK, | |
1139 | /* IP0_9_8 [2] */ | |
1140 | FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0, | |
1141 | /* IP0_7 [1] */ | |
1142 | 0, 0, | |
1143 | /* IP0_6 [1] */ | |
1144 | 0, 0, | |
1145 | /* IP0_5 [1] */ | |
1146 | 0, 0, | |
1147 | /* IP0_4 [1] */ | |
1148 | 0, 0, | |
1149 | /* IP0_3 [1] */ | |
1150 | 0, 0, | |
1151 | /* IP0_2 [1] */ | |
1152 | 0, 0, | |
1153 | /* IP0_1 [1] */ | |
1154 | 0, 0, | |
1155 | /* IP0_0 [1] */ | |
1156 | FN_SD1_CD, FN_CAN0_RX, } | |
1157 | }, | |
fafcfc5a NI |
1158 | |
1159 | /* | |
25f9613f | 1160 | * From IPSR1 to IPSR5 have been removed because they does not use. |
fafcfc5a NI |
1161 | */ |
1162 | ||
1163 | { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32, | |
1164 | 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, | |
1165 | 2, 2) { | |
1166 | /* IP6_31_29 [3] */ | |
1167 | FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, | |
1168 | FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0, | |
1169 | /* IP6_28_26 [3] */ | |
1170 | FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C, | |
1171 | FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0, | |
1172 | /* IP6_25_23 [3] */ | |
1173 | FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, | |
1174 | FN_AVB_COL, 0, 0, 0, | |
1175 | /* IP6_22_20 [3] */ | |
1176 | FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, | |
1177 | FN_AVB_RX_ER, 0, 0, 0, | |
1178 | /* IP6_19_17 [3] */ | |
1179 | FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, | |
1180 | FN_AVB_RXD7, 0, 0, 0, | |
1181 | /* IP6_16 [1] */ | |
1182 | FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, | |
1183 | /* IP6_15 [1] */ | |
1184 | FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5, | |
1185 | /* IP6_14 [1] */ | |
1186 | FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, | |
1187 | /* IP6_13 [1] */ | |
1188 | FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3, | |
1189 | /* IP6_12 [1] */ | |
1190 | FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, | |
1191 | /* IP6_11 [1] */ | |
1192 | FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1, | |
1193 | /* IP6_10 [1] */ | |
1194 | FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, | |
1195 | /* IP6_9 [1] */ | |
1196 | FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV, | |
1197 | /* IP6_8 [1] */ | |
1198 | FN_VI0_CLK, FN_AVB_RX_CLK, | |
1199 | /* IP6_7_6 [2] */ | |
1200 | FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0, | |
1201 | /* IP6_5_4 [2] */ | |
1202 | FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0, | |
1203 | /* IP6_3_2 [2] */ | |
1204 | FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29, | |
1205 | /* IP6_1_0 [2] */ | |
1206 | FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, } | |
1207 | }, | |
1208 | { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32, | |
1209 | 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) { | |
1210 | /* IP7_31 [1] */ | |
1211 | FN_DREQ0_N, FN_SCIFB1_RXD, | |
1212 | /* IP7_30 [1] */ | |
1213 | 0, 0, | |
1214 | /* IP7_29_27 [3] */ | |
1215 | FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, | |
1216 | FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0, | |
1217 | /* IP7_26_24 [3] */ | |
1218 | FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, | |
1219 | FN_SSI_SCK6_B, 0, 0, 0, | |
1220 | /* IP7_23_21 [3] */ | |
1221 | FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D, | |
1222 | FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0, | |
1223 | /* IP7_20_18 [3] */ | |
1224 | FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D, | |
1225 | FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0, | |
1226 | /* IP7_17_15 [3] */ | |
1227 | FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5, | |
1228 | FN_SSI_SCK5_B, 0, 0, 0, | |
1229 | /* IP7_14_12 [3] */ | |
1230 | FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D, | |
1231 | FN_AVB_TXD4, FN_ADICHS2, 0, 0, | |
1232 | /* IP7_11_9 [3] */ | |
1233 | FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, | |
1234 | FN_AVB_TXD3, FN_ADICHS1, 0, 0, | |
1235 | /* IP7_8_6 [3] */ | |
1236 | FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, | |
1237 | FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0, | |
1238 | /* IP7_5_3 [3] */ | |
1239 | FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B, | |
1240 | FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0, | |
1241 | /* IP7_2_0 [3] */ | |
1242 | FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, | |
1243 | FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, } | |
1244 | }, | |
1245 | { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32, | |
1246 | 3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) { | |
1247 | /* IP8_31_29 [3] */ | |
1248 | FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2, | |
1249 | FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK, | |
1250 | /* IP8_28_26 [3] */ | |
1251 | FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, | |
1252 | FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0, | |
1253 | /* IP8_25_23 [3] */ | |
1254 | FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0, | |
1255 | FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0, | |
1256 | /* IP8_22_20 [3] */ | |
1257 | FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK, | |
1258 | FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0, | |
1259 | /* IP8_19_17 [3] */ | |
1260 | FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, | |
1261 | FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0, | |
1262 | /* IP8_16_15 [2] */ | |
1263 | FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B, | |
1264 | /* IP8_14_12 [3] */ | |
1265 | FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E, | |
1266 | FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0, | |
1267 | /* IP8_11_9 [3] */ | |
1268 | FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E, | |
1269 | FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0, | |
1270 | /* IP8_8_6 [3] */ | |
1271 | FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, | |
1272 | FN_AVB_LINK, FN_SSI_WS78_B, 0, 0, | |
1273 | /* IP8_5_3 [3] */ | |
1274 | FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B, | |
1275 | FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0, | |
1276 | /* IP8_2_0 [3] */ | |
1277 | FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, | |
1278 | FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, } | |
1279 | }, | |
1280 | ||
1281 | /* | |
1282 | * From IPSR9 to IPSR10 have been removed because they does not use. | |
1283 | */ | |
1284 | ||
1285 | { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32, | |
1286 | 2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) { | |
1287 | /* IP11_31_30 [2] */ | |
1288 | 0, 0, 0, 0, | |
1289 | /* IP11_29_27 [3] */ | |
1290 | FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B, | |
1291 | FN_AD_CLK_B, 0, 0, 0, | |
1292 | /* IP11_26_24 [3] */ | |
1293 | FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B, | |
1294 | FN_AD_DO_B, 0, 0, 0, | |
1295 | /* IP11_23_21 [3] */ | |
1296 | FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B, | |
1297 | FN_AD_DI_B, FN_PCMWE_N, 0, 0, | |
1298 | /* IP11_20_18 [3] */ | |
1299 | FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, | |
1300 | FN_CAN_CLK_D, FN_PCMOE_N, 0, 0, | |
1301 | /* IP11_17_16 [2] */ | |
1302 | FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, | |
1303 | /* IP11_15_14 [2] */ | |
1304 | FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, | |
1305 | /* IP11_13_11 [3] */ | |
1306 | FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C, | |
1307 | FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0, | |
1308 | /* IP11_10_8 [3] */ | |
1309 | FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, | |
1310 | FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0, | |
1311 | /* IP11_7_6 [2] */ | |
1312 | FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC, | |
1313 | FN_CAN_DEBUGOUT13, | |
1314 | /* IP11_5_3 [3] */ | |
1315 | FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1, | |
1316 | FN_CAN_DEBUGOUT12, 0, 0, 0, | |
1317 | /* IP11_2_0 [3] */ | |
1318 | FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0, | |
1319 | FN_CAN_DEBUGOUT11, 0, 0, 0, } | |
1320 | }, | |
1321 | ||
1322 | /* | |
1323 | * From IPSR12 to IPSR13 have been removed because they does not use. | |
1324 | */ | |
1325 | ||
1326 | { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32, | |
1327 | 2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3, | |
1328 | 2, 1) { | |
1329 | /* SEL_ADG [2] */ | |
1330 | FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3, | |
1331 | /* SEL_ADI [1] */ | |
1332 | FN_SEL_ADI_0, FN_SEL_ADI_1, | |
1333 | /* SEL_CAN [2] */ | |
1334 | FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3, | |
1335 | /* SEL_DARC [3] */ | |
1336 | FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3, | |
1337 | FN_SEL_DARC_4, 0, 0, 0, | |
1338 | /* SEL_DR0 [1] */ | |
1339 | FN_SEL_DR0_0, FN_SEL_DR0_1, | |
1340 | /* SEL_DR1 [1] */ | |
1341 | FN_SEL_DR1_0, FN_SEL_DR1_1, | |
1342 | /* SEL_DR2 [1] */ | |
1343 | FN_SEL_DR2_0, FN_SEL_DR2_1, | |
1344 | /* SEL_DR3 [1] */ | |
1345 | FN_SEL_DR3_0, FN_SEL_DR3_1, | |
1346 | /* SEL_ETH [1] */ | |
1347 | FN_SEL_ETH_0, FN_SEL_ETH_1, | |
1348 | /* SLE_FSN [1] */ | |
1349 | FN_SEL_FSN_0, FN_SEL_FSN_1, | |
1350 | /* SEL_IC200 [3] */ | |
1351 | FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3, | |
1352 | FN_SEL_I2C00_4, 0, 0, 0, | |
1353 | /* SEL_I2C01 [3] */ | |
1354 | FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3, | |
1355 | FN_SEL_I2C01_4, 0, 0, 0, | |
1356 | /* SEL_I2C02 [3] */ | |
1357 | FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, | |
1358 | FN_SEL_I2C02_4, 0, 0, 0, | |
1359 | /* SEL_I2C03 [3] */ | |
1360 | FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3, | |
1361 | FN_SEL_I2C03_4, 0, 0, 0, | |
1362 | /* SEL_I2C04 [3] */ | |
1363 | FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3, | |
1364 | FN_SEL_I2C04_4, 0, 0, 0, | |
1365 | /* SEL_IIC00 [2] */ | |
1366 | FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3, | |
1367 | /* SEL_AVB [1] */ | |
1368 | FN_SEL_AVB_0, FN_SEL_AVB_1, } | |
1369 | }, | |
1370 | { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32, | |
1371 | 2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1, | |
1372 | 2, 2, 2, 1, 1, 2) { | |
1373 | /* SEL_IEB [2] */ | |
1374 | FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0, | |
1375 | /* SEL_IIC0 [2] */ | |
1376 | FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, | |
1377 | /* SEL_LBS [1] */ | |
1378 | FN_SEL_LBS_0, FN_SEL_LBS_1, | |
1379 | /* SEL_MSI1 [1] */ | |
1380 | FN_SEL_MSI1_0, FN_SEL_MSI1_1, | |
1381 | /* SEL_MSI2 [1] */ | |
1382 | FN_SEL_MSI2_0, FN_SEL_MSI2_1, | |
1383 | /* SEL_RAD [1] */ | |
1384 | FN_SEL_RAD_0, FN_SEL_RAD_1, | |
1385 | /* SEL_RCN [1] */ | |
1386 | FN_SEL_RCN_0, FN_SEL_RCN_1, | |
1387 | /* SEL_RSP [1] */ | |
1388 | FN_SEL_RSP_0, FN_SEL_RSP_1, | |
1389 | /* SEL_SCIFA0 [2] */ | |
1390 | FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, | |
1391 | FN_SEL_SCIFA0_3, | |
1392 | /* SEL_SCIFA1 [2] */ | |
1393 | FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0, | |
1394 | /* SEL_SCIFA2 [1] */ | |
1395 | FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, | |
1396 | /* SEL_SCIFA3 [1] */ | |
1397 | FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, | |
1398 | /* SEL_SCIFA4 [2] */ | |
1399 | FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, | |
1400 | FN_SEL_SCIFA4_3, | |
1401 | /* SEL_SCIFA5 [2] */ | |
1402 | FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, | |
1403 | FN_SEL_SCIFA5_3, | |
1404 | /* SEL_SPDM [1] */ | |
1405 | FN_SEL_SPDM_0, FN_SEL_SPDM_1, | |
1406 | /* SEL_TMU [1] */ | |
1407 | FN_SEL_TMU_0, FN_SEL_TMU_1, | |
1408 | /* SEL_TSIF0 [2] */ | |
1409 | FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, | |
1410 | /* SEL_CAN0 [2] */ | |
1411 | FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3, | |
1412 | /* SEL_CAN1 [2] */ | |
1413 | FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3, | |
1414 | /* SEL_HSCIF0 [1] */ | |
1415 | FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, | |
1416 | /* SEL_HSCIF1 [1] */ | |
1417 | FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, | |
1418 | /* SEL_RDS [2] */ | |
1419 | FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, } | |
1420 | }, | |
1421 | { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32, | |
1422 | 2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1, | |
1423 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { | |
1424 | /* SEL_SCIF0 [2] */ | |
1425 | FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3, | |
1426 | /* SEL_SCIF1 [2] */ | |
1427 | FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0, | |
1428 | /* SEL_SCIF2 [2] */ | |
1429 | FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0, | |
1430 | /* SEL_SCIF3 [1] */ | |
1431 | FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, | |
1432 | /* SEL_SCIF4 [3] */ | |
1433 | FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, | |
1434 | FN_SEL_SCIF4_4, 0, 0, 0, | |
1435 | /* SEL_SCIF5 [2] */ | |
1436 | FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, | |
1437 | /* SEL_SSI1 [1] */ | |
1438 | FN_SEL_SSI1_0, FN_SEL_SSI1_1, | |
1439 | /* SEL_SSI2 [1] */ | |
1440 | FN_SEL_SSI2_0, FN_SEL_SSI2_1, | |
1441 | /* SEL_SSI4 [1] */ | |
1442 | FN_SEL_SSI4_0, FN_SEL_SSI4_1, | |
1443 | /* SEL_SSI5 [1] */ | |
1444 | FN_SEL_SSI5_0, FN_SEL_SSI5_1, | |
1445 | /* SEL_SSI6 [1] */ | |
1446 | FN_SEL_SSI6_0, FN_SEL_SSI6_1, | |
1447 | /* SEL_SSI7 [1] */ | |
1448 | FN_SEL_SSI7_0, FN_SEL_SSI7_1, | |
1449 | /* SEL_SSI8 [1] */ | |
1450 | FN_SEL_SSI8_0, FN_SEL_SSI8_1, | |
1451 | /* SEL_SSI9 [1] */ | |
1452 | FN_SEL_SSI9_0, FN_SEL_SSI9_1, | |
1453 | /* RESEVED [1] */ | |
1454 | 0, 0, | |
1455 | /* RESEVED [1] */ | |
1456 | 0, 0, | |
1457 | /* RESEVED [1] */ | |
1458 | 0, 0, | |
1459 | /* RESEVED [1] */ | |
1460 | 0, 0, | |
1461 | /* RESEVED [1] */ | |
1462 | 0, 0, | |
1463 | /* RESEVED [1] */ | |
1464 | 0, 0, | |
1465 | /* RESEVED [1] */ | |
1466 | 0, 0, | |
1467 | /* RESEVED [1] */ | |
1468 | 0, 0, | |
1469 | /* RESEVED [1] */ | |
1470 | 0, 0, | |
1471 | /* RESEVED [1] */ | |
1472 | 0, 0, | |
1473 | /* RESEVED [1] */ | |
1474 | 0, 0, | |
1475 | /* RESEVED [1] */ | |
1476 | 0, 0, } | |
1477 | }, | |
1478 | { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } }, | |
1479 | { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { | |
1480 | 0, 0, | |
1481 | 0, 0, | |
1482 | 0, 0, | |
1483 | 0, 0, | |
1484 | 0, 0, | |
1485 | 0, 0, | |
1486 | GP_1_25_IN, GP_1_25_OUT, | |
1487 | GP_1_24_IN, GP_1_24_OUT, | |
1488 | GP_1_23_IN, GP_1_23_OUT, | |
1489 | GP_1_22_IN, GP_1_22_OUT, | |
1490 | GP_1_21_IN, GP_1_21_OUT, | |
1491 | GP_1_20_IN, GP_1_20_OUT, | |
1492 | GP_1_19_IN, GP_1_19_OUT, | |
1493 | GP_1_18_IN, GP_1_18_OUT, | |
1494 | GP_1_17_IN, GP_1_17_OUT, | |
1495 | GP_1_16_IN, GP_1_16_OUT, | |
1496 | GP_1_15_IN, GP_1_15_OUT, | |
1497 | GP_1_14_IN, GP_1_14_OUT, | |
1498 | GP_1_13_IN, GP_1_13_OUT, | |
1499 | GP_1_12_IN, GP_1_12_OUT, | |
1500 | GP_1_11_IN, GP_1_11_OUT, | |
1501 | GP_1_10_IN, GP_1_10_OUT, | |
1502 | GP_1_9_IN, GP_1_9_OUT, | |
1503 | GP_1_8_IN, GP_1_8_OUT, | |
1504 | GP_1_7_IN, GP_1_7_OUT, | |
1505 | GP_1_6_IN, GP_1_6_OUT, | |
1506 | GP_1_5_IN, GP_1_5_OUT, | |
1507 | GP_1_4_IN, GP_1_4_OUT, | |
1508 | GP_1_3_IN, GP_1_3_OUT, | |
1509 | GP_1_2_IN, GP_1_2_OUT, | |
1510 | GP_1_1_IN, GP_1_1_OUT, | |
1511 | GP_1_0_IN, GP_1_0_OUT, } | |
1512 | }, | |
1513 | { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } }, | |
1514 | { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } }, | |
1515 | { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } }, | |
1516 | { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { | |
1517 | 0, 0, | |
1518 | 0, 0, | |
1519 | 0, 0, | |
1520 | 0, 0, | |
1521 | GP_5_27_IN, GP_5_27_OUT, | |
1522 | GP_5_26_IN, GP_5_26_OUT, | |
1523 | GP_5_25_IN, GP_5_25_OUT, | |
1524 | GP_5_24_IN, GP_5_24_OUT, | |
1525 | GP_5_23_IN, GP_5_23_OUT, | |
1526 | GP_5_22_IN, GP_5_22_OUT, | |
1527 | GP_5_21_IN, GP_5_21_OUT, | |
1528 | GP_5_20_IN, GP_5_20_OUT, | |
1529 | GP_5_19_IN, GP_5_19_OUT, | |
1530 | GP_5_18_IN, GP_5_18_OUT, | |
1531 | GP_5_17_IN, GP_5_17_OUT, | |
1532 | GP_5_16_IN, GP_5_16_OUT, | |
1533 | GP_5_15_IN, GP_5_15_OUT, | |
1534 | GP_5_14_IN, GP_5_14_OUT, | |
1535 | GP_5_13_IN, GP_5_13_OUT, | |
1536 | GP_5_12_IN, GP_5_12_OUT, | |
1537 | GP_5_11_IN, GP_5_11_OUT, | |
1538 | GP_5_10_IN, GP_5_10_OUT, | |
1539 | GP_5_9_IN, GP_5_9_OUT, | |
1540 | GP_5_8_IN, GP_5_8_OUT, | |
1541 | GP_5_7_IN, GP_5_7_OUT, | |
1542 | GP_5_6_IN, GP_5_6_OUT, | |
1543 | GP_5_5_IN, GP_5_5_OUT, | |
1544 | GP_5_4_IN, GP_5_4_OUT, | |
1545 | GP_5_3_IN, GP_5_3_OUT, | |
1546 | GP_5_2_IN, GP_5_2_OUT, | |
1547 | GP_5_1_IN, GP_5_1_OUT, | |
1548 | GP_5_0_IN, GP_5_0_OUT, } | |
1549 | }, | |
1550 | { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { | |
1551 | 0, 0, | |
1552 | 0, 0, | |
1553 | 0, 0, | |
1554 | 0, 0, | |
1555 | 0, 0, | |
1556 | 0, 0, | |
1557 | GP_6_25_IN, GP_6_25_OUT, | |
1558 | GP_6_24_IN, GP_6_24_OUT, | |
1559 | GP_6_23_IN, GP_6_23_OUT, | |
1560 | GP_6_22_IN, GP_6_22_OUT, | |
1561 | GP_6_21_IN, GP_6_21_OUT, | |
1562 | GP_6_20_IN, GP_6_20_OUT, | |
1563 | GP_6_19_IN, GP_6_19_OUT, | |
1564 | GP_6_18_IN, GP_6_18_OUT, | |
1565 | GP_6_17_IN, GP_6_17_OUT, | |
1566 | GP_6_16_IN, GP_6_16_OUT, | |
1567 | GP_6_15_IN, GP_6_15_OUT, | |
1568 | GP_6_14_IN, GP_6_14_OUT, | |
1569 | GP_6_13_IN, GP_6_13_OUT, | |
1570 | GP_6_12_IN, GP_6_12_OUT, | |
1571 | GP_6_11_IN, GP_6_11_OUT, | |
1572 | GP_6_10_IN, GP_6_10_OUT, | |
1573 | GP_6_9_IN, GP_6_9_OUT, | |
1574 | GP_6_8_IN, GP_6_8_OUT, | |
1575 | GP_6_7_IN, GP_6_7_OUT, | |
1576 | GP_6_6_IN, GP_6_6_OUT, | |
1577 | GP_6_5_IN, GP_6_5_OUT, | |
1578 | GP_6_4_IN, GP_6_4_OUT, | |
1579 | GP_6_3_IN, GP_6_3_OUT, | |
1580 | GP_6_2_IN, GP_6_2_OUT, | |
1581 | GP_6_1_IN, GP_6_1_OUT, | |
1582 | GP_6_0_IN, GP_6_0_OUT, } | |
1583 | }, | |
1584 | { }, | |
1585 | }; | |
1586 | ||
1587 | static struct pinmux_data_reg pinmux_data_regs[] = { | |
1588 | { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } }, | |
1589 | { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { | |
1590 | 0, 0, 0, 0, | |
1591 | 0, 0, GP_1_25_DATA, GP_1_24_DATA, | |
1592 | GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, | |
1593 | GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, | |
1594 | GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, | |
1595 | GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, | |
1596 | GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, | |
1597 | GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } | |
1598 | }, | |
1599 | { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } }, | |
1600 | { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } }, | |
1601 | { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } }, | |
1602 | { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { | |
1603 | 0, 0, 0, 0, | |
1604 | GP_5_27_DATA, GP_5_26_DATA, GP_5_25_DATA, GP_5_24_DATA, | |
1605 | GP_5_23_DATA, GP_5_22_DATA, GP_5_21_DATA, GP_5_20_DATA, | |
1606 | GP_5_19_DATA, GP_5_18_DATA, GP_5_17_DATA, GP_5_16_DATA, | |
1607 | GP_5_15_DATA, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, | |
1608 | GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, | |
1609 | GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, | |
1610 | GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } | |
1611 | }, | |
1612 | { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { | |
1613 | 0, 0, 0, 0, | |
1614 | 0, 0, GP_6_25_DATA, GP_6_24_DATA, | |
1615 | GP_6_23_DATA, GP_6_22_DATA, GP_6_21_DATA, GP_6_20_DATA, | |
1616 | GP_6_19_DATA, GP_6_18_DATA, GP_6_17_DATA, GP_6_16_DATA, | |
1617 | GP_6_15_DATA, GP_6_14_DATA, GP_6_13_DATA, GP_6_12_DATA, | |
1618 | GP_6_11_DATA, GP_6_10_DATA, GP_6_9_DATA, GP_6_8_DATA, | |
1619 | GP_6_7_DATA, GP_6_6_DATA, GP_6_5_DATA, GP_6_4_DATA, | |
1620 | GP_6_3_DATA, GP_6_2_DATA, GP_6_1_DATA, GP_6_0_DATA } | |
1621 | }, | |
1622 | { }, | |
1623 | }; | |
1624 | ||
1625 | static struct pinmux_info r8a7794_pinmux_info = { | |
1626 | .name = "r8a7794_pfc", | |
1627 | ||
1628 | .unlock_reg = 0xe6060000, /* PMMR */ | |
1629 | ||
1630 | .reserved_id = PINMUX_RESERVED, | |
1631 | .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, | |
1632 | .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, | |
1633 | .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, | |
1634 | .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, | |
1635 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, | |
1636 | ||
1637 | .first_gpio = GPIO_GP_0_0, | |
1638 | .last_gpio = GPIO_FN_AD_CLK_B, | |
1639 | ||
1640 | .gpios = pinmux_gpios, | |
1641 | .cfg_regs = pinmux_config_regs, | |
1642 | .data_regs = pinmux_data_regs, | |
1643 | ||
1644 | .gpio_data = pinmux_data, | |
1645 | .gpio_data_size = ARRAY_SIZE(pinmux_data), | |
1646 | }; | |
1647 | ||
1648 | void r8a7794_pinmux_init(void) | |
1649 | { | |
1650 | register_pinmux(&r8a7794_pinmux_info); | |
1651 | } |