[thirdparty/kernel/stable.git] / arch / arm / mach-rockchip / platsmp.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright (c) 2013 MundoReader S.L.
 * Author: Heiko Stuebner <heiko@sntech.de>
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/smp.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/regmap.h>
#include <linux/mfd/syscon.h>

#include <linux/reset.h>
#include <linux/cpu.h>
#include <asm/cacheflush.h>
#include <asm/cp15.h>
#include <asm/smp_scu.h>
#include <asm/smp_plat.h>
#include <asm/mach/map.h>

#include "core.h"

static void __iomem *scu_base_addr;
static void __iomem *sram_base_addr;
static int ncores;

#define PMU_PWRDN_CON		0x08
#define PMU_PWRDN_ST		0x0c

#define PMU_PWRDN_SCU		4

static struct regmap *pmu;
static int has_pmu = true;

static int pmu_power_domain_is_on(int pd)
{
	u32 val;
	int ret;

	ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
	if (ret < 0)
		return ret;

	return !(val & BIT(pd));
}

static struct reset_control *rockchip_get_core_reset(int cpu)
{
	struct device *dev = get_cpu_device(cpu);
	struct device_node *np;

	/* The cpu device is only available after the initial core bringup */
	if (dev)
		np = dev->of_node;
	else
		np = of_get_cpu_node(cpu, NULL);

	return of_reset_control_get_exclusive(np, NULL);
}

static int pmu_set_power_domain(int pd, bool on)
{
	u32 val = (on) ? 0 : BIT(pd);
	struct reset_control *rstc = rockchip_get_core_reset(pd);
	int ret;

	if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
		pr_err("%s: could not get reset control for core %d\n",
		       __func__, pd);
		return PTR_ERR(rstc);
	}

	/*
	 * We need to soft reset the cpu when we turn off the cpu power domain,
	 * or else the active processors might be stalled when the individual
	 * processor is powered down.
	 */
	if (!IS_ERR(rstc) && !on)
		reset_control_assert(rstc);

	if (has_pmu) {
		ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
		if (ret < 0) {
			pr_err("%s: could not update power domain\n",
			       __func__);
			return ret;
		}

		ret = -1;
		while (ret != on) {
			ret = pmu_power_domain_is_on(pd);
			if (ret < 0) {
				pr_err("%s: could not read power domain state\n",
				       __func__);
				return ret;
			}
		}
	}

	if (!IS_ERR(rstc)) {
		if (on)
			reset_control_deassert(rstc);
		reset_control_put(rstc);
	}

	return 0;
}

/*
 * Handling of CPU cores
 */

static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
	int ret;

	if (!sram_base_addr || (has_pmu && !pmu)) {
		pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
		return -ENXIO;
	}

	if (cpu >= ncores) {
		pr_err("%s: cpu %d outside maximum number of cpus %d\n",
		       __func__, cpu, ncores);
		return -ENXIO;
	}

	/* start the core */
	ret = pmu_set_power_domain(0 + cpu, true);
	if (ret < 0)
		return ret;

	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
		/*
		 * We communicate with the bootrom to active the cpus other
		 * than cpu0, after a blob of initialize code, they will
		 * stay at wfe state, once they are actived, they will check
		 * the mailbox:
		 * sram_base_addr + 4: 0xdeadbeaf
		 * sram_base_addr + 8: start address for pc
		 * The cpu0 need to wait the other cpus other than cpu0 entering
		 * the wfe state.The wait time is affected by many aspects.
		 * (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
		 */
		mdelay(1); /* ensure the cpus other than cpu0 to startup */

		writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
		writel(0xDEADBEAF, sram_base_addr + 4);
		dsb_sev();
	}

	return 0;
}

/**
 * rockchip_smp_prepare_sram - populate necessary sram block
 * Starting cores execute the code residing at the start of the on-chip sram
 * after power-on. Therefore make sure, this sram region is reserved and
 * big enough. After this check, copy the trampoline code that directs the
 * core to the real startup code in ram into the sram-region.
 * @node: mmio-sram device node
 */
static int __init rockchip_smp_prepare_sram(struct device_node *node)
{
	unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
					    &rockchip_secondary_trampoline;
	struct resource res;
	unsigned int rsize;
	int ret;

	ret = of_address_to_resource(node, 0, &res);
	if (ret < 0) {
		pr_err("%s: could not get address for node %pOF\n",
		       __func__, node);
		return ret;
	}

	rsize = resource_size(&res);
	if (rsize < trampoline_sz) {
		pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
		       __func__, rsize, trampoline_sz);
		return -EINVAL;
	}

	/* set the boot function for the sram code */
	rockchip_boot_fn = __pa_symbol(secondary_startup);

	/* copy the trampoline to sram, that runs during startup of the core */
	memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
	flush_cache_all();
	outer_clean_range(0, trampoline_sz);

	dsb_sev();

	return 0;
}

static const struct regmap_config rockchip_pmu_regmap_config = {
	.name = "rockchip-pmu",
	.reg_bits = 32,
	.val_bits = 32,
	.reg_stride = 4,
};

static int __init rockchip_smp_prepare_pmu(void)
{
	struct device_node *node;
	void __iomem *pmu_base;

	/*
	 * This function is only called via smp_ops->smp_prepare_cpu().
	 * That only happens if a "/cpus" device tree node exists
	 * and has an "enable-method" property that selects the SMP
	 * operations defined herein.
	 */
	node = of_find_node_by_path("/cpus");

	pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
	of_node_put(node);
	if (!IS_ERR(pmu))
		return 0;

	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
	if (!IS_ERR(pmu))
		return 0;

	/* fallback, create our own regmap for the pmu area */
	pmu = NULL;
	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
	if (!node) {
		pr_err("%s: could not find pmu dt node\n", __func__);
		return -ENODEV;
	}

	pmu_base = of_iomap(node, 0);
	of_node_put(node);
	if (!pmu_base) {
		pr_err("%s: could not map pmu registers\n", __func__);
		return -ENOMEM;
	}

	pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
	if (IS_ERR(pmu)) {
		int ret = PTR_ERR(pmu);

		iounmap(pmu_base);
		pmu = NULL;
		pr_err("%s: regmap init failed\n", __func__);
		return ret;
	}

	return 0;
}

static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
{
	struct device_node *node;
	unsigned int i;

	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
	if (!node) {
		pr_err("%s: could not find sram dt node\n", __func__);
		return;
	}

	sram_base_addr = of_iomap(node, 0);
	if (!sram_base_addr) {
		pr_err("%s: could not map sram registers\n", __func__);
		return;
	}

	if (has_pmu && rockchip_smp_prepare_pmu())
		return;

	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
		if (rockchip_smp_prepare_sram(node))
			return;

		/* enable the SCU power domain */
		pmu_set_power_domain(PMU_PWRDN_SCU, true);

		node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
		if (!node) {
			pr_err("%s: missing scu\n", __func__);
			return;
		}

		scu_base_addr = of_iomap(node, 0);
		if (!scu_base_addr) {
			pr_err("%s: could not map scu registers\n", __func__);
			return;
		}

		/*
		 * While the number of cpus is gathered from dt, also get the
		 * number of cores from the scu to verify this value when
		 * booting the cores.
		 */
		ncores = scu_get_core_count(scu_base_addr);
		pr_err("%s: ncores %d\n", __func__, ncores);

		scu_enable(scu_base_addr);
	} else {
		unsigned int l2ctlr;

		asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
		ncores = ((l2ctlr >> 24) & 0x3) + 1;
	}

	/* Make sure that all cores except the first are really off */
	for (i = 1; i < ncores; i++)
		pmu_set_power_domain(0 + i, false);
}

static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
{
	has_pmu = false;

	rockchip_smp_prepare_cpus(max_cpus);
}

#ifdef CONFIG_HOTPLUG_CPU
static int rockchip_cpu_kill(unsigned int cpu)
{
	/*
	 * We need a delay here to ensure that the dying CPU can finish
	 * executing v7_coherency_exit() and reach the WFI/WFE state
	 * prior to having the power domain disabled.
	 */
	mdelay(1);

	pmu_set_power_domain(0 + cpu, false);
	return 1;
}

static void rockchip_cpu_die(unsigned int cpu)
{
	v7_exit_coherency_flush(louis);
	while (1)
		cpu_do_idle();
}
#endif

static const struct smp_operations rk3036_smp_ops __initconst = {
	.smp_prepare_cpus	= rk3036_smp_prepare_cpus,
	.smp_boot_secondary	= rockchip_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_kill		= rockchip_cpu_kill,
	.cpu_die		= rockchip_cpu_die,
#endif
};

static const struct smp_operations rockchip_smp_ops __initconst = {
	.smp_prepare_cpus	= rockchip_smp_prepare_cpus,
	.smp_boot_secondary	= rockchip_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
	.cpu_kill		= rockchip_cpu_kill,
	.cpu_die		= rockchip_cpu_die,
#endif
};

CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);
Commit	Line	Data
c942fddf	1	// SPDX-License-Identifier: GPL-2.0-or-later
a7a2b311 HS	2	/*
	3	* Copyright (c) 2013 MundoReader S.L.
	4	* Author: Heiko Stuebner <heiko@sntech.de>
a7a2b311 HS	5	*/
	6
	7	#include <linux/delay.h>
	8	#include <linux/init.h>
	9	#include <linux/smp.h>
	10	#include <linux/io.h>
	11	#include <linux/of.h>
	12	#include <linux/of_address.h>
d003b58c HS	13	#include <linux/regmap.h>
d003b58c HS	14	#include <linux/mfd/syscon.h>
a7a2b311	15
3ee851e2 KY	16	#include <linux/reset.h>
3ee851e2 KY	17	#include <linux/cpu.h>
a7a2b311	18	#include <asm/cacheflush.h>
f54b91fd	19	#include <asm/cp15.h>
a7a2b311 HS	20	#include <asm/smp_scu.h>
	21	#include <asm/smp_plat.h>
	22	#include <asm/mach/map.h>
	23
	24	#include "core.h"
	25
	26	static void __iomem *scu_base_addr;
	27	static void __iomem *sram_base_addr;
	28	static int ncores;
	29
	30	#define PMU_PWRDN_CON 0x08
	31	#define PMU_PWRDN_ST 0x0c
	32
	33	#define PMU_PWRDN_SCU 4
	34
d003b58c	35	static struct regmap *pmu;
9def7ccf	36	static int has_pmu = true;
a7a2b311	37
d003b58c	38	static int pmu_power_domain_is_on(int pd)
a7a2b311	39	{
d003b58c HS	40	u32 val;
	41	int ret;
	42
	43	ret = regmap_read(pmu, PMU_PWRDN_ST, &val);
	44	if (ret < 0)
	45	return ret;
	46
	47	return !(val & BIT(pd));
a7a2b311 HS	48	}
a7a2b311 HS	49
bd76d738	50	static struct reset_control *rockchip_get_core_reset(int cpu)
3ee851e2 KY	51	{
	52	struct device *dev = get_cpu_device(cpu);
	53	struct device_node *np;
	54
	55	/* The cpu device is only available after the initial core bringup */
	56	if (dev)
	57	np = dev->of_node;
	58	else
26d51929	59	np = of_get_cpu_node(cpu, NULL);
3ee851e2	60
da45adf9	61	return of_reset_control_get_exclusive(np, NULL);
3ee851e2 KY	62	}
3ee851e2 KY	63
d003b58c	64	static int pmu_set_power_domain(int pd, bool on)
a7a2b311	65	{
d003b58c	66	u32 val = (on) ? 0 : BIT(pd);
fe4407c0	67	struct reset_control *rstc = rockchip_get_core_reset(pd);
d003b58c HS	68	int ret;
d003b58c HS	69
fe4407c0 CW	70	if (IS_ERR(rstc) && read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
	71	pr_err("%s: could not get reset control for core %d\n",
	72	__func__, pd);
	73	return PTR_ERR(rstc);
	74	}
	75
3ee851e2 KY	76	/*
	77	* We need to soft reset the cpu when we turn off the cpu power domain,
	78	* or else the active processors might be stalled when the individual
	79	* processor is powered down.
	80	*/
fe4407c0 CW	81	if (!IS_ERR(rstc) && !on)
fe4407c0 CW	82	reset_control_assert(rstc);
3ee851e2	83
9def7ccf HS	84	if (has_pmu) {
9def7ccf HS	85	ret = regmap_update_bits(pmu, PMU_PWRDN_CON, BIT(pd), val);
d003b58c	86	if (ret < 0) {
9def7ccf	87	pr_err("%s: could not update power domain\n",
7f0b61ad	88	__func__);
d003b58c HS	89	return ret;
d003b58c HS	90	}
9def7ccf HS	91
	92	ret = -1;
	93	while (ret != on) {
	94	ret = pmu_power_domain_is_on(pd);
	95	if (ret < 0) {
	96	pr_err("%s: could not read power domain state\n",
	97	__func__);
	98	return ret;
	99	}
	100	}
d003b58c HS	101	}
d003b58c HS	102
fe4407c0 CW	103	if (!IS_ERR(rstc)) {
	104	if (on)
	105	reset_control_deassert(rstc);
	106	reset_control_put(rstc);
	107	}
	108
d003b58c	109	return 0;
a7a2b311 HS	110	}
	111
	112	/*
	113	* Handling of CPU cores
	114	*/
	115
374d4dd3	116	static int rockchip_boot_secondary(unsigned int cpu, struct task_struct *idle)
a7a2b311	117	{
3ee851e2 KY	118	int ret;
3ee851e2 KY	119
9def7ccf	120	if (!sram_base_addr \|\| (has_pmu && !pmu)) {
a7a2b311 HS	121	pr_err("%s: sram or pmu missing for cpu boot\n", __func__);
	122	return -ENXIO;
	123	}
	124
	125	if (cpu >= ncores) {
	126	pr_err("%s: cpu %d outside maximum number of cpus %d\n",
7f0b61ad	127	__func__, cpu, ncores);
a7a2b311 HS	128	return -ENXIO;
	129	}
	130
	131	/* start the core */
3ee851e2 KY	132	ret = pmu_set_power_domain(0 + cpu, true);
	133	if (ret < 0)
	134	return ret;
	135
	136	if (read_cpuid_part() != ARM_CPU_PART_CORTEX_A9) {
7f0b61ad CW	137	/*
7f0b61ad CW	138	* We communicate with the bootrom to active the cpus other
3ee851e2 KY	139	* than cpu0, after a blob of initialize code, they will
	140	* stay at wfe state, once they are actived, they will check
	141	* the mailbox:
	142	* sram_base_addr + 4: 0xdeadbeaf
	143	* sram_base_addr + 8: start address for pc
fe4407c0 CW	144	* The cpu0 need to wait the other cpus other than cpu0 entering
	145	* the wfe state.The wait time is affected by many aspects.
	146	* (e.g: cpu frequency, bootrom frequency, sram frequency, ...)
7f0b61ad	147	*/
fe4407c0 CW	148	mdelay(1); /* ensure the cpus other than cpu0 to startup */
fe4407c0 CW	149
64fc2a94	150	writel(__pa_symbol(secondary_startup), sram_base_addr + 8);
3ee851e2 KY	151	writel(0xDEADBEAF, sram_base_addr + 4);
	152	dsb_sev();
	153	}
	154
	155	return 0;
a7a2b311 HS	156	}
	157
	158	/**
	159	* rockchip_smp_prepare_sram - populate necessary sram block
	160	* Starting cores execute the code residing at the start of the on-chip sram
	161	* after power-on. Therefore make sure, this sram region is reserved and
	162	* big enough. After this check, copy the trampoline code that directs the
	163	* core to the real startup code in ram into the sram-region.
	164	* @node: mmio-sram device node
	165	*/
	166	static int __init rockchip_smp_prepare_sram(struct device_node *node)
	167	{
	168	unsigned int trampoline_sz = &rockchip_secondary_trampoline_end -
	169	&rockchip_secondary_trampoline;
	170	struct resource res;
	171	unsigned int rsize;
	172	int ret;
	173
	174	ret = of_address_to_resource(node, 0, &res);
	175	if (ret < 0) {
a8e65e06 RH	176	pr_err("%s: could not get address for node %pOF\n",
a8e65e06 RH	177	__func__, node);
a7a2b311 HS	178	return ret;
	179	}
	180
	181	rsize = resource_size(&res);
	182	if (rsize < trampoline_sz) {
	183	pr_err("%s: reserved block with size 0x%x is to small for trampoline size 0x%x\n",
	184	__func__, rsize, trampoline_sz);
	185	return -EINVAL;
	186	}
	187
a7a2b311	188	/* set the boot function for the sram code */
64fc2a94	189	rockchip_boot_fn = __pa_symbol(secondary_startup);
a7a2b311 HS	190
	191	/* copy the trampoline to sram, that runs during startup of the core */
	192	memcpy(sram_base_addr, &rockchip_secondary_trampoline, trampoline_sz);
	193	flush_cache_all();
	194	outer_clean_range(0, trampoline_sz);
	195
	196	dsb_sev();
	197
	198	return 0;
	199	}
	200
bd76d738	201	static const struct regmap_config rockchip_pmu_regmap_config = {
03151b89	202	.name = "rockchip-pmu",
d003b58c HS	203	.reg_bits = 32,
	204	.val_bits = 32,
	205	.reg_stride = 4,
	206	};
	207
	208	static int __init rockchip_smp_prepare_pmu(void)
	209	{
	210	struct device_node *node;
	211	void __iomem *pmu_base;
	212
6de2d21a HS	213	/*
	214	* This function is only called via smp_ops->smp_prepare_cpu().
	215	* That only happens if a "/cpus" device tree node exists
	216	* and has an "enable-method" property that selects the SMP
	217	* operations defined herein.
	218	*/
	219	node = of_find_node_by_path("/cpus");
	220
	221	pmu = syscon_regmap_lookup_by_phandle(node, "rockchip,pmu");
	222	of_node_put(node);
	223	if (!IS_ERR(pmu))
	224	return 0;
	225
d003b58c HS	226	pmu = syscon_regmap_lookup_by_compatible("rockchip,rk3066-pmu");
	227	if (!IS_ERR(pmu))
	228	return 0;
	229
	230	/* fallback, create our own regmap for the pmu area */
	231	pmu = NULL;
	232	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-pmu");
	233	if (!node) {
	234	pr_err("%s: could not find pmu dt node\n", __func__);
	235	return -ENODEV;
	236	}
	237
	238	pmu_base = of_iomap(node, 0);
fbd7af04	239	of_node_put(node);
d003b58c HS	240	if (!pmu_base) {
	241	pr_err("%s: could not map pmu registers\n", __func__);
	242	return -ENOMEM;
	243	}
	244
	245	pmu = regmap_init_mmio(NULL, pmu_base, &rockchip_pmu_regmap_config);
	246	if (IS_ERR(pmu)) {
	247	int ret = PTR_ERR(pmu);
	248
	249	iounmap(pmu_base);
	250	pmu = NULL;
	251	pr_err("%s: regmap init failed\n", __func__);
	252	return ret;
	253	}
	254
	255	return 0;
	256	}
	257
a7a2b311 HS	258	static void __init rockchip_smp_prepare_cpus(unsigned int max_cpus)
	259	{
	260	struct device_node *node;
	261	unsigned int i;
	262
a7a2b311 HS	263	node = of_find_compatible_node(NULL, NULL, "rockchip,rk3066-smp-sram");
	264	if (!node) {
	265	pr_err("%s: could not find sram dt node\n", __func__);
	266	return;
	267	}
	268
3ee851e2 KY	269	sram_base_addr = of_iomap(node, 0);
	270	if (!sram_base_addr) {
	271	pr_err("%s: could not map sram registers\n", __func__);
a7a2b311	272	return;
3ee851e2	273	}
a7a2b311	274
9def7ccf	275	if (has_pmu && rockchip_smp_prepare_pmu())
a7a2b311	276	return;
a7a2b311	277
3ee851e2 KY	278	if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
	279	if (rockchip_smp_prepare_sram(node))
	280	return;
a7a2b311	281
3ee851e2 KY	282	/* enable the SCU power domain */
	283	pmu_set_power_domain(PMU_PWRDN_SCU, true);
	284
	285	node = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
	286	if (!node) {
	287	pr_err("%s: missing scu\n", __func__);
	288	return;
	289	}
a7a2b311	290
3ee851e2 KY	291	scu_base_addr = of_iomap(node, 0);
	292	if (!scu_base_addr) {
	293	pr_err("%s: could not map scu registers\n", __func__);
	294	return;
	295	}
	296
	297	/*
	298	* While the number of cpus is gathered from dt, also get the
	299	* number of cores from the scu to verify this value when
	300	* booting the cores.
	301	*/
	302	ncores = scu_get_core_count(scu_base_addr);
	303	pr_err("%s: ncores %d\n", __func__, ncores);
	304
	305	scu_enable(scu_base_addr);
	306	} else {
	307	unsigned int l2ctlr;
	308
	309	asm ("mrc p15, 1, %0, c9, c0, 2\n" : "=r" (l2ctlr));
	310	ncores = ((l2ctlr >> 24) & 0x3) + 1;
	311	}
a7a2b311 HS	312
	313	/* Make sure that all cores except the first are really off */
	314	for (i = 1; i < ncores; i++)
	315	pmu_set_power_domain(0 + i, false);
	316	}
	317
9def7ccf HS	318	static void __init rk3036_smp_prepare_cpus(unsigned int max_cpus)
	319	{
	320	has_pmu = false;
	321
	322	rockchip_smp_prepare_cpus(max_cpus);
	323	}
	324
f54b91fd RP	325	#ifdef CONFIG_HOTPLUG_CPU
	326	static int rockchip_cpu_kill(unsigned int cpu)
	327	{
e306bc16 CW	328	/*
	329	* We need a delay here to ensure that the dying CPU can finish
	330	* executing v7_coherency_exit() and reach the WFI/WFE state
	331	* prior to having the power domain disabled.
	332	*/
	333	mdelay(1);
	334
f54b91fd RP	335	pmu_set_power_domain(0 + cpu, false);
	336	return 1;
	337	}
	338
	339	static void rockchip_cpu_die(unsigned int cpu)
	340	{
	341	v7_exit_coherency_flush(louis);
7f0b61ad	342	while (1)
f54b91fd RP	343	cpu_do_idle();
	344	}
	345	#endif
	346
26dc88fb	347	static const struct smp_operations rk3036_smp_ops __initconst = {
9def7ccf HS	348	.smp_prepare_cpus = rk3036_smp_prepare_cpus,
	349	.smp_boot_secondary = rockchip_boot_secondary,
	350	#ifdef CONFIG_HOTPLUG_CPU
	351	.cpu_kill = rockchip_cpu_kill,
	352	.cpu_die = rockchip_cpu_die,
	353	#endif
	354	};
	355
75305275	356	static const struct smp_operations rockchip_smp_ops __initconst = {
a7a2b311 HS	357	.smp_prepare_cpus = rockchip_smp_prepare_cpus,
a7a2b311 HS	358	.smp_boot_secondary = rockchip_boot_secondary,
f54b91fd RP	359	#ifdef CONFIG_HOTPLUG_CPU
	360	.cpu_kill = rockchip_cpu_kill,
	361	.cpu_die = rockchip_cpu_die,
	362	#endif
a7a2b311	363	};
7f0b61ad	364
9def7ccf	365	CPU_METHOD_OF_DECLARE(rk3036_smp, "rockchip,rk3036-smp", &rk3036_smp_ops);
26ab69cb	366	CPU_METHOD_OF_DECLARE(rk3066_smp, "rockchip,rk3066-smp", &rockchip_smp_ops);