]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
aa89b554 KY |
2 | /* |
3 | * Copyright (c) 2016 Rockchip Electronics Co., Ltd | |
aa89b554 | 4 | */ |
1e7d2be0 | 5 | #include <common.h> |
25c61730 | 6 | #include <asm/armv7.h> |
aa89b554 | 7 | #include <asm/io.h> |
8af6cafc | 8 | #include <asm/arch-rockchip/bootrom.h> |
15f09a1a | 9 | #include <asm/arch-rockchip/hardware.h> |
070e48b3 | 10 | #include <asm/arch-rockchip/grf_rk3288.h> |
f35c417c | 11 | #include <asm/arch-rockchip/pmu_rk3288.h> |
1e7d2be0 | 12 | #include <asm/arch-rockchip/qos_rk3288.h> |
f35c417c KY |
13 | #include <asm/arch-rockchip/sdram_common.h> |
14 | ||
15 | DECLARE_GLOBAL_DATA_PTR; | |
aa89b554 | 16 | |
070e48b3 | 17 | #define GRF_BASE 0xff770000 |
aa89b554 | 18 | |
8af6cafc KY |
19 | const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { |
20 | [BROM_BOOTSOURCE_EMMC] = "dwmmc@ff0f0000", | |
21 | [BROM_BOOTSOURCE_SD] = "dwmmc@ff0c0000", | |
22 | }; | |
23 | ||
25c61730 KY |
24 | #ifdef CONFIG_SPL_BUILD |
25 | static void configure_l2ctlr(void) | |
26 | { | |
27 | u32 l2ctlr; | |
28 | ||
29 | l2ctlr = read_l2ctlr(); | |
30 | l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ | |
31 | ||
32 | /* | |
33 | * Data RAM write latency: 2 cycles | |
34 | * Data RAM read latency: 2 cycles | |
35 | * Data RAM setup latency: 1 cycle | |
36 | * Tag RAM write latency: 1 cycle | |
37 | * Tag RAM read latency: 1 cycle | |
38 | * Tag RAM setup latency: 1 cycle | |
39 | */ | |
40 | l2ctlr |= (1 << 3 | 1 << 0); | |
41 | write_l2ctlr(l2ctlr); | |
42 | } | |
43 | #endif | |
44 | ||
1e7d2be0 KY |
45 | int rk3288_qos_init(void) |
46 | { | |
47 | int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT; | |
48 | /* set vop qos to higher priority */ | |
49 | writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS); | |
50 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS); | |
51 | ||
52 | if (!fdt_node_check_compatible(gd->fdt_blob, 0, | |
53 | "rockchip,rk3288-tinker")) { | |
54 | /* set isp qos to higher priority */ | |
55 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS); | |
56 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS); | |
57 | writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS); | |
58 | } | |
59 | ||
60 | return 0; | |
61 | } | |
62 | ||
aa89b554 KY |
63 | int arch_cpu_init(void) |
64 | { | |
ccab9e7e KY |
65 | #ifdef CONFIG_SPL_BUILD |
66 | configure_l2ctlr(); | |
67 | #else | |
aa89b554 | 68 | /* We do some SoC one time setting here. */ |
070e48b3 | 69 | struct rk3288_grf * const grf = (void *)GRF_BASE; |
aa89b554 KY |
70 | |
71 | /* Use rkpwm by default */ | |
070e48b3 | 72 | rk_setreg(&grf->soc_con2, 1 << 0); |
1e7d2be0 KY |
73 | |
74 | /* | |
75 | * Disable JTAG on sdmmc0 IO. The SDMMC won't work until this bit is | |
76 | * cleared | |
77 | */ | |
78 | rk_clrreg(&grf->soc_con0, 1 << 12); | |
79 | ||
80 | rk3288_qos_init(); | |
ccab9e7e | 81 | #endif |
aa89b554 KY |
82 | |
83 | return 0; | |
84 | } | |
e83e885e KY |
85 | |
86 | #ifdef CONFIG_DEBUG_UART_BOARD_INIT | |
87 | void board_debug_uart_init(void) | |
88 | { | |
89 | /* Enable early UART on the RK3288 */ | |
90 | struct rk3288_grf * const grf = (void *)GRF_BASE; | |
91 | ||
92 | rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | | |
93 | GPIO7C6_MASK << GPIO7C6_SHIFT, | |
94 | GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | | |
95 | GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); | |
96 | } | |
97 | #endif |