[thirdparty/linux.git] / arch / arm / mach-s3c24xx / mach-osiris.c

/* linux/arch/arm/mach-s3c2440/mach-osiris.c
 *
 * Copyright (c) 2005-2008 Simtec Electronics
 *	http://armlinux.simtec.co.uk/
 *	Ben Dooks <ben@simtec.co.uk>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
*/

#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/timer.h>
#include <linux/init.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/syscore_ops.h>
#include <linux/serial_core.h>
#include <linux/clk.h>
#include <linux/i2c.h>
#include <linux/io.h>

#include <linux/i2c/tps65010.h>

#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>

#include <mach/osiris-map.h>
#include <mach/osiris-cpld.h>

#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/mach-types.h>

#include <plat/cpu-freq.h>
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-mem.h>
#include <mach/regs-lcd.h>
#include <linux/platform_data/mtd-nand-s3c2410.h>
#include <linux/platform_data/i2c-s3c2410.h>

#include <linux/mtd/mtd.h>
#include <linux/mtd/nand.h>
#include <linux/mtd/nand_ecc.h>
#include <linux/mtd/partitions.h>

#include <plat/gpio-cfg.h>
#include <plat/clock.h>
#include <plat/devs.h>
#include <plat/cpu.h>

#include "common.h"

/* onboard perihperal map */

static struct map_desc osiris_iodesc[] __initdata = {
  /* ISA IO areas (may be over-written later) */

  {
	  .virtual	= (u32)S3C24XX_VA_ISA_BYTE,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)S3C24XX_VA_ISA_WORD,
	  .pfn		= __phys_to_pfn(S3C2410_CS5),
	  .length	= SZ_16M,
	  .type		= MT_DEVICE,
  },

  /* CPLD control registers */

  {
	  .virtual	= (u32)OSIRIS_VA_CTRL0,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL0),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL1,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL1),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_CTRL2,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_CTRL2),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  }, {
	  .virtual	= (u32)OSIRIS_VA_IDREG,
	  .pfn		= __phys_to_pfn(OSIRIS_PA_IDREG),
	  .length	= SZ_16K,
	  .type		= MT_DEVICE,
  },
};

#define UCON S3C2410_UCON_DEFAULT | S3C2410_UCON_UCLK
#define ULCON S3C2410_LCON_CS8 | S3C2410_LCON_PNONE | S3C2410_LCON_STOPB
#define UFCON S3C2410_UFCON_RXTRIG8 | S3C2410_UFCON_FIFOMODE

static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
	[0] = {
		.hwport	     = 0,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
	[1] = {
		.hwport	     = 1,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	},
	[2] = {
		.hwport	     = 2,
		.flags	     = 0,
		.ucon	     = UCON,
		.ulcon	     = ULCON,
		.ufcon	     = UFCON,
		.clk_sel	= S3C2410_UCON_CLKSEL1 | S3C2410_UCON_CLKSEL2,
	}
};

/* NAND Flash on Osiris board */

static int external_map[]   = { 2 };
static int chip0_map[]      = { 0 };
static int chip1_map[]      = { 1 };

static struct mtd_partition __initdata osiris_default_nand_part[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_16K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_16K,
		.offset	= SZ_16K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
	[0] = {
		.name	= "Boot Agent",
		.size	= SZ_128K,
		.offset	= 0,
	},
	[1] = {
		.name	= "/boot",
		.size	= SZ_4M - SZ_128K,
		.offset	= SZ_128K,
	},
	[2] = {
		.name	= "user1",
		.offset	= SZ_4M,
		.size	= SZ_32M - SZ_4M,
	},
	[3] = {
		.name	= "user2",
		.offset	= SZ_32M,
		.size	= MTDPART_SIZ_FULL,
	}
};

/* the Osiris has 3 selectable slots for nand-flash, the two
 * on-board chip areas, as well as the external slot.
 *
 * Note, there is no current hot-plug support for the External
 * socket.
*/

static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
	[1] = {
		.name		= "External",
		.nr_chips	= 1,
		.nr_map		= external_map,
		.options	= NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[0] = {
		.name		= "chip0",
		.nr_chips	= 1,
		.nr_map		= chip0_map,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
	[2] = {
		.name		= "chip1",
		.nr_chips	= 1,
		.nr_map		= chip1_map,
		.options	= NAND_SCAN_SILENT_NODEV,
		.nr_partitions	= ARRAY_SIZE(osiris_default_nand_part),
		.partitions	= osiris_default_nand_part,
	},
};

static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
{
	unsigned int tmp;

	slot = set->nr_map[slot] & 3;

	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
		 slot, set, set->nr_map);

	tmp = __raw_readb(OSIRIS_VA_CTRL0);
	tmp &= ~OSIRIS_CTRL0_NANDSEL;
	tmp |= slot;

	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
}

static struct s3c2410_platform_nand __initdata osiris_nand_info = {
	.tacls		= 25,
	.twrph0		= 60,
	.twrph1		= 60,
	.nr_sets	= ARRAY_SIZE(osiris_nand_sets),
	.sets		= osiris_nand_sets,
	.select_chip	= osiris_nand_select,
};

/* PCMCIA control and configuration */

static struct resource osiris_pcmcia_resource[] = {
	[0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
	[1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
};

static struct platform_device osiris_pcmcia = {
	.name		= "osiris-pcmcia",
	.id		= -1,
	.num_resources	= ARRAY_SIZE(osiris_pcmcia_resource),
	.resource	= osiris_pcmcia_resource,
};

/* Osiris power management device */

#ifdef CONFIG_PM
static unsigned char pm_osiris_ctrl0;

static int osiris_pm_suspend(void)
{
	unsigned int tmp;

	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;

	/* ensure correct NAND slot is selected on resume */
	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	        tmp |= 2;

	__raw_writeb(tmp, OSIRIS_VA_CTRL0);

	/* ensure that an nRESET is not generated on resume. */
	gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
	gpio_free(S3C2410_GPA(21));

	return 0;
}

static void osiris_pm_resume(void)
{
	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
		__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);

	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);

	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
}

#else
#define osiris_pm_suspend NULL
#define osiris_pm_resume NULL
#endif

static struct syscore_ops osiris_pm_syscore_ops = {
	.suspend	= osiris_pm_suspend,
	.resume		= osiris_pm_resume,
};

/* Link for DVS driver to TPS65011 */

static void osiris_tps_release(struct device *dev)
{
	/* static device, do not need to release anything */
}

static struct platform_device osiris_tps_device = {
	.name	= "osiris-dvs",
	.id	= -1,
	.dev.release = osiris_tps_release,
};

static int osiris_tps_setup(struct i2c_client *client, void *context)
{
	osiris_tps_device.dev.parent = &client->dev;
	return platform_device_register(&osiris_tps_device);
}

static int osiris_tps_remove(struct i2c_client *client, void *context)
{
	platform_device_unregister(&osiris_tps_device);
	return 0;
}

static struct tps65010_board osiris_tps_board = {
	.base		= -1,	/* GPIO can go anywhere at the moment */
	.setup		= osiris_tps_setup,
	.teardown	= osiris_tps_remove,
};

/* I2C devices fitted. */

static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	{
		I2C_BOARD_INFO("tps65011", 0x48),
		.irq	= IRQ_EINT20,
		.platform_data = &osiris_tps_board,
	},
};

/* Standard Osiris devices */

static struct platform_device *osiris_devices[] __initdata = {
	&s3c_device_i2c0,
	&s3c_device_wdt,
	&s3c_device_nand,
	&osiris_pcmcia,
};

static struct clk *osiris_clocks[] __initdata = {
	&s3c24xx_dclk0,
	&s3c24xx_dclk1,
	&s3c24xx_clkout0,
	&s3c24xx_clkout1,
	&s3c24xx_uclk,
};

static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	.refresh	= 7800, /* refresh period is 7.8usec */
	.auto_io	= 1,
	.need_io	= 1,
};

static void __init osiris_map_io(void)
{
	unsigned long flags;

	/* initialise the clocks */

	s3c24xx_dclk0.parent = &clk_upll;
	s3c24xx_dclk0.rate   = 12*1000*1000;

	s3c24xx_dclk1.parent = &clk_upll;
	s3c24xx_dclk1.rate   = 24*1000*1000;

	s3c24xx_clkout0.parent  = &s3c24xx_dclk0;
	s3c24xx_clkout1.parent  = &s3c24xx_dclk1;

	s3c24xx_uclk.parent  = &s3c24xx_clkout1;

	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));

	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	s3c24xx_init_clocks(0);
	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));

	/* check for the newer revision boards with large page nand */

	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
		printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
		       __raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
		osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
		osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	} else {
		/* write-protect line to the NAND */
		gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
		gpio_free(S3C2410_GPA(0));
	}

	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */

	local_irq_save(flags);
	__raw_writel(__raw_readl(S3C2410_BWSCON) | S3C2410_BWSCON_ST1 | S3C2410_BWSCON_ST2 | S3C2410_BWSCON_ST3 | S3C2410_BWSCON_ST4 | S3C2410_BWSCON_ST5, S3C2410_BWSCON);
	local_irq_restore(flags);
}

static void __init osiris_init(void)
{
	register_syscore_ops(&osiris_pm_syscore_ops);

	s3c_i2c0_set_platdata(NULL);
	s3c_nand_set_platdata(&osiris_nand_info);

	s3c_cpufreq_setboard(&osiris_cpufreq);

	i2c_register_board_info(0, osiris_i2c_devs,
				ARRAY_SIZE(osiris_i2c_devs));

	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
};

MACHINE_START(OSIRIS, "Simtec-OSIRIS")
	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
	.atag_offset	= 0x100,
	.map_io		= osiris_map_io,
	.init_irq	= s3c24xx_init_irq,
	.init_machine	= osiris_init,
	.init_time	= s3c24xx_timer_init,
	.restart	= s3c244x_restart,
MACHINE_END
Commit	Line	Data
a21765a7	1	/* linux/arch/arm/mach-s3c2440/mach-osiris.c
110d322b	2	*
ccae941e	3	* Copyright (c) 2005-2008 Simtec Electronics
110d322b BD	4	* http://armlinux.simtec.co.uk/
	5	* Ben Dooks <ben@simtec.co.uk>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/types.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/list.h>
	16	#include <linux/timer.h>
	17	#include <linux/init.h>
ec976d6e	18	#include <linux/gpio.h>
110d322b	19	#include <linux/device.h>
bb072c3c	20	#include <linux/syscore_ops.h>
b6d1f542	21	#include <linux/serial_core.h>
d96a9804	22	#include <linux/clk.h>
f3374221	23	#include <linux/i2c.h>
fced80c7	24	#include <linux/io.h>
110d322b	25
4fa084af BD	26	#include <linux/i2c/tps65010.h>
4fa084af BD	27
110d322b BD	28	#include <asm/mach/arch.h>
	29	#include <asm/mach/map.h>
	30	#include <asm/mach/irq.h>
	31
a09e64fb RK	32	#include <mach/osiris-map.h>
a09e64fb RK	33	#include <mach/osiris-cpld.h>
110d322b	34
a09e64fb	35	#include <mach/hardware.h>
110d322b BD	36	#include <asm/irq.h>
	37	#include <asm/mach-types.h>
	38
baf6b281	39	#include <plat/cpu-freq.h>
a2b7ba9c	40	#include <plat/regs-serial.h>
a09e64fb RK	41	#include <mach/regs-gpio.h>
	42	#include <mach/regs-mem.h>
	43	#include <mach/regs-lcd.h>
436d42c6 AB	44	#include <linux/platform_data/mtd-nand-s3c2410.h>
436d42c6 AB	45	#include <linux/platform_data/i2c-s3c2410.h>
110d322b BD	46
	47	#include <linux/mtd/mtd.h>
	48	#include <linux/mtd/nand.h>
	49	#include <linux/mtd/nand_ecc.h>
	50	#include <linux/mtd/partitions.h>
	51
40b956f0	52	#include <plat/gpio-cfg.h>
d5120ae7	53	#include <plat/clock.h>
a2b7ba9c BD	54	#include <plat/devs.h>
a2b7ba9c BD	55	#include <plat/cpu.h>
110d322b	56
b27b0727 KK	57	#include "common.h"
b27b0727 KK	58
6cbdc8c5	59	/* onboard perihperal map */
110d322b BD	60
	61	static struct map_desc osiris_iodesc[] __initdata = {
	62	/* ISA IO areas (may be over-written later) */
	63
	64	{
	65	.virtual = (u32)S3C24XX_VA_ISA_BYTE,
	66	.pfn = __phys_to_pfn(S3C2410_CS5),
	67	.length = SZ_16M,
	68	.type = MT_DEVICE,
	69	}, {
	70	.virtual = (u32)S3C24XX_VA_ISA_WORD,
	71	.pfn = __phys_to_pfn(S3C2410_CS5),
	72	.length = SZ_16M,
	73	.type = MT_DEVICE,
	74	},
	75
	76	/* CPLD control registers */
	77
	78	{
c362aecd BD	79	.virtual = (u32)OSIRIS_VA_CTRL0,
	80	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL0),
	81	.length = SZ_16K,
	82	.type = MT_DEVICE,
	83	}, {
110d322b BD	84	.virtual = (u32)OSIRIS_VA_CTRL1,
	85	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL1),
	86	.length = SZ_16K,
705630db	87	.type = MT_DEVICE,
110d322b BD	88	}, {
	89	.virtual = (u32)OSIRIS_VA_CTRL2,
	90	.pfn = __phys_to_pfn(OSIRIS_PA_CTRL2),
	91	.length = SZ_16K,
705630db	92	.type = MT_DEVICE,
c362aecd BD	93	}, {
	94	.virtual = (u32)OSIRIS_VA_IDREG,
	95	.pfn = __phys_to_pfn(OSIRIS_PA_IDREG),
	96	.length = SZ_16K,
	97	.type = MT_DEVICE,
110d322b BD	98	},
	99	};
	100
	101	#define UCON S3C2410_UCON_DEFAULT \| S3C2410_UCON_UCLK
	102	#define ULCON S3C2410_LCON_CS8 \| S3C2410_LCON_PNONE \| S3C2410_LCON_STOPB
	103	#define UFCON S3C2410_UFCON_RXTRIG8 \| S3C2410_UFCON_FIFOMODE
	104
66a9b49a	105	static struct s3c2410_uartcfg osiris_uartcfgs[] __initdata = {
110d322b BD	106	[0] = {
	107	.hwport = 0,
	108	.flags = 0,
	109	.ucon = UCON,
	110	.ulcon = ULCON,
	111	.ufcon = UFCON,
afba7f91	112	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
110d322b BD	113	},
110d322b BD	114	[1] = {
e2e5810f	115	.hwport = 1,
110d322b BD	116	.flags = 0,
	117	.ucon = UCON,
	118	.ulcon = ULCON,
	119	.ufcon = UFCON,
afba7f91	120	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
110d322b	121	},
ca7aa4de BD	122	[2] = {
	123	.hwport = 2,
	124	.flags = 0,
	125	.ucon = UCON,
	126	.ulcon = ULCON,
	127	.ufcon = UFCON,
afba7f91	128	.clk_sel = S3C2410_UCON_CLKSEL1 \| S3C2410_UCON_CLKSEL2,
ca7aa4de	129	}
110d322b BD	130	};
	131
	132	/* NAND Flash on Osiris board */
	133
	134	static int external_map[] = { 2 };
	135	static int chip0_map[] = { 0 };
	136	static int chip1_map[] = { 1 };
	137
2a3a1804	138	static struct mtd_partition __initdata osiris_default_nand_part[] = {
110d322b BD	139	[0] = {
	140	.name = "Boot Agent",
	141	.size = SZ_16K,
705630db	142	.offset = 0,
110d322b BD	143	},
	144	[1] = {
	145	.name = "/boot",
	146	.size = SZ_4M - SZ_16K,
	147	.offset = SZ_16K,
	148	},
	149	[2] = {
	150	.name = "user1",
	151	.offset = SZ_4M,
	152	.size = SZ_32M - SZ_4M,
	153	},
	154	[3] = {
	155	.name = "user2",
	156	.offset = SZ_32M,
	157	.size = MTDPART_SIZ_FULL,
	158	}
	159	};
	160
2a3a1804	161	static struct mtd_partition __initdata osiris_default_nand_part_large[] = {
3c3e69cd BD	162	[0] = {
	163	.name = "Boot Agent",
	164	.size = SZ_128K,
	165	.offset = 0,
	166	},
	167	[1] = {
	168	.name = "/boot",
	169	.size = SZ_4M - SZ_128K,
	170	.offset = SZ_128K,
	171	},
	172	[2] = {
	173	.name = "user1",
	174	.offset = SZ_4M,
	175	.size = SZ_32M - SZ_4M,
	176	},
	177	[3] = {
	178	.name = "user2",
	179	.offset = SZ_32M,
	180	.size = MTDPART_SIZ_FULL,
	181	}
	182	};
	183
110d322b BD	184	/* the Osiris has 3 selectable slots for nand-flash, the two
	185	* on-board chip areas, as well as the external slot.
	186	*
	187	* Note, there is no current hot-plug support for the External
	188	* socket.
	189	*/
	190
2a3a1804	191	static struct s3c2410_nand_set __initdata osiris_nand_sets[] = {
110d322b BD	192	[1] = {
	193	.name = "External",
	194	.nr_chips = 1,
	195	.nr_map = external_map,
d9237380	196	.options = NAND_SCAN_SILENT_NODEV,
110d322b	197	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	198	.partitions = osiris_default_nand_part,
110d322b BD	199	},
	200	[0] = {
	201	.name = "chip0",
	202	.nr_chips = 1,
	203	.nr_map = chip0_map,
	204	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	205	.partitions = osiris_default_nand_part,
110d322b BD	206	},
	207	[2] = {
	208	.name = "chip1",
	209	.nr_chips = 1,
	210	.nr_map = chip1_map,
d9237380	211	.options = NAND_SCAN_SILENT_NODEV,
110d322b	212	.nr_partitions = ARRAY_SIZE(osiris_default_nand_part),
705630db	213	.partitions = osiris_default_nand_part,
110d322b BD	214	},
	215	};
	216
	217	static void osiris_nand_select(struct s3c2410_nand_set *set, int slot)
	218	{
	219	unsigned int tmp;
	220
	221	slot = set->nr_map[slot] & 3;
	222
	223	pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n",
	224	slot, set, set->nr_map);
	225
c362aecd BD	226	tmp = __raw_readb(OSIRIS_VA_CTRL0);
c362aecd BD	227	tmp &= ~OSIRIS_CTRL0_NANDSEL;
110d322b BD	228	tmp \|= slot;
110d322b BD	229
c362aecd	230	pr_debug("osiris_nand: ctrl0 now %02x\n", tmp);
110d322b	231
c362aecd	232	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
110d322b BD	233	}
110d322b BD	234
2a3a1804	235	static struct s3c2410_platform_nand __initdata osiris_nand_info = {
110d322b BD	236	.tacls = 25,
	237	.twrph0 = 60,
	238	.twrph1 = 60,
	239	.nr_sets = ARRAY_SIZE(osiris_nand_sets),
	240	.sets = osiris_nand_sets,
	241	.select_chip = osiris_nand_select,
	242	};
	243
	244	/* PCMCIA control and configuration */
	245
	246	static struct resource osiris_pcmcia_resource[] = {
5ff2714a TB	247	[0] = DEFINE_RES_MEM(0x0f000000, SZ_1M),
5ff2714a TB	248	[1] = DEFINE_RES_MEM(0x0c000000, SZ_1M),
110d322b BD	249	};
	250
	251	static struct platform_device osiris_pcmcia = {
	252	.name = "osiris-pcmcia",
	253	.id = -1,
	254	.num_resources = ARRAY_SIZE(osiris_pcmcia_resource),
	255	.resource = osiris_pcmcia_resource,
	256	};
	257
5698bd28 BD	258	/* Osiris power management device */
	259
	260	#ifdef CONFIG_PM
	261	static unsigned char pm_osiris_ctrl0;
	262
bb072c3c	263	static int osiris_pm_suspend(void)
5698bd28	264	{
28047ece BD	265	unsigned int tmp;
28047ece BD	266
5698bd28	267	pm_osiris_ctrl0 = __raw_readb(OSIRIS_VA_CTRL0);
28047ece BD	268	tmp = pm_osiris_ctrl0 & ~OSIRIS_CTRL0_NANDSEL;
	269
	270	/* ensure correct NAND slot is selected on resume */
	271	if ((pm_osiris_ctrl0 & OSIRIS_CTRL0_BOOT_INT) == 0)
	272	tmp \|= 2;
	273
	274	__raw_writeb(tmp, OSIRIS_VA_CTRL0);
	275
4afcddae	276	/* ensure that an nRESET is not generated on resume. */
42aa322c SN	277	gpio_request_one(S3C2410_GPA(21), GPIOF_OUT_INIT_HIGH, NULL);
42aa322c SN	278	gpio_free(S3C2410_GPA(21));
4afcddae	279
5698bd28 BD	280	return 0;
	281	}
	282
bb072c3c	283	static void osiris_pm_resume(void)
5698bd28 BD	284	{
	285	if (pm_osiris_ctrl0 & OSIRIS_CTRL0_FIX8)
	286	__raw_writeb(OSIRIS_CTRL1_FIX8, OSIRIS_VA_CTRL1);
	287
28047ece BD	288	__raw_writeb(pm_osiris_ctrl0, OSIRIS_VA_CTRL0);
28047ece BD	289
40b956f0	290	s3c_gpio_cfgpin(S3C2410_GPA(21), S3C2410_GPA21_nRSTOUT);
5698bd28 BD	291	}
	292
	293	#else
	294	#define osiris_pm_suspend NULL
	295	#define osiris_pm_resume NULL
	296	#endif
	297
bb072c3c	298	static struct syscore_ops osiris_pm_syscore_ops = {
5698bd28 BD	299	.suspend = osiris_pm_suspend,
	300	.resume = osiris_pm_resume,
	301	};
	302
4fa084af BD	303	/* Link for DVS driver to TPS65011 */
	304
	305	static void osiris_tps_release(struct device *dev)
	306	{
	307	/* static device, do not need to release anything */
	308	}
	309
	310	static struct platform_device osiris_tps_device = {
	311	.name = "osiris-dvs",
	312	.id = -1,
	313	.dev.release = osiris_tps_release,
	314	};
	315
	316	static int osiris_tps_setup(struct i2c_client client, void context)
	317	{
	318	osiris_tps_device.dev.parent = &client->dev;
	319	return platform_device_register(&osiris_tps_device);
	320	}
	321
	322	static int osiris_tps_remove(struct i2c_client client, void context)
	323	{
	324	platform_device_unregister(&osiris_tps_device);
	325	return 0;
	326	}
	327
	328	static struct tps65010_board osiris_tps_board = {
	329	.base = -1, /* GPIO can go anywhere at the moment */
	330	.setup = osiris_tps_setup,
	331	.teardown = osiris_tps_remove,
	332	};
	333
f3374221 BD	334	/* I2C devices fitted. */
	335
	336	static struct i2c_board_info osiris_i2c_devs[] __initdata = {
	337	{
	338	I2C_BOARD_INFO("tps65011", 0x48),
	339	.irq = IRQ_EINT20,
4fa084af	340	.platform_data = &osiris_tps_board,
f3374221 BD	341	},
	342	};
	343
110d322b BD	344	/* Standard Osiris devices */
	345
	346	static struct platform_device *osiris_devices[] __initdata = {
3e1b776c	347	&s3c_device_i2c0,
55ba86bc	348	&s3c_device_wdt,
110d322b BD	349	&s3c_device_nand,
	350	&osiris_pcmcia,
	351	};
	352
2bc7509f	353	static struct clk *osiris_clocks[] __initdata = {
110d322b BD	354	&s3c24xx_dclk0,
	355	&s3c24xx_dclk1,
	356	&s3c24xx_clkout0,
	357	&s3c24xx_clkout1,
	358	&s3c24xx_uclk,
	359	};
	360
baf6b281 BD	361	static struct s3c_cpufreq_board __initdata osiris_cpufreq = {
	362	.refresh = 7800, /* refresh period is 7.8usec */
	363	.auto_io = 1,
	364	.need_io = 1,
	365	};
	366
da956fd6	367	static void __init osiris_map_io(void)
110d322b	368	{
da956fd6 BD	369	unsigned long flags;
da956fd6 BD	370
110d322b BD	371	/* initialise the clocks */
110d322b BD	372
d96a9804	373	s3c24xx_dclk0.parent = &clk_upll;
110d322b BD	374	s3c24xx_dclk0.rate = 1210001000;
110d322b BD	375
d96a9804	376	s3c24xx_dclk1.parent = &clk_upll;
110d322b BD	377	s3c24xx_dclk1.rate = 2410001000;
	378
	379	s3c24xx_clkout0.parent = &s3c24xx_dclk0;
	380	s3c24xx_clkout1.parent = &s3c24xx_dclk1;
	381
	382	s3c24xx_uclk.parent = &s3c24xx_clkout1;
	383
ce89c206 BD	384	s3c24xx_register_clocks(osiris_clocks, ARRAY_SIZE(osiris_clocks));
ce89c206 BD	385
110d322b BD	386	s3c24xx_init_io(osiris_iodesc, ARRAY_SIZE(osiris_iodesc));
	387	s3c24xx_init_clocks(0);
	388	s3c24xx_init_uarts(osiris_uartcfgs, ARRAY_SIZE(osiris_uartcfgs));
110d322b	389
3c3e69cd BD	390	/* check for the newer revision boards with large page nand */
	391
	392	if ((__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK) >= 4) {
	393	printk(KERN_INFO "OSIRIS-B detected (revision %d)\n",
	394	__raw_readb(OSIRIS_VA_IDREG) & OSIRIS_ID_REVMASK);
	395	osiris_nand_sets[0].partitions = osiris_default_nand_part_large;
	396	osiris_nand_sets[0].nr_partitions = ARRAY_SIZE(osiris_default_nand_part_large);
	397	} else {
	398	/* write-protect line to the NAND */
42aa322c SN	399	gpio_request_one(S3C2410_GPA(0), GPIOF_OUT_INIT_HIGH, NULL);
42aa322c SN	400	gpio_free(S3C2410_GPA(0));
3c3e69cd BD	401	}
3c3e69cd BD	402
110d322b	403	/* fix bus configuration (nBE settings wrong on ABLE pre v2.20) */
da956fd6 BD	404
da956fd6 BD	405	local_irq_save(flags);
110d322b	406	__raw_writel(__raw_readl(S3C2410_BWSCON) \| S3C2410_BWSCON_ST1 \| S3C2410_BWSCON_ST2 \| S3C2410_BWSCON_ST3 \| S3C2410_BWSCON_ST4 \| S3C2410_BWSCON_ST5, S3C2410_BWSCON);
da956fd6	407	local_irq_restore(flags);
110d322b BD	408	}
110d322b BD	409
57e5171c BD	410	static void __init osiris_init(void)
57e5171c BD	411	{
bb072c3c	412	register_syscore_ops(&osiris_pm_syscore_ops);
5698bd28	413
3e1b776c	414	s3c_i2c0_set_platdata(NULL);
2a3a1804	415	s3c_nand_set_platdata(&osiris_nand_info);
3e1b776c	416
baf6b281 BD	417	s3c_cpufreq_setboard(&osiris_cpufreq);
baf6b281 BD	418
f3374221 BD	419	i2c_register_board_info(0, osiris_i2c_devs,
	420	ARRAY_SIZE(osiris_i2c_devs));
	421
57e5171c BD	422	platform_add_devices(osiris_devices, ARRAY_SIZE(osiris_devices));
	423	};
	424
110d322b BD	425	MACHINE_START(OSIRIS, "Simtec-OSIRIS")
110d322b BD	426	/* Maintainer: Ben Dooks <ben@simtec.co.uk> */
69d50710	427	.atag_offset = 0x100,
110d322b BD	428	.map_io = osiris_map_io,
110d322b BD	429	.init_irq = s3c24xx_init_irq,
5698bd28	430	.init_machine = osiris_init,
6bb27d73	431	.init_time = s3c24xx_timer_init,
c1ba544f	432	.restart = s3c244x_restart,
110d322b	433	MACHINE_END