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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
3 | * (C) Copyright 2009 Samsung Electronics | |
4 | * Minkyu Kang <mk7.kang@samsung.com> | |
5 | * Heungjun Kim <riverful.kim@samsung.com> | |
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6 | */ |
7 | ||
8 | #ifndef _S5PC1XX_CPU_H | |
9 | #define _S5PC1XX_CPU_H | |
10 | ||
7775831d | 11 | #define S5P_CPU_NAME "S5P" |
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12 | #define S5PC1XX_ADDR_BASE 0xE0000000 |
13 | ||
399e5ae0 | 14 | /* S5PC100 */ |
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15 | #define S5PC100_PRO_ID 0xE0000000 |
16 | #define S5PC100_CLOCK_BASE 0xE0100000 | |
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17 | #define S5PC100_GPIO_BASE 0xE0300000 |
18 | #define S5PC100_VIC0_BASE 0xE4000000 | |
19 | #define S5PC100_VIC1_BASE 0xE4100000 | |
20 | #define S5PC100_VIC2_BASE 0xE4200000 | |
21 | #define S5PC100_DMC_BASE 0xE6000000 | |
22 | #define S5PC100_SROMC_BASE 0xE7000000 | |
23 | #define S5PC100_ONENAND_BASE 0xE7100000 | |
24 | #define S5PC100_PWMTIMER_BASE 0xEA000000 | |
25 | #define S5PC100_WATCHDOG_BASE 0xEA200000 | |
26 | #define S5PC100_UART_BASE 0xEC000000 | |
50002848 | 27 | #define S5PC100_MMC_BASE 0xED800000 |
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28 | |
29 | /* S5PC110 */ | |
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30 | #define S5PC110_PRO_ID 0xE0000000 |
31 | #define S5PC110_CLOCK_BASE 0xE0100000 | |
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32 | #define S5PC110_GPIO_BASE 0xE0200000 |
33 | #define S5PC110_PWMTIMER_BASE 0xE2500000 | |
34 | #define S5PC110_WATCHDOG_BASE 0xE2700000 | |
35 | #define S5PC110_UART_BASE 0xE2900000 | |
36 | #define S5PC110_SROMC_BASE 0xE8000000 | |
50002848 | 37 | #define S5PC110_MMC_BASE 0xEB000000 |
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38 | #define S5PC110_DMC0_BASE 0xF0000000 |
39 | #define S5PC110_DMC1_BASE 0xF1400000 | |
40 | #define S5PC110_VIC0_BASE 0xF2000000 | |
41 | #define S5PC110_VIC1_BASE 0xF2100000 | |
42 | #define S5PC110_VIC2_BASE 0xF2200000 | |
43 | #define S5PC110_VIC3_BASE 0xF2300000 | |
a954da29 ŁM |
44 | #define S5PC110_OTG_BASE 0xEC000000 |
45 | #define S5PC110_PHY_BASE 0xEC100000 | |
46 | #define S5PC110_USB_PHY_CONTROL 0xE010E80C | |
47 | ||
399e5ae0 | 48 | |
399e5ae0 | 49 | #ifndef __ASSEMBLY__ |
37168dab | 50 | #include <asm/io.h> |
399e5ae0 | 51 | /* CPU detection macros */ |
37168dab | 52 | extern unsigned int s5p_cpu_id; |
d1cbf0a5 PW |
53 | extern unsigned int s5p_cpu_rev; |
54 | ||
55 | static inline int s5p_get_cpu_rev(void) | |
56 | { | |
57 | return s5p_cpu_rev; | |
58 | } | |
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59 | |
60 | static inline void s5p_set_cpu_id(void) | |
61 | { | |
62 | s5p_cpu_id = readl(S5PC100_PRO_ID); | |
d1cbf0a5 | 63 | s5p_cpu_rev = s5p_cpu_id & 0x000000FF; |
37168dab MK |
64 | s5p_cpu_id = 0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12); |
65 | } | |
399e5ae0 | 66 | |
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67 | static inline char *s5p_get_cpu_name(void) |
68 | { | |
69 | return S5P_CPU_NAME; | |
70 | } | |
71 | ||
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72 | #define IS_SAMSUNG_TYPE(type, id) \ |
73 | static inline int cpu_is_##type(void) \ | |
74 | { \ | |
37168dab | 75 | return s5p_cpu_id == id ? 1 : 0; \ |
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76 | } |
77 | ||
78 | IS_SAMSUNG_TYPE(s5pc100, 0xc100) | |
79 | IS_SAMSUNG_TYPE(s5pc110, 0xc110) | |
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80 | |
81 | #define SAMSUNG_BASE(device, base) \ | |
82 | static inline unsigned int samsung_get_base_##device(void) \ | |
83 | { \ | |
84 | if (cpu_is_s5pc100()) \ | |
85 | return S5PC100_##base; \ | |
86 | else if (cpu_is_s5pc110()) \ | |
87 | return S5PC110_##base; \ | |
88 | else \ | |
89 | return 0; \ | |
545dabbe | 90 | } |
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91 | |
92 | SAMSUNG_BASE(clock, CLOCK_BASE) | |
93 | SAMSUNG_BASE(gpio, GPIO_BASE) | |
94 | SAMSUNG_BASE(pro_id, PRO_ID) | |
95 | SAMSUNG_BASE(mmc, MMC_BASE) | |
96 | SAMSUNG_BASE(sromc, SROMC_BASE) | |
97 | SAMSUNG_BASE(timer, PWMTIMER_BASE) | |
98 | SAMSUNG_BASE(uart, UART_BASE) | |
851db35e | 99 | SAMSUNG_BASE(watchdog, WATCHDOG_BASE) |
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100 | #endif |
101 | ||
102 | #endif /* _S5PC1XX_CPU_H */ |