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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
1da177e4 | 2 | /* |
a09e64fb | 3 | * arch/arm/mach-sa1100/include/mach/hardware.h |
1da177e4 | 4 | * |
2f82af08 | 5 | * Copyright (C) 1998 Nicolas Pitre <nico@fluxnic.net> |
1da177e4 LT |
6 | * |
7 | * This file contains the hardware definitions for SA1100 architecture | |
8 | * | |
9 | * 2000/05/23 John Dorsey <john+@cs.cmu.edu> | |
10 | * Definitions for SA1111 added. | |
11 | */ | |
12 | ||
13 | #ifndef __ASM_ARCH_HARDWARE_H | |
14 | #define __ASM_ARCH_HARDWARE_H | |
15 | ||
1da177e4 | 16 | |
c94e4ad2 | 17 | #define UNCACHEABLE_ADDR 0xfa050000 /* ICIP */ |
1da177e4 LT |
18 | |
19 | ||
1da177e4 LT |
20 | /* |
21 | * SA1100 internal I/O mappings | |
22 | * | |
23 | * We have the following mapping: | |
24 | * phys virt | |
25 | * 80000000 f8000000 | |
26 | * 90000000 fa000000 | |
27 | * a0000000 fc000000 | |
28 | * b0000000 fe000000 | |
29 | */ | |
30 | ||
31 | #define VIO_BASE 0xf8000000 /* virtual start of IO space */ | |
32 | #define VIO_SHIFT 3 /* x = IO space shrink power */ | |
33 | #define PIO_START 0x80000000 /* physical start of IO space */ | |
34 | ||
35 | #define io_p2v( x ) \ | |
3169663a | 36 | IOMEM( (((x)&0x00ffffff) | (((x)&0x30000000)>>VIO_SHIFT)) + VIO_BASE ) |
1da177e4 LT |
37 | #define io_v2p( x ) \ |
38 | ( (((x)&0x00ffffff) | (((x)&(0x30000000>>VIO_SHIFT))<<VIO_SHIFT)) + PIO_START ) | |
39 | ||
3169663a RK |
40 | #define __MREG(x) IOMEM(io_p2v(x)) |
41 | ||
1da177e4 | 42 | #ifndef __ASSEMBLY__ |
1da177e4 | 43 | |
3169663a | 44 | # define __REG(x) (*((volatile unsigned long __iomem *)io_p2v(x))) |
61c8c158 | 45 | # define __PREG(x) (io_v2p((unsigned long)&(x))) |
1da177e4 LT |
46 | |
47 | #else | |
48 | ||
49 | # define __REG(x) io_p2v(x) | |
50 | # define __PREG(x) io_v2p(x) | |
51 | ||
52 | #endif | |
53 | ||
54 | #include "SA-1100.h" | |
55 | ||
1da177e4 | 56 | #endif /* _ASM_ARCH_HARDWARE_H */ |