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[people/ms/u-boot.git] / arch / arm / mach-socfpga / clock_manager_arria10.c
CommitLineData
177ba1f9
LFT		 1/*
2 * Copyright (C) 2016-2017 Intel Corporation
3 *
4 * SPDX-License-Identifier: GPL-2.0
5 */
6
7#include <common.h>
8#include <fdtdec.h>
9#include <asm/io.h>
10#include <asm/arch/clock_manager.h>
11
12DECLARE_GLOBAL_DATA_PTR;
13
14static u32 eosc1_hz;
15static u32 cb_intosc_hz;
16static u32 f2s_free_hz;
17static u32 cm_l4_main_clk_hz;
18static u32 cm_l4_sp_clk_hz;
19static u32 cm_l4_mp_clk_hz;
20static u32 cm_l4_sys_free_clk_hz;
21
22struct mainpll_cfg {
23 u32 vco0_psrc;
24 u32 vco1_denom;
25 u32 vco1_numer;
26 u32 mpuclk;
27 u32 mpuclk_cnt;
28 u32 mpuclk_src;
29 u32 nocclk;
30 u32 nocclk_cnt;
31 u32 nocclk_src;
32 u32 cntr2clk_cnt;
33 u32 cntr3clk_cnt;
34 u32 cntr4clk_cnt;
35 u32 cntr5clk_cnt;
36 u32 cntr6clk_cnt;
37 u32 cntr7clk_cnt;
38 u32 cntr7clk_src;
39 u32 cntr8clk_cnt;
40 u32 cntr9clk_cnt;
41 u32 cntr9clk_src;
42 u32 cntr15clk_cnt;
43 u32 nocdiv_l4mainclk;
44 u32 nocdiv_l4mpclk;
45 u32 nocdiv_l4spclk;
46 u32 nocdiv_csatclk;
47 u32 nocdiv_cstraceclk;
48 u32 nocdiv_cspdbclk;
49};
50
51struct perpll_cfg {
52 u32 vco0_psrc;
53 u32 vco1_denom;
54 u32 vco1_numer;
55 u32 cntr2clk_cnt;
56 u32 cntr2clk_src;
57 u32 cntr3clk_cnt;
58 u32 cntr3clk_src;
59 u32 cntr4clk_cnt;
60 u32 cntr4clk_src;
61 u32 cntr5clk_cnt;
62 u32 cntr5clk_src;
63 u32 cntr6clk_cnt;
64 u32 cntr6clk_src;
65 u32 cntr7clk_cnt;
66 u32 cntr8clk_cnt;
67 u32 cntr8clk_src;
68 u32 cntr9clk_cnt;
69 u32 emacctl_emac0sel;
70 u32 emacctl_emac1sel;
71 u32 emacctl_emac2sel;
72 u32 gpiodiv_gpiodbclk;
73};
74
75struct alteragrp_cfg {
76 u32 nocclk;
77 u32 mpuclk;
78};
79
80static const struct socfpga_clock_manager *clock_manager_base =
81 (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
82
83static int of_to_struct(const void *blob, int node, int cfg_len, void *cfg)
84{
85 if (fdtdec_get_int_array(blob, node, "altr,of_reg_value",
86 (u32 *)cfg, cfg_len)) {
87 /* could not find required property */
88 return -EINVAL;
89 }
90
91 return 0;
92}
93
94static int of_get_input_clks(const void *blob, int node, u32 *val)
95{
96 *val = fdtdec_get_uint(blob, node, "clock-frequency", 0);
97 if (!*val)
98 return -EINVAL;
99
100 return 0;
101}
102
103static int of_get_clk_cfg(const void *blob, struct mainpll_cfg *main_cfg,
104 struct perpll_cfg *per_cfg,
105 struct alteragrp_cfg *altrgrp_cfg)
106{
107 int node, child, len;
108 const char *node_name;
109
110 node = fdtdec_next_compatible(blob, 0, COMPAT_ALTERA_SOCFPGA_CLK);
111 if (node < 0)
112 return -EINVAL;
113
114 child = fdt_first_subnode(blob, node);
115 if (child < 0)
116 return -EINVAL;
117
118 child = fdt_first_subnode(blob, child);
119 if (child < 0)
120 return -EINVAL;
121
122 node_name = fdt_get_name(blob, child, &len);
123
124 while (node_name) {
125 if (!strcmp(node_name, "osc1")) {
126 if (of_get_input_clks(blob, child, &eosc1_hz))
127 return -EINVAL;
128 } else if (!strcmp(node_name, "cb_intosc_ls_clk")) {
129 if (of_get_input_clks(blob, child, &cb_intosc_hz))
130 return -EINVAL;
131 } else if (!strcmp(node_name, "f2s_free_clk")) {
132 if (of_get_input_clks(blob, child, &f2s_free_hz))
133 return -EINVAL;
134 } else if (!strcmp(node_name, "main_pll")) {
135 if (of_to_struct(blob, child,
136 sizeof(*main_cfg)/sizeof(u32),
137 main_cfg))
138 return -EINVAL;
139 } else if (!strcmp(node_name, "periph_pll")) {
140 if (of_to_struct(blob, child,
141 sizeof(*per_cfg)/sizeof(u32),
142 per_cfg))
143 return -EINVAL;
144 } else if (!strcmp(node_name, "altera")) {
145 if (of_to_struct(blob, child,
146 sizeof(*altrgrp_cfg)/sizeof(u32),
147 altrgrp_cfg))
148 return -EINVAL;
149
150 main_cfg->mpuclk = altrgrp_cfg->mpuclk;
151 main_cfg->nocclk = altrgrp_cfg->nocclk;
152 }
153 child = fdt_next_subnode(blob, child);
154
155 if (child < 0)
156 break;
157
158 node_name = fdt_get_name(blob, child, &len);
159 }
160
161 return 0;
162}
163
164/* calculate the intended main VCO frequency based on handoff */
165static unsigned int cm_calc_handoff_main_vco_clk_hz
166 (struct mainpll_cfg *main_cfg)
167{
168 unsigned int clk_hz;
169
170 /* Check main VCO clock source: eosc, intosc or f2s? */
171 switch (main_cfg->vco0_psrc) {
172 case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
173 clk_hz = eosc1_hz;
174 break;
175 case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
176 clk_hz = cb_intosc_hz;
177 break;
178 case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
179 clk_hz = f2s_free_hz;
180 break;
181 default:
182 return 0;
183 }
184
185 /* calculate the VCO frequency */
186 clk_hz /= 1 + main_cfg->vco1_denom;
187 clk_hz *= 1 + main_cfg->vco1_numer;
188
189 return clk_hz;
190}
191
192/* calculate the intended periph VCO frequency based on handoff */
193static unsigned int cm_calc_handoff_periph_vco_clk_hz(
194 struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
195{
196 unsigned int clk_hz;
197
198 /* Check periph VCO clock source: eosc, intosc, f2s or mainpll? */
199 switch (per_cfg->vco0_psrc) {
200 case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
201 clk_hz = eosc1_hz;
202 break;
203 case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
204 clk_hz = cb_intosc_hz;
205 break;
206 case CLKMGR_PERPLL_VCO0_PSRC_F2S:
207 clk_hz = f2s_free_hz;
208 break;
209 case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
210 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
211 clk_hz /= main_cfg->cntr15clk_cnt;
212 break;
213 default:
214 return 0;
215 }
216
217 /* calculate the VCO frequency */
218 clk_hz /= 1 + per_cfg->vco1_denom;
219 clk_hz *= 1 + per_cfg->vco1_numer;
220
221 return clk_hz;
222}
223
224/* calculate the intended MPU clock frequency based on handoff */
225static unsigned int cm_calc_handoff_mpu_clk_hz(struct mainpll_cfg *main_cfg,
226 struct perpll_cfg *per_cfg)
227{
228 unsigned int clk_hz;
229
230 /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
231 switch (main_cfg->mpuclk_src) {
232 case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
233 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
234 clk_hz /= (main_cfg->mpuclk & CLKMGR_MAINPLL_MPUCLK_CNT_MSK)
235 + 1;
236 break;
237 case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
238 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
239 clk_hz /= ((main_cfg->mpuclk >>
240 CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
241 CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
242 break;
243 case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
244 clk_hz = eosc1_hz;
245 break;
246 case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
247 clk_hz = cb_intosc_hz;
248 break;
249 case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
250 clk_hz = f2s_free_hz;
251 break;
252 default:
253 return 0;
254 }
255
256 clk_hz /= main_cfg->mpuclk_cnt + 1;
257 return clk_hz;
258}
259
260/* calculate the intended NOC clock frequency based on handoff */
261static unsigned int cm_calc_handoff_noc_clk_hz(struct mainpll_cfg *main_cfg,
262 struct perpll_cfg *per_cfg)
263{
264 unsigned int clk_hz;
265
266 /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
267 switch (main_cfg->nocclk_src) {
268 case CLKMGR_MAINPLL_NOCCLK_SRC_MAIN:
269 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
270 clk_hz /= (main_cfg->nocclk & CLKMGR_MAINPLL_NOCCLK_CNT_MSK)
271 + 1;
272 break;
273 case CLKMGR_MAINPLL_NOCCLK_SRC_PERI:
274 clk_hz = cm_calc_handoff_periph_vco_clk_hz(main_cfg, per_cfg);
275 clk_hz /= ((main_cfg->nocclk >>
276 CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
277 CLKMGR_MAINPLL_NOCCLK_CNT_MSK) + 1;
278 break;
279 case CLKMGR_MAINPLL_NOCCLK_SRC_OSC1:
280 clk_hz = eosc1_hz;
281 break;
282 case CLKMGR_MAINPLL_NOCCLK_SRC_INTOSC:
283 clk_hz = cb_intosc_hz;
284 break;
285 case CLKMGR_MAINPLL_NOCCLK_SRC_FPGA:
286 clk_hz = f2s_free_hz;
287 break;
288 default:
289 return 0;
290 }
291
292 clk_hz /= main_cfg->nocclk_cnt + 1;
293 return clk_hz;
294}
295
296/* return 1 if PLL ramp is required */
297static int cm_is_pll_ramp_required(int main0periph1,
298 struct mainpll_cfg *main_cfg,
299 struct perpll_cfg *per_cfg)
300{
301 /* Check for main PLL */
302 if (main0periph1 == 0) {
303 /*
304 * PLL ramp is not required if both MPU clock and NOC clock are
305 * not sourced from main PLL
306 */
307 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
308 main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_MAIN)
309 return 0;
310
311 /*
312 * PLL ramp is required if MPU clock is sourced from main PLL
313 * and MPU clock is over 900MHz (as advised by HW team)
314 */
315 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN &&
316 (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
317 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
318 return 1;
319
320 /*
321 * PLL ramp is required if NOC clock is sourced from main PLL
322 * and NOC clock is over 300MHz (as advised by HW team)
323 */
324 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN &&
325 (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
326 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
327 return 2;
328
329 } else if (main0periph1 == 1) {
330 /*
331 * PLL ramp is not required if both MPU clock and NOC clock are
332 * not sourced from periph PLL
333 */
334 if (main_cfg->mpuclk_src != CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
335 main_cfg->nocclk_src != CLKMGR_MAINPLL_NOCCLK_SRC_PERI)
336 return 0;
337
338 /*
339 * PLL ramp is required if MPU clock are source from periph PLL
340 * and MPU clock is over 900MHz (as advised by HW team)
341 */
342 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI &&
343 (cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg) >
344 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ))
345 return 1;
346
347 /*
348 * PLL ramp is required if NOC clock are source from periph PLL
349 * and NOC clock is over 300MHz (as advised by HW team)
350 */
351 if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI &&
352 (cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg) >
353 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ))
354 return 2;
355 }
356
357 return 0;
358}
359
360static u32 cm_calculate_numer(struct mainpll_cfg *main_cfg,
361 struct perpll_cfg *per_cfg,
362 u32 safe_hz, u32 clk_hz)
363{
364 u32 cnt;
365 u32 clk;
366 u32 shift;
367 u32 mask;
368 u32 denom;
369
370 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
371 cnt = main_cfg->mpuclk_cnt;
372 clk = main_cfg->mpuclk;
373 shift = 0;
374 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
375 denom = main_cfg->vco1_denom;
376 } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
377 cnt = main_cfg->nocclk_cnt;
378 clk = main_cfg->nocclk;
379 shift = 0;
380 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
381 denom = main_cfg->vco1_denom;
382 } else if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
383 cnt = main_cfg->mpuclk_cnt;
384 clk = main_cfg->mpuclk;
385 shift = CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB;
386 mask = CLKMGR_MAINPLL_MPUCLK_CNT_MSK;
387 denom = per_cfg->vco1_denom;
388 } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
389 cnt = main_cfg->nocclk_cnt;
390 clk = main_cfg->nocclk;
391 shift = CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB;
392 mask = CLKMGR_MAINPLL_NOCCLK_CNT_MSK;
393 denom = per_cfg->vco1_denom;
394 } else {
395 return 0;
396 }
397
398 return (safe_hz / clk_hz) * (cnt + 1) * (((clk >> shift) & mask) + 1) *
399 (1 + denom) - 1;
400}
401
402/*
403 * Calculate the new PLL numerator which is based on existing DTS hand off and
404 * intended safe frequency (safe_hz). Note that PLL ramp is only modifying the
405 * numerator while maintaining denominator as denominator will influence the
406 * jitter condition. Please refer A10 HPS TRM for the jitter guide. Note final
407 * value for numerator is minus with 1 to cater our register value
408 * representation.
409 */
410static unsigned int cm_calc_safe_pll_numer(int main0periph1,
411 struct mainpll_cfg *main_cfg,
412 struct perpll_cfg *per_cfg,
413 unsigned int safe_hz)
414{
415 unsigned int clk_hz = 0;
416
417 /* Check for main PLL */
418 if (main0periph1 == 0) {
419 /* Check main VCO clock source: eosc, intosc or f2s? */
420 switch (main_cfg->vco0_psrc) {
421 case CLKMGR_MAINPLL_VCO0_PSRC_EOSC:
422 clk_hz = eosc1_hz;
423 break;
424 case CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC:
425 clk_hz = cb_intosc_hz;
426 break;
427 case CLKMGR_MAINPLL_VCO0_PSRC_F2S:
428 clk_hz = f2s_free_hz;
429 break;
430 default:
431 return 0;
432 }
433 } else if (main0periph1 == 1) {
434 /* Check periph VCO clock source: eosc, intosc, f2s, mainpll */
435 switch (per_cfg->vco0_psrc) {
436 case CLKMGR_PERPLL_VCO0_PSRC_EOSC:
437 clk_hz = eosc1_hz;
438 break;
439 case CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC:
440 clk_hz = cb_intosc_hz;
441 break;
442 case CLKMGR_PERPLL_VCO0_PSRC_F2S:
443 clk_hz = f2s_free_hz;
444 break;
445 case CLKMGR_PERPLL_VCO0_PSRC_MAIN:
446 clk_hz = cm_calc_handoff_main_vco_clk_hz(main_cfg);
447 clk_hz /= main_cfg->cntr15clk_cnt;
448 break;
449 default:
450 return 0;
451 }
452 } else {
453 return 0;
454 }
455
456 return cm_calculate_numer(main_cfg, per_cfg, safe_hz, clk_hz);
457}
458
459/* ramping the main PLL to final value */
460static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
461 struct perpll_cfg *per_cfg,
462 unsigned int pll_ramp_main_hz)
463{
464 unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
465
466 /* find out the increment value */
467 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_MAIN) {
468 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
469 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
470 } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_MAIN) {
471 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
472 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
473 }
474
475 /* execute the ramping here */
476 for (clk_hz = pll_ramp_main_hz + clk_incr_hz;
477 clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
478 writel((main_cfg->vco1_denom <<
479 CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
480 cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
481 &clock_manager_base->main_pll.vco1);
482 mdelay(1);
483 cm_wait_for_lock(LOCKED_MASK);
484 }
485 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
486 main_cfg->vco1_numer, &clock_manager_base->main_pll.vco1);
487 mdelay(1);
488 cm_wait_for_lock(LOCKED_MASK);
489}
490
491/* ramping the periph PLL to final value */
492static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,
493 struct perpll_cfg *per_cfg,
494 unsigned int pll_ramp_periph_hz)
495{
496 unsigned int clk_hz = 0, clk_incr_hz = 0, clk_final_hz = 0;
497
498 /* find out the increment value */
499 if (main_cfg->mpuclk_src == CLKMGR_MAINPLL_MPUCLK_SRC_PERI) {
500 clk_incr_hz = CLKMGR_PLL_RAMP_MPUCLK_INCREMENT_HZ;
501 clk_final_hz = cm_calc_handoff_mpu_clk_hz(main_cfg, per_cfg);
502 } else if (main_cfg->nocclk_src == CLKMGR_MAINPLL_NOCCLK_SRC_PERI) {
503 clk_incr_hz = CLKMGR_PLL_RAMP_NOCCLK_INCREMENT_HZ;
504 clk_final_hz = cm_calc_handoff_noc_clk_hz(main_cfg, per_cfg);
505 }
506 /* execute the ramping here */
507 for (clk_hz = pll_ramp_periph_hz + clk_incr_hz;
508 clk_hz < clk_final_hz; clk_hz += clk_incr_hz) {
509 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
510 cm_calc_safe_pll_numer(1, main_cfg, per_cfg, clk_hz),
511 &clock_manager_base->per_pll.vco1);
512 mdelay(1);
513 cm_wait_for_lock(LOCKED_MASK);
514 }
515 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
516 per_cfg->vco1_numer, &clock_manager_base->per_pll.vco1);
517 mdelay(1);
518 cm_wait_for_lock(LOCKED_MASK);
519}
520
521/*
522 * Setup clocks while making no assumptions of the
523 * previous state of the clocks.
524 *
525 * Start by being paranoid and gate all sw managed clocks
526 *
527 * Put all plls in bypass
528 *
529 * Put all plls VCO registers back to reset value (bgpwr dwn).
530 *
531 * Put peripheral and main pll src to reset value to avoid glitch.
532 *
533 * Delay 5 us.
534 *
535 * Deassert bg pwr dn and set numerator and denominator
536 *
537 * Start 7 us timer.
538 *
539 * set internal dividers
540 *
541 * Wait for 7 us timer.
542 *
543 * Enable plls
544 *
545 * Set external dividers while plls are locking
546 *
547 * Wait for pll lock
548 *
549 * Assert/deassert outreset all.
550 *
551 * Take all pll's out of bypass
552 *
553 * Clear safe mode
554 *
555 * set source main and peripheral clocks
556 *
557 * Ungate clocks
558 */
559
560static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)
561{
562 unsigned int pll_ramp_main_hz = 0, pll_ramp_periph_hz = 0,
563 ramp_required;
564
565 /* gate off all mainpll clock excpet HW managed clock */
566 writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
567 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
568 &clock_manager_base->main_pll.enr);
569
570 /* now we can gate off the rest of the peripheral clocks */
571 writel(0, &clock_manager_base->per_pll.en);
572
573 /* Put all plls in external bypass */
574 writel(CLKMGR_MAINPLL_BYPASS_RESET,
575 &clock_manager_base->main_pll.bypasss);
576 writel(CLKMGR_PERPLL_BYPASS_RESET,
577 &clock_manager_base->per_pll.bypasss);
578
579 /*
580 * Put all plls VCO registers back to reset value.
581 * Some code might have messed with them. At same time set the
582 * desired clock source
583 */
584 writel(CLKMGR_MAINPLL_VCO0_RESET |
585 CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK |
586 (main_cfg->vco0_psrc << CLKMGR_MAINPLL_VCO0_PSRC_LSB),
587 &clock_manager_base->main_pll.vco0);
588
589 writel(CLKMGR_PERPLL_VCO0_RESET |
590 CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK |
591 (per_cfg->vco0_psrc << CLKMGR_PERPLL_VCO0_PSRC_LSB),
592 &clock_manager_base->per_pll.vco0);
593
594 writel(CLKMGR_MAINPLL_VCO1_RESET, &clock_manager_base->main_pll.vco1);
595 writel(CLKMGR_PERPLL_VCO1_RESET, &clock_manager_base->per_pll.vco1);
596
597 /* clear the interrupt register status register */
598 writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
599 CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
600 CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
601 CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
602 CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
603 CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK |
604 CLKMGR_CLKMGR_INTR_MAINPLLACHIEVED_SET_MSK |
605 CLKMGR_CLKMGR_INTR_PERPLLACHIEVED_SET_MSK,
606 &clock_manager_base->intr);
607
608 /* Program VCO Numerator and Denominator for main PLL */
609 ramp_required = cm_is_pll_ramp_required(0, main_cfg, per_cfg);
610 if (ramp_required) {
611 /* set main PLL to safe starting threshold frequency */
612 if (ramp_required == 1)
613 pll_ramp_main_hz = CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
614 else if (ramp_required == 2)
615 pll_ramp_main_hz = CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
616
617 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
618 cm_calc_safe_pll_numer(0, main_cfg, per_cfg,
619 pll_ramp_main_hz),
620 &clock_manager_base->main_pll.vco1);
621 } else
622 writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
623 main_cfg->vco1_numer,
624 &clock_manager_base->main_pll.vco1);
625
626 /* Program VCO Numerator and Denominator for periph PLL */
627 ramp_required = cm_is_pll_ramp_required(1, main_cfg, per_cfg);
628 if (ramp_required) {
629 /* set periph PLL to safe starting threshold frequency */
630 if (ramp_required == 1)
631 pll_ramp_periph_hz =
632 CLKMGR_PLL_RAMP_MPUCLK_THRESHOLD_HZ;
633 else if (ramp_required == 2)
634 pll_ramp_periph_hz =
635 CLKMGR_PLL_RAMP_NOCCLK_THRESHOLD_HZ;
636
637 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
638 cm_calc_safe_pll_numer(1, main_cfg, per_cfg,
639 pll_ramp_periph_hz),
640 &clock_manager_base->per_pll.vco1);
641 } else
642 writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
643 per_cfg->vco1_numer,
644 &clock_manager_base->per_pll.vco1);
645
646 /* Wait for at least 5 us */
647 udelay(5);
648
649 /* Now deassert BGPWRDN and PWRDN */
650 clrbits_le32(&clock_manager_base->main_pll.vco0,
651 CLKMGR_MAINPLL_VCO0_BGPWRDN_SET_MSK |
652 CLKMGR_MAINPLL_VCO0_PWRDN_SET_MSK);
653 clrbits_le32(&clock_manager_base->per_pll.vco0,
654 CLKMGR_PERPLL_VCO0_BGPWRDN_SET_MSK |
655 CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
656
657 /* Wait for at least 7 us */
658 udelay(7);
659
660 /* enable the VCO and disable the external regulator to PLL */
661 writel((readl(&clock_manager_base->main_pll.vco0) &
662 ~CLKMGR_MAINPLL_VCO0_REGEXTSEL_SET_MSK) |
663 CLKMGR_MAINPLL_VCO0_EN_SET_MSK,
664 &clock_manager_base->main_pll.vco0);
665 writel((readl(&clock_manager_base->per_pll.vco0) &
666 ~CLKMGR_PERPLL_VCO0_REGEXTSEL_SET_MSK) |
667 CLKMGR_PERPLL_VCO0_EN_SET_MSK,
668 &clock_manager_base->per_pll.vco0);
669
670 /* setup all the main PLL counter and clock source */
671 writel(main_cfg->nocclk,
672 SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET);
673 writel(main_cfg->mpuclk,
674 SOCFPGA_CLKMGR_ADDRESS + CLKMGR_ALTERAGRP_MPU_CLK_OFFSET);
675
676 /* main_emaca_clk divider */
677 writel(main_cfg->cntr2clk_cnt, &clock_manager_base->main_pll.cntr2clk);
678 /* main_emacb_clk divider */
679 writel(main_cfg->cntr3clk_cnt, &clock_manager_base->main_pll.cntr3clk);
680 /* main_emac_ptp_clk divider */
681 writel(main_cfg->cntr4clk_cnt, &clock_manager_base->main_pll.cntr4clk);
682 /* main_gpio_db_clk divider */
683 writel(main_cfg->cntr5clk_cnt, &clock_manager_base->main_pll.cntr5clk);
684 /* main_sdmmc_clk divider */
685 writel(main_cfg->cntr6clk_cnt, &clock_manager_base->main_pll.cntr6clk);
686 /* main_s2f_user0_clk divider */
687 writel(main_cfg->cntr7clk_cnt |
688 (main_cfg->cntr7clk_src << CLKMGR_MAINPLL_CNTR7CLK_SRC_LSB),
689 &clock_manager_base->main_pll.cntr7clk);
690 /* main_s2f_user1_clk divider */
691 writel(main_cfg->cntr8clk_cnt, &clock_manager_base->main_pll.cntr8clk);
692 /* main_hmc_pll_clk divider */
693 writel(main_cfg->cntr9clk_cnt |
694 (main_cfg->cntr9clk_src << CLKMGR_MAINPLL_CNTR9CLK_SRC_LSB),
695 &clock_manager_base->main_pll.cntr9clk);
696 /* main_periph_ref_clk divider */
697 writel(main_cfg->cntr15clk_cnt,
698 &clock_manager_base->main_pll.cntr15clk);
699
700 /* setup all the peripheral PLL counter and clock source */
701 /* peri_emaca_clk divider */
702 writel(per_cfg->cntr2clk_cnt |
703 (per_cfg->cntr2clk_src << CLKMGR_PERPLL_CNTR2CLK_SRC_LSB),
704 &clock_manager_base->per_pll.cntr2clk);
705 /* peri_emacb_clk divider */
706 writel(per_cfg->cntr3clk_cnt |
707 (per_cfg->cntr3clk_src << CLKMGR_PERPLL_CNTR3CLK_SRC_LSB),
708 &clock_manager_base->per_pll.cntr3clk);
709 /* peri_emac_ptp_clk divider */
710 writel(per_cfg->cntr4clk_cnt |
711 (per_cfg->cntr4clk_src << CLKMGR_PERPLL_CNTR4CLK_SRC_LSB),
712 &clock_manager_base->per_pll.cntr4clk);
713 /* peri_gpio_db_clk divider */
714 writel(per_cfg->cntr5clk_cnt |
715 (per_cfg->cntr5clk_src << CLKMGR_PERPLL_CNTR5CLK_SRC_LSB),
716 &clock_manager_base->per_pll.cntr5clk);
717 /* peri_sdmmc_clk divider */
718 writel(per_cfg->cntr6clk_cnt |
719 (per_cfg->cntr6clk_src << CLKMGR_PERPLL_CNTR6CLK_SRC_LSB),
720 &clock_manager_base->per_pll.cntr6clk);
721 /* peri_s2f_user0_clk divider */
722 writel(per_cfg->cntr7clk_cnt, &clock_manager_base->per_pll.cntr7clk);
723 /* peri_s2f_user1_clk divider */
724 writel(per_cfg->cntr8clk_cnt |
725 (per_cfg->cntr8clk_src << CLKMGR_PERPLL_CNTR8CLK_SRC_LSB),
726 &clock_manager_base->per_pll.cntr8clk);
727 /* peri_hmc_pll_clk divider */
728 writel(per_cfg->cntr9clk_cnt, &clock_manager_base->per_pll.cntr9clk);
729
730 /* setup all the external PLL counter */
731 /* mpu wrapper / external divider */
732 writel(main_cfg->mpuclk_cnt |
733 (main_cfg->mpuclk_src << CLKMGR_MAINPLL_MPUCLK_SRC_LSB),
734 &clock_manager_base->main_pll.mpuclk);
735 /* NOC wrapper / external divider */
736 writel(main_cfg->nocclk_cnt |
737 (main_cfg->nocclk_src << CLKMGR_MAINPLL_NOCCLK_SRC_LSB),
738 &clock_manager_base->main_pll.nocclk);
739 /* NOC subclock divider such as l4 */
740 writel(main_cfg->nocdiv_l4mainclk |
741 (main_cfg->nocdiv_l4mpclk <<
742 CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) |
743 (main_cfg->nocdiv_l4spclk <<
744 CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB) |
745 (main_cfg->nocdiv_csatclk <<
746 CLKMGR_MAINPLL_NOCDIV_CSATCLK_LSB) |
747 (main_cfg->nocdiv_cstraceclk <<
748 CLKMGR_MAINPLL_NOCDIV_CSTRACECLK_LSB) |
749 (main_cfg->nocdiv_cspdbclk <<
750 CLKMGR_MAINPLL_NOCDIV_CSPDBGCLK_LSB),
751 &clock_manager_base->main_pll.nocdiv);
752 /* gpio_db external divider */
753 writel(per_cfg->gpiodiv_gpiodbclk,
754 &clock_manager_base->per_pll.gpiodiv);
755
756 /* setup the EMAC clock mux select */
757 writel((per_cfg->emacctl_emac0sel <<
758 CLKMGR_PERPLL_EMACCTL_EMAC0SEL_LSB) |
759 (per_cfg->emacctl_emac1sel <<
760 CLKMGR_PERPLL_EMACCTL_EMAC1SEL_LSB) |
761 (per_cfg->emacctl_emac2sel <<
762 CLKMGR_PERPLL_EMACCTL_EMAC2SEL_LSB),
763 &clock_manager_base->per_pll.emacctl);
764
765 /* at this stage, check for PLL lock status */
766 cm_wait_for_lock(LOCKED_MASK);
767
768 /*
769 * after locking, but before taking out of bypass,
770 * assert/deassert outresetall
771 */
772 /* assert mainpll outresetall */
773 setbits_le32(&clock_manager_base->main_pll.vco0,
774 CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
775 /* assert perpll outresetall */
776 setbits_le32(&clock_manager_base->per_pll.vco0,
777 CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
778 /* de-assert mainpll outresetall */
779 clrbits_le32(&clock_manager_base->main_pll.vco0,
780 CLKMGR_MAINPLL_VCO0_OUTRSTALL_SET_MSK);
781 /* de-assert perpll outresetall */
782 clrbits_le32(&clock_manager_base->per_pll.vco0,
783 CLKMGR_PERPLL_VCO0_OUTRSTALL_SET_MSK);
784
785 /* Take all PLLs out of bypass when boot mode is cleared. */
786 /* release mainpll from bypass */
787 writel(CLKMGR_MAINPLL_BYPASS_RESET,
788 &clock_manager_base->main_pll.bypassr);
789 /* wait till Clock Manager is not busy */
790 cm_wait_for_fsm();
791
792 /* release perpll from bypass */
793 writel(CLKMGR_PERPLL_BYPASS_RESET,
794 &clock_manager_base->per_pll.bypassr);
795 /* wait till Clock Manager is not busy */
796 cm_wait_for_fsm();
797
798 /* clear boot mode */
799 clrbits_le32(&clock_manager_base->ctrl,
800 CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
801 /* wait till Clock Manager is not busy */
802 cm_wait_for_fsm();
803
804 /* At here, we need to ramp to final value if needed */
805 if (pll_ramp_main_hz != 0)
806 cm_pll_ramp_main(main_cfg, per_cfg, pll_ramp_main_hz);
807 if (pll_ramp_periph_hz != 0)
808 cm_pll_ramp_periph(main_cfg, per_cfg, pll_ramp_periph_hz);
809
810 /* Now ungate non-hw-managed clocks */
811 writel(CLKMGR_MAINPLL_EN_S2FUSER0CLKEN_SET_MSK |
812 CLKMGR_MAINPLL_EN_HMCPLLREFCLKEN_SET_MSK,
813 &clock_manager_base->main_pll.ens);
814 writel(CLKMGR_PERPLL_EN_RESET, &clock_manager_base->per_pll.ens);
815
816 /* Clear the loss lock and slip bits as they might set during
817 clock reconfiguration */
818 writel(CLKMGR_CLKMGR_INTR_MAINPLLLOST_SET_MSK |
819 CLKMGR_CLKMGR_INTR_PERPLLLOST_SET_MSK |
820 CLKMGR_CLKMGR_INTR_MAINPLLRFSLIP_SET_MSK |
821 CLKMGR_CLKMGR_INTR_PERPLLRFSLIP_SET_MSK |
822 CLKMGR_CLKMGR_INTR_MAINPLLFBSLIP_SET_MSK |
823 CLKMGR_CLKMGR_INTR_PERPLLFBSLIP_SET_MSK,
824 &clock_manager_base->intr);
825
826 return 0;
827}
828
829void cm_use_intosc(void)
830{
831 setbits_le32(&clock_manager_base->ctrl,
832 CLKMGR_CLKMGR_CTL_BOOTCLK_INTOSC_SET_MSK);
833}
834
835unsigned int cm_get_noc_clk_hz(void)
836{
837 unsigned int clk_src, divisor, nocclk, src_hz;
838
839 nocclk = readl(&clock_manager_base->main_pll.nocclk);
840 clk_src = (nocclk >> CLKMGR_MAINPLL_NOCCLK_SRC_LSB) &
841 CLKMGR_MAINPLL_NOCCLK_SRC_MSK;
842
843 divisor = 1 + (nocclk & CLKMGR_MAINPLL_NOCDIV_MSK);
844
845 if (clk_src == CLKMGR_PERPLLGRP_SRC_MAIN) {
846 src_hz = cm_get_main_vco_clk_hz();
847 src_hz /= 1 +
848 (readl(SOCFPGA_CLKMGR_ADDRESS + CLKMGR_MAINPLL_NOC_CLK_OFFSET) &
849 CLKMGR_MAINPLL_NOCCLK_CNT_MSK);
850 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_PERI) {
851 src_hz = cm_get_per_vco_clk_hz();
852 src_hz /= 1 +
853 ((readl(SOCFPGA_CLKMGR_ADDRESS +
854 CLKMGR_MAINPLL_NOC_CLK_OFFSET) >>
855 CLKMGR_MAINPLL_NOCCLK_PERICNT_LSB) &
856 CLKMGR_MAINPLL_NOCCLK_CNT_MSK);
857 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_OSC1) {
858 src_hz = eosc1_hz;
859 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_INTOSC) {
860 src_hz = cb_intosc_hz;
861 } else if (clk_src == CLKMGR_PERPLLGRP_SRC_FPGA) {
862 src_hz = f2s_free_hz;
863 } else {
864 src_hz = 0;
865 }
866
867 return src_hz / divisor;
868}
869
870unsigned int cm_get_l4_noc_hz(unsigned int nocdivshift)
871{
872 unsigned int divisor2 = 1 <<
873 ((readl(&clock_manager_base->main_pll.nocdiv) >>
874 nocdivshift) & CLKMGR_MAINPLL_NOCDIV_MSK);
875
876 return cm_get_noc_clk_hz() / divisor2;
877}
878
879int cm_basic_init(const void *blob)
880{
881 struct mainpll_cfg main_cfg;
882 struct perpll_cfg per_cfg;
883 struct alteragrp_cfg altrgrp_cfg;
884 int rval;
885
886 /* initialize to zero for use case of optional node */
887 memset(&main_cfg, 0, sizeof(main_cfg));
888 memset(&per_cfg, 0, sizeof(per_cfg));
889 memset(&altrgrp_cfg, 0, sizeof(altrgrp_cfg));
890
891 rval = of_get_clk_cfg(blob, &main_cfg, &per_cfg, &altrgrp_cfg);
892 if (rval)
893 return rval;
894
895 rval = cm_full_cfg(&main_cfg, &per_cfg);
896
897 cm_l4_main_clk_hz =
898 cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
899
900 cm_l4_mp_clk_hz = cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
901
902 cm_l4_sp_clk_hz = cm_get_l4_sp_clk_hz();
903
904 cm_l4_sys_free_clk_hz = cm_get_noc_clk_hz() / 4;
905
906 return rval;
907}
908
909unsigned long cm_get_mpu_clk_hz(void)
910{
911 u32 reg, clk_hz;
912 u32 clk_src, mainmpuclk_reg;
913
914 mainmpuclk_reg = readl(&clock_manager_base->main_pll.mpuclk);
915
916 clk_src = (mainmpuclk_reg >> CLKMGR_MAINPLL_MPUCLK_SRC_LSB) &
917 CLKMGR_MAINPLL_MPUCLK_SRC_MSK;
918
919 reg = readl(&clock_manager_base->altera.mpuclk);
920 /* Check MPU clock source: main, periph, osc1, intosc or f2s? */
921 switch (clk_src) {
922 case CLKMGR_MAINPLL_MPUCLK_SRC_MAIN:
923 clk_hz = cm_get_main_vco_clk_hz();
924 clk_hz /= (reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
925 break;
926 case CLKMGR_MAINPLL_MPUCLK_SRC_PERI:
927 clk_hz = cm_get_per_vco_clk_hz();
928 clk_hz /= (((reg >> CLKMGR_MAINPLL_MPUCLK_PERICNT_LSB) &
929 CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1);
930 break;
931 case CLKMGR_MAINPLL_MPUCLK_SRC_OSC1:
932 clk_hz = eosc1_hz;
933 break;
934 case CLKMGR_MAINPLL_MPUCLK_SRC_INTOSC:
935 clk_hz = cb_intosc_hz;
936 break;
937 case CLKMGR_MAINPLL_MPUCLK_SRC_FPGA:
938 clk_hz = f2s_free_hz;
939 break;
940 default:
941 printf("cm_get_mpu_clk_hz invalid clk_src %d\n", clk_src);
942 return 0;
943 }
944
945 clk_hz /= (mainmpuclk_reg & CLKMGR_MAINPLL_MPUCLK_CNT_MSK) + 1;
946
947 return clk_hz;
948}
949
950unsigned int cm_get_per_vco_clk_hz(void)
951{
952 u32 src_hz = 0;
953 u32 clk_src = 0;
954 u32 numer = 0;
955 u32 denom = 0;
956 u32 vco = 0;
957
958 clk_src = readl(&clock_manager_base->per_pll.vco0);
959
960 clk_src = (clk_src >> CLKMGR_PERPLL_VCO0_PSRC_LSB) &
961 CLKMGR_PERPLL_VCO0_PSRC_MSK;
962
963 if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_EOSC) {
964 src_hz = eosc1_hz;
965 } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_E_INTOSC) {
966 src_hz = cb_intosc_hz;
967 } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_F2S) {
968 src_hz = f2s_free_hz;
969 } else if (clk_src == CLKMGR_PERPLL_VCO0_PSRC_MAIN) {
970 src_hz = cm_get_main_vco_clk_hz();
971 src_hz /= (readl(&clock_manager_base->main_pll.cntr15clk) &
972 CLKMGR_MAINPLL_CNTRCLK_MSK) + 1;
973 } else {
974 printf("cm_get_per_vco_clk_hz invalid clk_src %d\n", clk_src);
975 return 0;
976 }
977
978 vco = readl(&clock_manager_base->per_pll.vco1);
979
980 numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK;
981
982 denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) &
983 CLKMGR_PERPLL_VCO1_DENOM_MSK;
984
985 vco = src_hz;
986 vco /= 1 + denom;
987 vco *= 1 + numer;
988
989 return vco;
990}
991
992unsigned int cm_get_main_vco_clk_hz(void)
993{
994 u32 src_hz, numer, denom, vco;
995
996 u32 clk_src = readl(&clock_manager_base->main_pll.vco0);
997
998 clk_src = (clk_src >> CLKMGR_MAINPLL_VCO0_PSRC_LSB) &
999 CLKMGR_MAINPLL_VCO0_PSRC_MSK;
1000
1001 if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_EOSC) {
1002 src_hz = eosc1_hz;
1003 } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_E_INTOSC) {
1004 src_hz = cb_intosc_hz;
1005 } else if (clk_src == CLKMGR_MAINPLL_VCO0_PSRC_F2S) {
1006 src_hz = f2s_free_hz;
1007 } else {
1008 printf("cm_get_main_vco_clk_hz invalid clk_src %d\n", clk_src);
1009 return 0;
1010 }
1011
1012 vco = readl(&clock_manager_base->main_pll.vco1);
1013
1014 numer = vco & CLKMGR_MAINPLL_VCO1_NUMER_MSK;
1015
1016 denom = (vco >> CLKMGR_MAINPLL_VCO1_DENOM_LSB) &
1017 CLKMGR_MAINPLL_VCO1_DENOM_MSK;
1018
1019 vco = src_hz;
1020 vco /= 1 + denom;
1021 vco *= 1 + numer;
1022
1023 return vco;
1024}
1025
1026unsigned int cm_get_l4_sp_clk_hz(void)
1027{
1028 return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4SPCLK_LSB);
1029}
1030
1031unsigned int cm_get_mmc_controller_clk_hz(void)
1032{
1033 u32 clk_hz = 0;
1034 u32 clk_input = 0;
1035
1036 clk_input = readl(&clock_manager_base->per_pll.cntr6clk);
1037 clk_input = (clk_input >> CLKMGR_PERPLL_CNTR6CLK_SRC_LSB) &
1038 CLKMGR_PERPLLGRP_SRC_MSK;
1039
1040 switch (clk_input) {
1041 case CLKMGR_PERPLLGRP_SRC_MAIN:
1042 clk_hz = cm_get_main_vco_clk_hz();
1043 clk_hz /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
1044 CLKMGR_MAINPLL_CNTRCLK_MSK);
1045 break;
1046
1047 case CLKMGR_PERPLLGRP_SRC_PERI:
1048 clk_hz = cm_get_per_vco_clk_hz();
1049 clk_hz /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
1050 CLKMGR_PERPLL_CNTRCLK_MSK);
1051 break;
1052
1053 case CLKMGR_PERPLLGRP_SRC_OSC1:
1054 clk_hz = eosc1_hz;
1055 break;
1056
1057 case CLKMGR_PERPLLGRP_SRC_INTOSC:
1058 clk_hz = cb_intosc_hz;
1059 break;
1060
1061 case CLKMGR_PERPLLGRP_SRC_FPGA:
1062 clk_hz = f2s_free_hz;
1063 break;
1064 }
1065
1066 return clk_hz / 4;
1067}
1068
1069unsigned int cm_get_spi_controller_clk_hz(void)
1070{
1071 return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB);
1072}
1073
1074unsigned int cm_get_qspi_controller_clk_hz(void)
1075{
1076 return cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB);
1077}
1078
1079void cm_print_clock_quick_summary(void)
1080{
1081 printf("MPU %10ld kHz\n", cm_get_mpu_clk_hz() / 1000);
1082 printf("MMC %8d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
1083 printf("QSPI %8d kHz\n", cm_get_qspi_controller_clk_hz() / 1000);
1084 printf("SPI %8d kHz\n", cm_get_spi_controller_clk_hz() / 1000);
1085 printf("EOSC1 %8d kHz\n", eosc1_hz / 1000);
1086 printf("cb_intosc %8d kHz\n", cb_intosc_hz / 1000);
1087 printf("f2s_free %8d kHz\n", f2s_free_hz / 1000);
1088 printf("Main VCO %8d kHz\n", cm_get_main_vco_clk_hz() / 1000);
1089 printf("NOC %8d kHz\n", cm_get_noc_clk_hz() / 1000);
1090 printf("L4 Main %8d kHz\n",
1091 cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MAINCLK_LSB) / 1000);
1092 printf("L4 MP %8d kHz\n",
1093 cm_get_l4_noc_hz(CLKMGR_MAINPLL_NOCDIV_L4MPCLK_LSB) / 1000);
1094 printf("L4 SP %8d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
1095 printf("L4 sys free %8d kHz\n", cm_l4_sys_free_clk_hz / 1000);
1096}
"Das U-Boot" Source Tree