[people/ms/u-boot.git] / arch / arm / mach-socfpga / qts-filter.sh

#!/bin/sh

#
# helper function to convert from DOS to Unix, if necessary, and handle
# lines ending in '\'.
#
fix_newlines_in_macros() {
	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
}

#
# Process iocsr_config_*.[ch]
# $1:	SoC type
# $2:	Input handoff directory
# $3:	Input BSP Generated directory
# $4:	Output directory
#
process_iocsr_config() {
	soc="$1"
	in_qts_dir="$2"
	in_bsp_dir="$3"
	out_dir="$4"

	(
	cat << EOF
/*
 * Altera SoCFPGA IOCSR configuration
 *
 * SPDX-License-Identifier:	BSD-3-Clause
 */

#ifndef __SOCFPGA_IOCSR_CONFIG_H__
#define __SOCFPGA_IOCSR_CONFIG_H__

EOF

	# Retrieve the scan chain lengths
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/iocsr_config_${soc}.h |
	grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH'	| tr -d "()"

	echo ""

	# Retrieve the scan chain config and zap the ad-hoc length encoding
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/iocsr_config_${soc}.c |
	sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'

	cat << EOF

#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
EOF
	) > "${out_dir}/iocsr_config.h"
}

#
# Process pinmux_config_*.c (and ignore pinmux_config.h)
# $1:	SoC type
# $2:	Input directory
# $3:	Output directory
#
process_pinmux_config() {
	soc="$1"
	in_qts_dir="$2"
	in_bsp_dir="$3"
	out_dir="$4"

	(
	cat << EOF
/*
 * Altera SoCFPGA PinMux configuration
 *
 * SPDX-License-Identifier:	BSD-3-Clause
 */

#ifndef __SOCFPGA_PINMUX_CONFIG_H__
#define __SOCFPGA_PINMUX_CONFIG_H__

EOF

	# Retrieve the pinmux config and zap the ad-hoc length encoding
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/pinmux_config_${soc}.c |
	sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'

	cat << EOF

#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
EOF
	) > "${out_dir}/pinmux_config.h"
}

#
# Process pll_config.h
# $1:	SoC type (not used)
# $2:	Input directory
# $3:	Output directory
#
process_pll_config() {
	soc="$1"
	in_qts_dir="$2"
	in_bsp_dir="$3"
	out_dir="$4"

	(
	cat << EOF
/*
 * Altera SoCFPGA Clock and PLL configuration
 *
 * SPDX-License-Identifier:	BSD-3-Clause
 */

#ifndef __SOCFPGA_PLL_CONFIG_H__
#define __SOCFPGA_PLL_CONFIG_H__

EOF

	# Retrieve the pll config and zap parenthesis
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/pll_config.h |
	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'

	cat << EOF

#endif /* __SOCFPGA_PLL_CONFIG_H__ */
EOF
	) > "${out_dir}/pll_config.h"
}

#
# Filter out only the macros which are actually used by the code
#
grep_sdram_config() {
	egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
}

#
# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
# $1:	SoC type (not used)
# $2:	Input directory
# $3:	Output directory
#
process_sdram_config() {
	soc="$1"
	in_qts_dir="$2"
	in_bsp_dir="$3"
	out_dir="$4"

	(
	cat << EOF
/*
 * Altera SoCFPGA SDRAM configuration
 *
 * SPDX-License-Identifier:	BSD-3-Clause
 */

#ifndef __SOCFPGA_SDRAM_CONFIG_H__
#define __SOCFPGA_SDRAM_CONFIG_H__

EOF

	echo "/* SDRAM configuration */"
	# Retrieve the sdram config, zap broken lines and zap parenthesis
	fix_newlines_in_macros \
		${in_bsp_dir}/generated/sdram/sdram_config.h |
	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
		sort -u | grep_sdram_config

	echo ""
	echo "/* Sequencer auto configuration */"
	fix_newlines_in_macros \
		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
	sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
		sort -u | grep_sdram_config

	echo ""
	echo "/* Sequencer defines configuration */"
	fix_newlines_in_macros \
		${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
	sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
		sort -u | grep_sdram_config

	echo ""
	echo "/* Sequencer ac_rom_init configuration */"
	fix_newlines_in_macros \
		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c |
	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'

	echo ""
	echo "/* Sequencer inst_rom_init configuration */"
	fix_newlines_in_macros \
		${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c |
	sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'

	cat << EOF

#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
EOF
	) > "${out_dir}/sdram_config.h"
}

usage() {
	echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
	echo "Process QTS-generated headers into U-Boot compatible ones."
	echo ""
	echo "  soc_type      - Type of SoC, either 'cyclone5' or 'arria5'."
	echo "  input_qts_dir - Directory with compiled Quartus project"
	echo "                  and containing the Quartus project file (QPF)."
	echo "  input_bsp_dir - Directory with generated bsp containing"
	echo "                  the settings.bsp file."
	echo "  output_dir    - Directory to store the U-Boot compatible"
	echo "                  headers."
	echo ""
}

soc="$1"
in_qts_dir="$2"
in_bsp_dir="$3"
out_dir="$4"

if [ "$#" -ne 4 ] ; then
	usage
	exit 1
fi

if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
	! -d "${out_dir}" -o -z "${soc}" ] ; then
	usage
	exit 3
fi

process_iocsr_config  "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
process_pll_config    "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
process_sdram_config  "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
Commit	Line	Data
e996b936 MV	1	#!/bin/sh
e996b936 MV	2
27211b60 BR	3	#
	4	# helper function to convert from DOS to Unix, if necessary, and handle
	5	# lines ending in '\'.
	6	#
	7	fix_newlines_in_macros() {
	8	sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
	9	}
	10
e996b936 MV	11	#
	12	# Process iocsr_config_*.[ch]
	13	# $1: SoC type
217db227 DW	14	# $2: Input handoff directory
	15	# $3: Input BSP Generated directory
	16	# $4: Output directory
e996b936 MV	17	#
	18	process_iocsr_config() {
	19	soc="$1"
217db227 DW	20	in_qts_dir="$2"
	21	in_bsp_dir="$3"
	22	out_dir="$4"
e996b936 MV	23
	24	(
	25	cat << EOF
	26	/*
	27	* Altera SoCFPGA IOCSR configuration
	28	*
	29	* SPDX-License-Identifier: BSD-3-Clause
	30	*/
	31
	32	#ifndef __SOCFPGA_IOCSR_CONFIG_H__
	33	#define __SOCFPGA_IOCSR_CONFIG_H__
	34
	35	EOF
	36
	37	# Retrieve the scan chain lengths
27211b60 BR	38	fix_newlines_in_macros \
	39	${in_bsp_dir}/generated/iocsr_config_${soc}.h \|
	40	grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' \| tr -d "()"
e996b936 MV	41
	42	echo ""
	43
	44	# Retrieve the scan chain config and zap the ad-hoc length encoding
27211b60 BR	45	fix_newlines_in_macros \
	46	${in_bsp_dir}/generated/iocsr_config_${soc}.c \|
	47	sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
e996b936 MV	48
	49	cat << EOF
	50
	51	#endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
	52	EOF
	53	) > "${out_dir}/iocsr_config.h"
	54	}
	55
	56	#
	57	# Process pinmux_config_*.c (and ignore pinmux_config.h)
	58	# $1: SoC type
	59	# $2: Input directory
	60	# $3: Output directory
	61	#
	62	process_pinmux_config() {
	63	soc="$1"
217db227 DW	64	in_qts_dir="$2"
	65	in_bsp_dir="$3"
	66	out_dir="$4"
e996b936 MV	67
	68	(
	69	cat << EOF
	70	/*
	71	* Altera SoCFPGA PinMux configuration
	72	*
	73	* SPDX-License-Identifier: BSD-3-Clause
	74	*/
	75
	76	#ifndef __SOCFPGA_PINMUX_CONFIG_H__
	77	#define __SOCFPGA_PINMUX_CONFIG_H__
	78
	79	EOF
	80
	81	# Retrieve the pinmux config and zap the ad-hoc length encoding
27211b60 BR	82	fix_newlines_in_macros \
	83	${in_bsp_dir}/generated/pinmux_config_${soc}.c \|
	84	sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'
e996b936 MV	85
	86	cat << EOF
	87
	88	#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
	89	EOF
	90	) > "${out_dir}/pinmux_config.h"
	91	}
	92
	93	#
	94	# Process pll_config.h
	95	# $1: SoC type (not used)
	96	# $2: Input directory
	97	# $3: Output directory
	98	#
	99	process_pll_config() {
	100	soc="$1"
217db227 DW	101	in_qts_dir="$2"
	102	in_bsp_dir="$3"
	103	out_dir="$4"
e996b936 MV	104
	105	(
	106	cat << EOF
	107	/*
	108	* Altera SoCFPGA Clock and PLL configuration
	109	*
	110	* SPDX-License-Identifier: BSD-3-Clause
	111	*/
	112
	113	#ifndef __SOCFPGA_PLL_CONFIG_H__
	114	#define __SOCFPGA_PLL_CONFIG_H__
	115
	116	EOF
	117
	118	# Retrieve the pll config and zap parenthesis
27211b60 BR	119	fix_newlines_in_macros \
	120	${in_bsp_dir}/generated/pll_config.h \|
	121	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
e996b936 MV	122
	123	cat << EOF
	124
	125	#endif /* __SOCFPGA_PLL_CONFIG_H__ */
	126	EOF
	127	) > "${out_dir}/pll_config.h"
	128	}
	129
	130	#
	131	# Filter out only the macros which are actually used by the code
	132	#
	133	grep_sdram_config() {
89a54abf	134	egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE\|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL\|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER\|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN\|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN\|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN\|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT\|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN\|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT\|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT\|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES\|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES\|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ\|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE\|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS\|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS\|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS\|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS\|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH\|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH\|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN\|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK\|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL\|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA\|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH\|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH\|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP\|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP\|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP\|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP\|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR\|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN\|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST\|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE\|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC\|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY\|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0\|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32\|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0\|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14\|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46\|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0\|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0\|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32\|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0\|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4\|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36\|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0\|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32\|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64\|RW_MGR_ACTIVATE_0_AND_1\|RW_MGR_ACTIVATE_0_AND_1_WAIT1\|RW_MGR_ACTIVATE_0_AND_1_WAIT2\|RW_MGR_ACTIVATE_1\|RW_MGR_CLEAR_DQS_ENABLE\|RW_MGR_GUARANTEED_READ\|RW_MGR_GUARANTEED_READ_CONT\|RW_MGR_GUARANTEED_WRITE\|RW_MGR_GUARANTEED_WRITE_WAIT0\|RW_MGR_GUARANTEED_WRITE_WAIT1\|RW_MGR_GUARANTEED_WRITE_WAIT2\|RW_MGR_GUARANTEED_WRITE_WAIT3\|RW_MGR_IDLE\|RW_MGR_IDLE_LOOP1\|RW_MGR_IDLE_LOOP2\|RW_MGR_INIT_RESET_0_CKE_0\|RW_MGR_INIT_RESET_1_CKE_0\|RW_MGR_LFSR_WR_RD_BANK_0\|RW_MGR_LFSR_WR_RD_BANK_0_DATA\|RW_MGR_LFSR_WR_RD_BANK_0_DQS\|RW_MGR_LFSR_WR_RD_BANK_0_NOP\|RW_MGR_LFSR_WR_RD_BANK_0_WAIT\|RW_MGR_LFSR_WR_RD_BANK_0_WL_1\|RW_MGR_LFSR_WR_RD_DM_BANK_0\|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA\|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS\|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP\|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT\|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1\|RW_MGR_MRS0_DLL_RESET\|RW_MGR_MRS0_DLL_RESET_MIRR\|RW_MGR_MRS0_USER\|RW_MGR_MRS0_USER_MIRR\|RW_MGR_MRS1\|RW_MGR_MRS1_MIRR\|RW_MGR_MRS2\|RW_MGR_MRS2_MIRR\|RW_MGR_MRS3\|RW_MGR_MRS3_MIRR\|RW_MGR_PRECHARGE_ALL\|RW_MGR_READ_B2B\|RW_MGR_READ_B2B_WAIT1\|RW_MGR_READ_B2B_WAIT2\|RW_MGR_REFRESH_ALL\|RW_MGR_RETURN\|RW_MGR_SGLE_READ\|RW_MGR_ZQCL\|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH\|RW_MGR_MEM_ADDRESS_MIRRORING\|RW_MGR_MEM_DATA_MASK_WIDTH\|RW_MGR_MEM_DATA_WIDTH\|RW_MGR_MEM_DQ_PER_READ_DQS\|RW_MGR_MEM_DQ_PER_WRITE_DQS\|RW_MGR_MEM_IF_READ_DQS_WIDTH\|RW_MGR_MEM_IF_WRITE_DQS_WIDTH\|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM\|RW_MGR_MEM_NUMBER_OF_RANKS\|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS\|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS\|IO_DELAY_PER_DCHAIN_TAP\|IO_DELAY_PER_DQS_EN_DCHAIN_TAP\|IO_DELAY_PER_OPA_TAP\|IO_DLL_CHAIN_LENGTH\|IO_DQDQS_OUT_PHASE_MAX\|IO_DQS_EN_DELAY_MAX\|IO_DQS_EN_DELAY_OFFSET\|IO_DQS_EN_PHASE_MAX\|IO_DQS_IN_DELAY_MAX\|IO_DQS_IN_RESERVE\|IO_DQS_OUT_RESERVE\|IO_IO_IN_DELAY_MAX\|IO_IO_OUT1_DELAY_MAX\|IO_IO_OUT2_DELAY_MAX\|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS\|AFI_RATE_RATIO\|CALIB_LFIFO_OFFSET\|CALIB_VFIFO_OFFSET\|ENABLE_SUPER_QUICK_CALIBRATION\|MAX_LATENCY_COUNT_WIDTH\|READ_VALID_FIFO_SIZE\|REG_FILE_INIT_SEQ_SIGNATURE\|TINIT_CNTR0_VAL\|TINIT_CNTR1_VAL\|TINIT_CNTR2_VAL\|TRESET_CNTR0_VAL\|TRESET_CNTR1_VAL\|TRESET_CNTR2_VAL\|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR\|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC\|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
e996b936 MV	135	}
	136
	137	#
	138	# Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
	139	# $1: SoC type (not used)
	140	# $2: Input directory
	141	# $3: Output directory
	142	#
	143	process_sdram_config() {
	144	soc="$1"
217db227 DW	145	in_qts_dir="$2"
	146	in_bsp_dir="$3"
	147	out_dir="$4"
e996b936 MV	148
	149	(
	150	cat << EOF
	151	/*
	152	* Altera SoCFPGA SDRAM configuration
	153	*
	154	* SPDX-License-Identifier: BSD-3-Clause
	155	*/
	156
	157	#ifndef __SOCFPGA_SDRAM_CONFIG_H__
	158	#define __SOCFPGA_SDRAM_CONFIG_H__
	159
	160	EOF
	161
	162	echo "/* SDRAM configuration */"
	163	# Retrieve the sdram config, zap broken lines and zap parenthesis
27211b60	164	fix_newlines_in_macros \
217db227	165	${in_bsp_dir}/generated/sdram/sdram_config.h \|
27211b60	166	sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" \|
e996b936 MV	167	sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' \|
	168	sort -u \| grep_sdram_config
	169
	170	echo ""
	171	echo "/* Sequencer auto configuration */"
27211b60	172	fix_newlines_in_macros \
217db227	173	${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h \|
27211b60	174	sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \|
217db227	175	sort -u \| grep_sdram_config
e996b936 MV	176
	177	echo ""
	178	echo "/* Sequencer defines configuration */"
27211b60	179	fix_newlines_in_macros \
217db227	180	${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h \|
27211b60	181	sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" \|
217db227	182	sort -u \| grep_sdram_config
e996b936 MV	183
	184	echo ""
	185	echo "/* Sequencer ac_rom_init configuration */"
27211b60 BR	186	fix_newlines_in_macros \
	187	${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c \|
	188	sed -n '/^const.\[/ !b; :next {/^const.\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
e996b936 MV	189
	190	echo ""
	191	echo "/* Sequencer inst_rom_init configuration */"
27211b60 BR	192	fix_newlines_in_macros \
	193	${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c \|
	194	sed -n '/^const.\[/ !b; :next {/^const.\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
e996b936 MV	195
	196	cat << EOF
	197
	198	#endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
	199	EOF
	200	) > "${out_dir}/sdram_config.h"
	201	}
	202
	203	usage() {
217db227	204	echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
e996b936 MV	205	echo "Process QTS-generated headers into U-Boot compatible ones."
e996b936 MV	206	echo ""
80da8664 MV	207	echo " soc_type - Type of SoC, either 'cyclone5' or 'arria5'."
	208	echo " input_qts_dir - Directory with compiled Quartus project"
	209	echo " and containing the Quartus project file (QPF)."
	210	echo " input_bsp_dir - Directory with generated bsp containing"
	211	echo " the settings.bsp file."
	212	echo " output_dir - Directory to store the U-Boot compatible"
	213	echo " headers."
e996b936 MV	214	echo ""
	215	}
	216
	217	soc="$1"
217db227 DW	218	in_qts_dir="$2"
	219	in_bsp_dir="$3"
	220	out_dir="$4"
e996b936	221
217db227	222	if [ "$#" -ne 4 ] ; then
e996b936 MV	223	usage
	224	exit 1
	225	fi
	226
217db227 DW	227	if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
217db227 DW	228	! -d "${out_dir}" -o -z "${soc}" ] ; then
e996b936 MV	229	usage
	230	exit 3
	231	fi
	232
217db227 DW	233	process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
	234	process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
	235	process_pll_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
	236	process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"