[people/ms/u-boot.git] / arch / arm / mach-socfpga / reset_manager.c

/*
 *  Copyright (C) 2013 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */


#include <common.h>
#include <asm/io.h>
#include <asm/arch/reset_manager.h>

DECLARE_GLOBAL_DATA_PTR;

static const struct socfpga_reset_manager *reset_manager_base =
		(void *)SOCFPGA_RSTMGR_ADDRESS;

/*
 * Write the reset manager register to cause reset
 */
void reset_cpu(ulong addr)
{
	/* request a warm reset */
	writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
	       &reset_manager_base->ctrl);
	/*
	 * infinite loop here as watchdog will trigger and reset
	 * the processor
	 */
	while (1)
		;
}
Commit	Line	Data
68e1747f CLS	1	/*
	2	* Copyright (C) 2013 Altera Corporation <www.altera.com>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7
	8	#include <common.h>
	9	#include <asm/io.h>
65d372c4	10	#include <asm/arch/reset_manager.h>
68e1747f CLS	11
	12	DECLARE_GLOBAL_DATA_PTR;
	13
	14	static const struct socfpga_reset_manager *reset_manager_base =
	15	(void *)SOCFPGA_RSTMGR_ADDRESS;
3191611a	16
68e1747f CLS	17	/*
	18	* Write the reset manager register to cause reset
	19	*/
	20	void reset_cpu(ulong addr)
	21	{
	22	/* request a warm reset */
2b09ea48 LFT	23	writel(1 << RSTMGR_CTRL_SWWARMRSTREQ_LSB,
2b09ea48 LFT	24	&reset_manager_base->ctrl);
68e1747f CLS	25	/*
	26	* infinite loop here as watchdog will trigger and reset
	27	* the processor
	28	*/
	29	while (1)
	30	;
	31	}