[people/ms/u-boot.git] / arch / arm / mach-socfpga / system_manager_gen5.c

/*
 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/system_manager.h>
#include <asm/arch/fpga_manager.h>

DECLARE_GLOBAL_DATA_PTR;

static struct socfpga_system_manager *sysmgr_regs =
	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

/*
 * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
 * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
 * CONFIG_SYSMGR_ISWGRP_HANDOFF.
 */
static void populate_sysmgr_fpgaintf_module(void)
{
	u32 handoff_val = 0;

	/* ISWGRP_HANDOFF_FPGAINTF */
	writel(0, &sysmgr_regs->iswgrp_handoff[2]);

	/* Enable the signal for those HPS peripherals that use FPGA. */
	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
		handoff_val |= SYSMGR_FPGAINTF_NAND;
	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
		handoff_val |= SYSMGR_FPGAINTF_EMAC1;
	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
		handoff_val |= SYSMGR_FPGAINTF_SDMMC;
	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
		handoff_val |= SYSMGR_FPGAINTF_EMAC0;
	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
		handoff_val |= SYSMGR_FPGAINTF_SPIM0;
	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
		handoff_val |= SYSMGR_FPGAINTF_SPIM1;

	/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
	based on pinmux setting */
	setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);

	handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
	if (fpgamgr_test_fpga_ready()) {
		/* Enable the required signals only */
		writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
	}
}

/*
 * Configure all the pin muxes
 */
void sysmgr_pinmux_init(void)
{
	u32 regs = (u32)&sysmgr_regs->emacio[0];
	const u8 *sys_mgr_init_table;
	unsigned int len;
	int i;

	sysmgr_get_pinmux_table(&sys_mgr_init_table, &len);

	for (i = 0; i < len; i++) {
		writel(sys_mgr_init_table[i], regs);
		regs += sizeof(regs);
	}

	populate_sysmgr_fpgaintf_module();
}

/*
 * This bit allows the bootrom to configure the IOs after a warm reset.
 */
void sysmgr_config_warmrstcfgio(int enable)
{
	if (enable)
		setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
			     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
	else
		clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
			     SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
}
Commit	Line	Data
5d649d2b	1	/*
4ddd541d	2	* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
5d649d2b CLS	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/system_manager.h>
665e4caf	10	#include <asm/arch/fpga_manager.h>
5d649d2b CLS	11
	12	DECLARE_GLOBAL_DATA_PTR;
	13
665e4caf MV	14	static struct socfpga_system_manager *sysmgr_regs =
	15	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
	16
807abb18 MV	17	/*
	18	* Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
	19	* The value is not wrote to SYSMGR.FPGAINTF.MODULE but
	20	* CONFIG_SYSMGR_ISWGRP_HANDOFF.
	21	*/
	22	static void populate_sysmgr_fpgaintf_module(void)
	23	{
4ddd541d	24	u32 handoff_val = 0;
807abb18 MV	25
	26	/* ISWGRP_HANDOFF_FPGAINTF */
	27	writel(0, &sysmgr_regs->iswgrp_handoff[2]);
	28
	29	/* Enable the signal for those HPS peripherals that use FPGA. */
	30	if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA)
	31	handoff_val \|= SYSMGR_FPGAINTF_NAND;
	32	if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
	33	handoff_val \|= SYSMGR_FPGAINTF_EMAC1;
	34	if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA)
	35	handoff_val \|= SYSMGR_FPGAINTF_SDMMC;
	36	if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
	37	handoff_val \|= SYSMGR_FPGAINTF_EMAC0;
	38	if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA)
	39	handoff_val \|= SYSMGR_FPGAINTF_SPIM0;
	40	if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA)
	41	handoff_val \|= SYSMGR_FPGAINTF_SPIM1;
	42
	43	/* populate (not writing) the value for SYSMGR.FPGAINTF.MODULE
	44	based on pinmux setting */
	45	setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val);
	46
	47	handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]);
	48	if (fpgamgr_test_fpga_ready()) {
	49	/* Enable the required signals only */
	50	writel(handoff_val, &sysmgr_regs->fpgaintfgrp_module);
	51	}
	52	}
	53
5d649d2b CLS	54	/*
	55	* Configure all the pin muxes
	56	*/
	57	void sysmgr_pinmux_init(void)
	58	{
4ddd541d	59	u32 regs = (u32)&sysmgr_regs->emacio[0];
cc9429a5	60	const u8 *sys_mgr_init_table;
2d779b39	61	unsigned int len;
665e4caf	62	int i;
5d649d2b	63
2d779b39 MV	64	sysmgr_get_pinmux_table(&sys_mgr_init_table, &len);
	65
	66	for (i = 0; i < len; i++) {
665e4caf MV	67	writel(sys_mgr_init_table[i], regs);
665e4caf MV	68	regs += sizeof(regs);
5d649d2b	69	}
807abb18 MV	70
807abb18 MV	71	populate_sysmgr_fpgaintf_module();
5d649d2b	72	}
08e463ee DN	73
	74	/*
	75	* This bit allows the bootrom to configure the IOs after a warm reset.
	76	*/
40687b4f	77	void sysmgr_config_warmrstcfgio(int enable)
08e463ee	78	{
40687b4f MV	79	if (enable)
	80	setbits_le32(&sysmgr_regs->romcodegrp_ctrl,
	81	SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
	82	else
	83	clrbits_le32(&sysmgr_regs->romcodegrp_ctrl,
	84	SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGIO);
08e463ee	85	}