[thirdparty/u-boot.git] / arch / arm / mach-stm32 / stm32f7 / clock.c

/*
 * (C) Copyright 2016
 * Vikas Manocha, <vikas.manocha@st.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/rcc.h>
#include <asm/arch/stm32.h>
#include <asm/arch/stm32_periph.h>

#define RCC_CR_HSION			BIT(0)
#define RCC_CR_HSEON			BIT(16)
#define RCC_CR_HSERDY			BIT(17)
#define RCC_CR_HSEBYP			BIT(18)
#define RCC_CR_CSSON			BIT(19)
#define RCC_CR_PLLON			BIT(24)
#define RCC_CR_PLLRDY			BIT(25)

#define RCC_PLLCFGR_PLLM_MASK		GENMASK(5, 0)
#define RCC_PLLCFGR_PLLN_MASK		GENMASK(14, 6)
#define RCC_PLLCFGR_PLLP_MASK		GENMASK(17, 16)
#define RCC_PLLCFGR_PLLQ_MASK		GENMASK(27, 24)
#define RCC_PLLCFGR_PLLSRC		BIT(22)
#define RCC_PLLCFGR_PLLM_SHIFT		0
#define RCC_PLLCFGR_PLLN_SHIFT		6
#define RCC_PLLCFGR_PLLP_SHIFT		16
#define RCC_PLLCFGR_PLLQ_SHIFT		24

#define RCC_CFGR_AHB_PSC_MASK		GENMASK(7, 4)
#define RCC_CFGR_APB1_PSC_MASK		GENMASK(12, 10)
#define RCC_CFGR_APB2_PSC_MASK		GENMASK(15, 13)
#define RCC_CFGR_SW0			BIT(0)
#define RCC_CFGR_SW1			BIT(1)
#define RCC_CFGR_SW_MASK		GENMASK(1, 0)
#define RCC_CFGR_SW_HSI			0
#define RCC_CFGR_SW_HSE			RCC_CFGR_SW0
#define RCC_CFGR_SW_PLL			RCC_CFGR_SW1
#define RCC_CFGR_SWS0			BIT(2)
#define RCC_CFGR_SWS1			BIT(3)
#define RCC_CFGR_SWS_MASK		GENMASK(3, 2)
#define RCC_CFGR_SWS_HSI		0
#define RCC_CFGR_SWS_HSE		RCC_CFGR_SWS0
#define RCC_CFGR_SWS_PLL		RCC_CFGR_SWS1
#define RCC_CFGR_HPRE_SHIFT		4
#define RCC_CFGR_PPRE1_SHIFT		10
#define RCC_CFGR_PPRE2_SHIFT		13

/*
 * Offsets of some PWR registers
 */
#define PWR_CR1_ODEN			BIT(16)
#define PWR_CR1_ODSWEN			BIT(17)
#define PWR_CSR1_ODRDY			BIT(16)
#define PWR_CSR1_ODSWRDY		BIT(17)

struct pll_psc {
	u8	pll_m;
	u16	pll_n;
	u8	pll_p;
	u8	pll_q;
	u8	ahb_psc;
	u8	apb1_psc;
	u8	apb2_psc;
};

#define AHB_PSC_1			0
#define AHB_PSC_2			0x8
#define AHB_PSC_4			0x9
#define AHB_PSC_8			0xA
#define AHB_PSC_16			0xB
#define AHB_PSC_64			0xC
#define AHB_PSC_128			0xD
#define AHB_PSC_256			0xE
#define AHB_PSC_512			0xF

#define APB_PSC_1			0
#define APB_PSC_2			0x4
#define APB_PSC_4			0x5
#define APB_PSC_8			0x6
#define APB_PSC_16			0x7

#if !defined(CONFIG_STM32_HSE_HZ)
#error "CONFIG_STM32_HSE_HZ not defined!"
#else
#if (CONFIG_STM32_HSE_HZ == 25000000)
#if (CONFIG_SYS_CLK_FREQ == 200000000)
/* 200 MHz */
struct pll_psc sys_pll_psc = {
	.pll_m = 25,
	.pll_n = 400,
	.pll_p = 2,
	.pll_q = 8,
	.ahb_psc = AHB_PSC_1,
	.apb1_psc = APB_PSC_4,
	.apb2_psc = APB_PSC_2
};
#endif
#else
#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
#endif
#endif

int configure_clocks(void)
{
	/* Reset RCC configuration */
	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON | RCC_CR_CSSON
		| RCC_CR_PLLON));
	writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
	writel(0, &STM32_RCC->cir); /* Disable all interrupts */

	/* Configure for HSE+PLL operation */
	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
		;

	setbits_le32(&STM32_RCC->cfgr, ((
		sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
		| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
		| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));

	/* Configure the main PLL */
	uint32_t pllcfgr = 0;
	pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
	pllcfgr |= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
	pllcfgr |= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
	pllcfgr |= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
	pllcfgr |= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
	writel(pllcfgr, &STM32_RCC->pllcfgr);

	/* Enable the main PLL */
	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
		;

	/* Enable high performance mode, System frequency up to 200 MHz */
	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
	/* Infinite wait! */
	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
		;
	/* Enable the Over-drive switch */
	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
	/* Infinite wait! */
	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
		;

	stm32_flash_latency_cfg(5);
	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);

	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
			RCC_CFGR_SWS_PLL)
		;

	return 0;
}

unsigned long clock_get(enum clock clck)
{
	u32 sysclk = 0;
	u32 shift = 0;
	/* Prescaler table lookups for clock computation */
	u8 ahb_psc_table[16] = {
		0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
	};
	u8 apb_psc_table[8] = {
		0, 0, 0, 0, 1, 2, 3, 4
	};

	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
			RCC_CFGR_SWS_PLL) {
		u16 pllm, plln, pllp;
		pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
		plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
			>> RCC_PLLCFGR_PLLN_SHIFT);
		pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
			>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
		sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
	}

	switch (clck) {
	case CLOCK_CORE:
		return sysclk;
		break;
	case CLOCK_AHB:
		shift = ahb_psc_table[(
			(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
			>> RCC_CFGR_HPRE_SHIFT)];
		return sysclk >>= shift;
		break;
	case CLOCK_APB1:
		shift = apb_psc_table[(
			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
			>> RCC_CFGR_PPRE1_SHIFT)];
		return sysclk >>= shift;
		break;
	case CLOCK_APB2:
		shift = apb_psc_table[(
			(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
			>> RCC_CFGR_PPRE2_SHIFT)];
		return sysclk >>= shift;
		break;
	default:
		return 0;
		break;
	}
}


void clock_setup(int peripheral)
{
	switch (peripheral) {
	case USART1_CLOCK_CFG:
		setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN);
		break;
	case GPIO_A_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN);
		break;
	case GPIO_B_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN);
		break;
	case GPIO_C_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN);
		break;
	case GPIO_D_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN);
		break;
	case GPIO_E_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN);
		break;
	case GPIO_F_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN);
		break;
	case GPIO_G_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN);
		break;
	case GPIO_H_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN);
		break;
	case GPIO_I_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN);
		break;
	case GPIO_J_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN);
		break;
	case GPIO_K_CLOCK_CFG:
		setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN);
		break;
	default:
		break;
	}
}
Commit	Line	Data
e66c49fa VM	1	/*
	2	* (C) Copyright 2016
	3	* Vikas Manocha, <vikas.manocha@st.com>
	4	*
	5	* SPDX-License-Identifier: GPL-2.0+
	6	*/
	7
	8	#include <common.h>
	9	#include <asm/io.h>
	10	#include <asm/arch/rcc.h>
	11	#include <asm/arch/stm32.h>
	12	#include <asm/arch/stm32_periph.h>
	13
bad5188b MK	14	#define RCC_CR_HSION BIT(0)
	15	#define RCC_CR_HSEON BIT(16)
	16	#define RCC_CR_HSERDY BIT(17)
	17	#define RCC_CR_HSEBYP BIT(18)
	18	#define RCC_CR_CSSON BIT(19)
	19	#define RCC_CR_PLLON BIT(24)
	20	#define RCC_CR_PLLRDY BIT(25)
ba0a3c16	21
bad5188b MK	22	#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
	23	#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
	24	#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
	25	#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
	26	#define RCC_PLLCFGR_PLLSRC BIT(22)
	27	#define RCC_PLLCFGR_PLLM_SHIFT 0
	28	#define RCC_PLLCFGR_PLLN_SHIFT 6
	29	#define RCC_PLLCFGR_PLLP_SHIFT 16
	30	#define RCC_PLLCFGR_PLLQ_SHIFT 24
ba0a3c16	31
bad5188b MK	32	#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
	33	#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
	34	#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
	35	#define RCC_CFGR_SW0 BIT(0)
	36	#define RCC_CFGR_SW1 BIT(1)
	37	#define RCC_CFGR_SW_MASK GENMASK(1, 0)
	38	#define RCC_CFGR_SW_HSI 0
	39	#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
	40	#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
	41	#define RCC_CFGR_SWS0 BIT(2)
	42	#define RCC_CFGR_SWS1 BIT(3)
	43	#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
	44	#define RCC_CFGR_SWS_HSI 0
	45	#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
	46	#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
	47	#define RCC_CFGR_HPRE_SHIFT 4
	48	#define RCC_CFGR_PPRE1_SHIFT 10
	49	#define RCC_CFGR_PPRE2_SHIFT 13
ba0a3c16 TN	50
	51	/*
	52	* Offsets of some PWR registers
	53	*/
bad5188b MK	54	#define PWR_CR1_ODEN BIT(16)
	55	#define PWR_CR1_ODSWEN BIT(17)
	56	#define PWR_CSR1_ODRDY BIT(16)
	57	#define PWR_CSR1_ODSWRDY BIT(17)
ba0a3c16 TN	58
	59	struct pll_psc {
	60	u8 pll_m;
	61	u16 pll_n;
	62	u8 pll_p;
	63	u8 pll_q;
	64	u8 ahb_psc;
	65	u8 apb1_psc;
	66	u8 apb2_psc;
	67	};
	68
bad5188b MK	69	#define AHB_PSC_1 0
	70	#define AHB_PSC_2 0x8
	71	#define AHB_PSC_4 0x9
	72	#define AHB_PSC_8 0xA
	73	#define AHB_PSC_16 0xB
	74	#define AHB_PSC_64 0xC
	75	#define AHB_PSC_128 0xD
	76	#define AHB_PSC_256 0xE
	77	#define AHB_PSC_512 0xF
ba0a3c16	78
bad5188b MK	79	#define APB_PSC_1 0
	80	#define APB_PSC_2 0x4
	81	#define APB_PSC_4 0x5
	82	#define APB_PSC_8 0x6
	83	#define APB_PSC_16 0x7
ba0a3c16 TN	84
	85	#if !defined(CONFIG_STM32_HSE_HZ)
	86	#error "CONFIG_STM32_HSE_HZ not defined!"
	87	#else
	88	#if (CONFIG_STM32_HSE_HZ == 25000000)
	89	#if (CONFIG_SYS_CLK_FREQ == 200000000)
	90	/* 200 MHz */
	91	struct pll_psc sys_pll_psc = {
	92	.pll_m = 25,
	93	.pll_n = 400,
	94	.pll_p = 2,
	95	.pll_q = 8,
	96	.ahb_psc = AHB_PSC_1,
	97	.apb1_psc = APB_PSC_4,
	98	.apb2_psc = APB_PSC_2
	99	};
	100	#endif
	101	#else
	102	#error "No PLL/Prescaler configuration for given CONFIG_STM32_HSE_HZ exists"
	103	#endif
	104	#endif
	105
	106	int configure_clocks(void)
	107	{
	108	/* Reset RCC configuration */
	109	setbits_le32(&STM32_RCC->cr, RCC_CR_HSION);
	110	writel(0, &STM32_RCC->cfgr); /* Reset CFGR */
	111	clrbits_le32(&STM32_RCC->cr, (RCC_CR_HSEON \| RCC_CR_CSSON
	112	\| RCC_CR_PLLON));
	113	writel(0x24003010, &STM32_RCC->pllcfgr); /* Reset value from RM */
	114	clrbits_le32(&STM32_RCC->cr, RCC_CR_HSEBYP);
	115	writel(0, &STM32_RCC->cir); /* Disable all interrupts */
	116
	117	/* Configure for HSE+PLL operation */
	118	setbits_le32(&STM32_RCC->cr, RCC_CR_HSEON);
	119	while (!(readl(&STM32_RCC->cr) & RCC_CR_HSERDY))
	120	;
	121
	122	setbits_le32(&STM32_RCC->cfgr, ((
	123	sys_pll_psc.ahb_psc << RCC_CFGR_HPRE_SHIFT)
	124	\| (sys_pll_psc.apb1_psc << RCC_CFGR_PPRE1_SHIFT)
	125	\| (sys_pll_psc.apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
	126
	127	/* Configure the main PLL */
	128	uint32_t pllcfgr = 0;
	129	pllcfgr = RCC_PLLCFGR_PLLSRC; /* pll source HSE */
	130	pllcfgr \|= sys_pll_psc.pll_m << RCC_PLLCFGR_PLLM_SHIFT;
	131	pllcfgr \|= sys_pll_psc.pll_n << RCC_PLLCFGR_PLLN_SHIFT;
	132	pllcfgr \|= ((sys_pll_psc.pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT;
	133	pllcfgr \|= sys_pll_psc.pll_q << RCC_PLLCFGR_PLLQ_SHIFT;
	134	writel(pllcfgr, &STM32_RCC->pllcfgr);
	135
	136	/* Enable the main PLL */
	137	setbits_le32(&STM32_RCC->cr, RCC_CR_PLLON);
	138	while (!(readl(&STM32_RCC->cr) & RCC_CR_PLLRDY))
	139	;
	140
	141	/* Enable high performance mode, System frequency up to 200 MHz */
	142	setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_PWREN);
	143	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODEN);
	144	/* Infinite wait! */
	145	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODRDY))
	146	;
	147	/* Enable the Over-drive switch */
148	setbits_le32(&STM32_PWR->cr1, PWR_CR1_ODSWEN);
149	/* Infinite wait! */
150	while (!(readl(&STM32_PWR->csr1) & PWR_CSR1_ODSWRDY))
151	;
152
153	stm32_flash_latency_cfg(5);
154	clrbits_le32(&STM32_RCC->cfgr, (RCC_CFGR_SW0 \| RCC_CFGR_SW1));
155	setbits_le32(&STM32_RCC->cfgr, RCC_CFGR_SW_PLL);
156
157	while ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) !=
158	RCC_CFGR_SWS_PLL)
159	;
160
161	return 0;
162	}
163
164	unsigned long clock_get(enum clock clck)
165	{
166	u32 sysclk = 0;
167	u32 shift = 0;
168	/* Prescaler table lookups for clock computation */
169	u8 ahb_psc_table[16] = {
170	0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
171	};
172	u8 apb_psc_table[8] = {
173	0, 0, 0, 0, 1, 2, 3, 4
174	};
175
176	if ((readl(&STM32_RCC->cfgr) & RCC_CFGR_SWS_MASK) ==
177	RCC_CFGR_SWS_PLL) {
178	u16 pllm, plln, pllp;
179	pllm = (readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
180	plln = ((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
181	>> RCC_PLLCFGR_PLLN_SHIFT);
182	pllp = ((((readl(&STM32_RCC->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
183	>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
184	sysclk = ((CONFIG_STM32_HSE_HZ / pllm) * plln) / pllp;
185	}
186
187	switch (clck) {
188	case CLOCK_CORE:
189	return sysclk;
190	break;
191	case CLOCK_AHB:
192	shift = ahb_psc_table[(
193	(readl(&STM32_RCC->cfgr) & RCC_CFGR_AHB_PSC_MASK)
194	>> RCC_CFGR_HPRE_SHIFT)];
195	return sysclk >>= shift;
196	break;
197	case CLOCK_APB1:
198	shift = apb_psc_table[(
199	(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB1_PSC_MASK)
200	>> RCC_CFGR_PPRE1_SHIFT)];
201	return sysclk >>= shift;
202	break;
203	case CLOCK_APB2:
204	shift = apb_psc_table[(
205	(readl(&STM32_RCC->cfgr) & RCC_CFGR_APB2_PSC_MASK)
206	>> RCC_CFGR_PPRE2_SHIFT)];
207	return sysclk >>= shift;
208	break;
209	default:
210	return 0;
211	break;
212	}
213	}
214
215
e66c49fa VM	216	void clock_setup(int peripheral)
	217	{
	218	switch (peripheral) {
	219	case USART1_CLOCK_CFG:
bad5188b	220	setbits_le32(&STM32_RCC->apb2enr, RCC_APB2ENR_USART1EN);
e66c49fa VM	221	break;
e66c49fa VM	222	case GPIO_A_CLOCK_CFG:
bad5188b	223	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_A_EN);
e66c49fa VM	224	break;
e66c49fa VM	225	case GPIO_B_CLOCK_CFG:
bad5188b	226	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_B_EN);
e66c49fa VM	227	break;
e66c49fa VM	228	case GPIO_C_CLOCK_CFG:
bad5188b	229	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_C_EN);
e66c49fa VM	230	break;
e66c49fa VM	231	case GPIO_D_CLOCK_CFG:
bad5188b	232	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_D_EN);
e66c49fa VM	233	break;
e66c49fa VM	234	case GPIO_E_CLOCK_CFG:
bad5188b	235	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_E_EN);
e66c49fa VM	236	break;
e66c49fa VM	237	case GPIO_F_CLOCK_CFG:
bad5188b	238	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_F_EN);
e66c49fa VM	239	break;
e66c49fa VM	240	case GPIO_G_CLOCK_CFG:
bad5188b	241	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_G_EN);
e66c49fa VM	242	break;
e66c49fa VM	243	case GPIO_H_CLOCK_CFG:
bad5188b	244	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_H_EN);
e66c49fa VM	245	break;
e66c49fa VM	246	case GPIO_I_CLOCK_CFG:
bad5188b	247	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_I_EN);
e66c49fa VM	248	break;
e66c49fa VM	249	case GPIO_J_CLOCK_CFG:
bad5188b	250	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_J_EN);
e66c49fa VM	251	break;
e66c49fa VM	252	case GPIO_K_CLOCK_CFG:
bad5188b	253	setbits_le32(&STM32_RCC->ahb1enr, RCC_AHB1ENR_GPIO_K_EN);
e66c49fa VM	254	break;
	255	default:
	256	break;
	257	}
	258	}