[thirdparty/u-boot.git] / arch / arm / mach-stm32mp / include / mach / sys_proto.h

/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
/*
 * Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
 */

/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */
#define CPU_STM32MP157Cxx	0x05000000
#define CPU_STM32MP157Axx	0x05000001
#define CPU_STM32MP153Cxx	0x05000024
#define CPU_STM32MP153Axx	0x05000025
#define CPU_STM32MP151Cxx	0x0500002E
#define CPU_STM32MP151Axx	0x0500002F
#define CPU_STM32MP157Fxx	0x05000080
#define CPU_STM32MP157Dxx	0x05000081
#define CPU_STM32MP153Fxx	0x050000A4
#define CPU_STM32MP153Dxx	0x050000A5
#define CPU_STM32MP151Fxx	0x050000AE
#define CPU_STM32MP151Dxx	0x050000AF

#define CPU_STM32MP135Cxx	0x05010000
#define CPU_STM32MP135Axx	0x05010001
#define CPU_STM32MP133Cxx	0x050100C0
#define CPU_STM32MP133Axx	0x050100C1
#define CPU_STM32MP131Cxx	0x050106C8
#define CPU_STM32MP131Axx	0x050106C9
#define CPU_STM32MP135Fxx	0x05010800
#define CPU_STM32MP135Dxx	0x05010801
#define CPU_STM32MP133Fxx	0x050108C0
#define CPU_STM32MP133Dxx	0x050108C1
#define CPU_STM32MP131Fxx	0x05010EC8
#define CPU_STM32MP131Dxx	0x05010EC9

/* return CPU_STMP32MP...Xxx constants */
u32 get_cpu_type(void);

#define CPU_DEV_STM32MP15	0x500
#define CPU_DEV_STM32MP13	0x501

/* return CPU_DEV constants */
u32 get_cpu_dev(void);

#define CPU_REV1	0x1000
#define CPU_REV1_1	0x1001
#define CPU_REV1_2	0x1003
#define CPU_REV2	0x2000
#define CPU_REV2_1	0x2001
#define CPU_REV2_2	0x2003

/* return Silicon revision = REV_ID[15:0] of Device Version */
u32 get_cpu_rev(void);

/* Get Package options from OTP */
u32 get_cpu_package(void);

/* package used for STM32MP15x */
#define STM32MP15_PKG_AA_LBGA448	4
#define STM32MP15_PKG_AB_LBGA354	3
#define STM32MP15_PKG_AC_TFBGA361	2
#define STM32MP15_PKG_AD_TFBGA257	1
#define STM32MP15_PKG_UNKNOWN		0

/* Get SOC name */
#define SOC_NAME_SIZE 20
void get_soc_name(char name[SOC_NAME_SIZE]);

/* return boot mode */
u32 get_bootmode(void);

/* return auth status and partition */
u32 get_bootauth(void);

int get_eth_nb(void);
int setup_mac_address(void);

/* board power management : configure vddcore according OPP */
void board_vddcore_init(u32 voltage_mv);

/* weak function */
void stm32mp_cpu_init(void);
void stm32mp_misc_init(void);

/* helper function: read data from OTP */
u32 get_otp(int index, int shift, int mask);

uintptr_t get_stm32mp_rom_api_table(void);
uintptr_t get_stm32mp_bl2_dtb(void);
Commit	Line	Data
4549e789	1	/* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
96583cdc PD	2	/*
96583cdc PD	3	* Copyright (C) 2015-2017, STMicroelectronics - All Rights Reserved
96583cdc PD	4	*/
96583cdc PD	5
960debbe	6	/* ID = Device Version (bit31:16) + Device Part Number (RPN) (bit15:0) */
35d568f0 PD	7	#define CPU_STM32MP157Cxx 0x05000000
	8	#define CPU_STM32MP157Axx 0x05000001
	9	#define CPU_STM32MP153Cxx 0x05000024
	10	#define CPU_STM32MP153Axx 0x05000025
	11	#define CPU_STM32MP151Cxx 0x0500002E
	12	#define CPU_STM32MP151Axx 0x0500002F
050fed8a PD	13	#define CPU_STM32MP157Fxx 0x05000080
	14	#define CPU_STM32MP157Dxx 0x05000081
	15	#define CPU_STM32MP153Fxx 0x050000A4
	16	#define CPU_STM32MP153Dxx 0x050000A5
	17	#define CPU_STM32MP151Fxx 0x050000AE
	18	#define CPU_STM32MP151Dxx 0x050000AF
96583cdc	19
960debbe PD	20	#define CPU_STM32MP135Cxx 0x05010000
	21	#define CPU_STM32MP135Axx 0x05010001
	22	#define CPU_STM32MP133Cxx 0x050100C0
	23	#define CPU_STM32MP133Axx 0x050100C1
	24	#define CPU_STM32MP131Cxx 0x050106C8
	25	#define CPU_STM32MP131Axx 0x050106C9
	26	#define CPU_STM32MP135Fxx 0x05010800
	27	#define CPU_STM32MP135Dxx 0x05010801
	28	#define CPU_STM32MP133Fxx 0x050108C0
	29	#define CPU_STM32MP133Dxx 0x050108C1
	30	#define CPU_STM32MP131Fxx 0x05010EC8
	31	#define CPU_STM32MP131Dxx 0x05010EC9
	32
35d568f0	33	/* return CPU_STMP32MP...Xxx constants */
96583cdc PD	34	u32 get_cpu_type(void);
96583cdc PD	35
7802a449	36	#define CPU_DEV_STM32MP15 0x500
960debbe	37	#define CPU_DEV_STM32MP13 0x501
7802a449 PD	38
	39	/* return CPU_DEV constants */
	40	u32 get_cpu_dev(void);
	41
655af9aa PD	42	#define CPU_REV1 0x1000
655af9aa PD	43	#define CPU_REV1_1 0x1001
50b371fd	44	#define CPU_REV1_2 0x1003
655af9aa PD	45	#define CPU_REV2 0x2000
655af9aa PD	46	#define CPU_REV2_1 0x2001
6bdef5b7	47	#define CPU_REV2_2 0x2003
96583cdc	48
655af9aa	49	/* return Silicon revision = REV_ID[15:0] of Device Version */
96583cdc	50	u32 get_cpu_rev(void);
24cb4587 PD	51
	52	/* Get Package options from OTP */
	53	u32 get_cpu_package(void);
	54
6df271a7 PD	55	/* package used for STM32MP15x */
	56	#define STM32MP15_PKG_AA_LBGA448 4
	57	#define STM32MP15_PKG_AB_LBGA354 3
	58	#define STM32MP15_PKG_AC_TFBGA361 2
	59	#define STM32MP15_PKG_AD_TFBGA257 1
	60	#define STM32MP15_PKG_UNKNOWN 0
24cb4587	61
ac5e4d8a PD	62	/* Get SOC name */
	63	#define SOC_NAME_SIZE 20
	64	void get_soc_name(char name[SOC_NAME_SIZE]);
	65
7f63c1e6 PD	66	/* return boot mode */
7f63c1e6 PD	67	u32 get_bootmode(void);
e71b9a64	68
c205fe97 IO	69	/* return auth status and partition */
	70	u32 get_bootauth(void);
	71
46f9eb5d	72	int get_eth_nb(void);
e71b9a64	73	int setup_mac_address(void);
4e62642a PD	74
	75	/* board power management : configure vddcore according OPP */
	76	void board_vddcore_init(u32 voltage_mv);
3865a7ec	77
6df271a7 PD	78	/* weak function */
	79	void stm32mp_cpu_init(void);
	80	void stm32mp_misc_init(void);
	81
3865a7ec PD	82	/* helper function: read data from OTP */
3865a7ec PD	83	u32 get_otp(int index, int shift, int mask);
dbeaca79 MV	84
	85	uintptr_t get_stm32mp_rom_api_table(void);
	86	uintptr_t get_stm32mp_bl2_dtb(void);