[thirdparty/u-boot.git] / arch / arm / mach-sunxi / board.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Some init for sunxi platform.
 */

#include <common.h>
#include <mmc.h>
#include <i2c.h>
#include <serial.h>
#include <spl.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/spl.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <asm/arch/tzpc.h>
#include <asm/arch/mmc.h>

#include <linux/compiler.h>

struct fel_stash {
	uint32_t sp;
	uint32_t lr;
	uint32_t cpsr;
	uint32_t sctlr;
	uint32_t vbar;
	uint32_t cr;
};

struct fel_stash fel_stash __attribute__((section(".data")));

#ifdef CONFIG_ARM64
#include <asm/armv8/mmu.h>

static struct mm_region sunxi_mem_map[] = {
	{
		/* SRAM, MMIO regions */
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x40000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE
	}, {
		/* RAM */
		.virt = 0x40000000UL,
		.phys = 0x40000000UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		/* List terminator */
		0,
	}
};
struct mm_region *mem_map = sunxi_mem_map;
#endif

static int gpio_init(void)
{
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || \
    defined(CONFIG_MACH_SUN7I) || \
    defined(CONFIG_MACH_SUN8I_R40)
	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
#endif
#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
#else
	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
#endif
	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
				 defined(CONFIG_MACH_SUN7I) || \
				 defined(CONFIG_MACH_SUN8I_R40))
	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif

	return 0;
}

#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
static int spl_board_load_image(struct spl_image_info *spl_image,
				struct spl_boot_device *bootdev)
{
	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	return_to_fel(fel_stash.sp, fel_stash.lr);

	return 0;
}
SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
#endif

void s_init(void)
{
	/*
	 * Undocumented magic taken from boot0, without this DRAM
	 * access gets messed up (seems cache related).
	 * The boot0 sources describe this as: "config ema for cache sram"
	 */
#if defined CONFIG_MACH_SUN6I
	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
#elif defined CONFIG_MACH_SUN8I
	__maybe_unused uint version;

	/* Unlock sram version info reg, read it, relock */
	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));

	/*
	 * Ideally this would be a switch case, but we do not know exactly
	 * which versions there are and which version needs which settings,
	 * so reproduce the per SoC code from the BSP.
	 */
#if defined CONFIG_MACH_SUN8I_A23
	if (version == 0x1650)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	else /* 0x1661 ? */
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#elif defined CONFIG_MACH_SUN8I_A33
	if (version != 0x1667)
		setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
#endif
	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
#endif

#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	asm volatile(
		"mrc p15, 0, r0, c1, c0, 1\n"
		"orr r0, r0, #1 << 6\n"
		"mcr p15, 0, r0, c1, c0, 1\n"
		::: "r0");
#endif
#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
	/* Enable non-secure access to some peripherals */
	tzpc_init();
#endif

	clock_init();
	timer_init();
	gpio_init();
#ifndef CONFIG_DM_I2C
	i2c_init_board();
#endif
	eth_init_board();
}

#ifdef CONFIG_SPL_BUILD
#endif

/* The sunxi internal brom will try to loader external bootloader
 * from mmc0, nand flash, mmc2.
 */
uint32_t sunxi_get_boot_device(void)
{
	int boot_source;

	/*
	 * When booting from the SD card or NAND memory, the "eGON.BT0"
	 * signature is expected to be found in memory at the address 0x0004
	 * (see the "mksunxiboot" tool, which generates this header).
	 *
	 * When booting in the FEL mode over USB, this signature is patched in
	 * memory and replaced with something else by the 'fel' tool. This other
	 * signature is selected in such a way, that it can't be present in a
	 * valid bootable SD card image (because the BROM would refuse to
	 * execute the SPL in this case).
	 *
	 * This checks for the signature and if it is not found returns to
	 * the FEL code in the BROM to wait and receive the main u-boot
	 * binary over USB. If it is found, it determines where SPL was
	 * read from.
	 */
	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
		return BOOT_DEVICE_BOARD;

	boot_source = readb(SPL_ADDR + 0x28);
	switch (boot_source) {
	case SUNXI_BOOTED_FROM_MMC0:
		return BOOT_DEVICE_MMC1;
	case SUNXI_BOOTED_FROM_NAND:
		return BOOT_DEVICE_NAND;
	case SUNXI_BOOTED_FROM_MMC2:
		return BOOT_DEVICE_MMC2;
	case SUNXI_BOOTED_FROM_SPI:
		return BOOT_DEVICE_SPI;
	}

	panic("Unknown boot source %d\n", boot_source);
	return -1;		/* Never reached */
}

#ifdef CONFIG_SPL_BUILD
u32 spl_boot_device(void)
{
	return sunxi_get_boot_device();
}

void board_init_f(ulong dummy)
{
	spl_init();
	preloader_console_init();

#ifdef CONFIG_SPL_I2C_SUPPORT
	/* Needed early by sunxi_board_init if PMU is enabled */
	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
#endif
	sunxi_board_init();
}
#endif

void reset_cpu(ulong addr)
{
#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
	static const struct sunxi_wdog *wdog =
		 &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);

	while (1) {
		/* sun5i sometimes gets stuck without this */
		writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
	}
#elif defined(CONFIG_SUNXI_GEN_SUN6I)
	static const struct sunxi_wdog *wdog =
		 ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;

	/* Set the watchdog for its shortest interval (.5s) and wait */
	writel(WDT_CFG_RESET, &wdog->cfg);
	writel(WDT_MODE_EN, &wdog->mode);
	writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
	while (1) { }
#endif
}

#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
void enable_caches(void)
{
	/* Enable D-cache. I-cache is already enabled in start.S */
	dcache_enable();
}
#endif
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
cba69eee IC	2	/*
	3	* (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	4	*
	5	* (C) Copyright 2007-2011
	6	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	7	* Tom Cubie <tangliang@allwinnertech.com>
	8	*
	9	* Some init for sunxi platform.
cba69eee IC	10	*/
	11
	12	#include <common.h>
a151403f	13	#include <mmc.h>
6620377e	14	#include <i2c.h>
cba69eee	15	#include <serial.h>
cba69eee	16	#include <spl.h>
cba69eee IC	17	#include <asm/gpio.h>
	18	#include <asm/io.h>
	19	#include <asm/arch/clock.h>
	20	#include <asm/arch/gpio.h>
af654d14	21	#include <asm/arch/spl.h>
cba69eee IC	22	#include <asm/arch/sys_proto.h>
cba69eee IC	23	#include <asm/arch/timer.h>
92369844	24	#include <asm/arch/tzpc.h>
a151403f	25	#include <asm/arch/mmc.h>
cba69eee	26
799aff38 IC	27	#include <linux/compiler.h>
799aff38 IC	28
942cb0b6 SG	29	struct fel_stash {
	30	uint32_t sp;
	31	uint32_t lr;
840fe95c SS	32	uint32_t cpsr;
	33	uint32_t sctlr;
	34	uint32_t vbar;
	35	uint32_t cr;
942cb0b6 SG	36	};
	37
	38	struct fel_stash fel_stash __attribute__((section(".data")));
	39
ce6912e1	40	#ifdef CONFIG_ARM64
d96ebc46 SS	41	#include <asm/armv8/mmu.h>
	42
	43	static struct mm_region sunxi_mem_map[] = {
	44	{
	45	/* SRAM, MMIO regions */
cd4b0c5f YS	46	.virt = 0x0UL,
cd4b0c5f YS	47	.phys = 0x0UL,
d96ebc46 SS	48	.size = 0x40000000UL,
	49	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	50	PTE_BLOCK_NON_SHARE
	51	}, {
	52	/* RAM */
cd4b0c5f YS	53	.virt = 0x40000000UL,
cd4b0c5f YS	54	.phys = 0x40000000UL,
d96ebc46 SS	55	.size = 0x80000000UL,
	56	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	57	PTE_BLOCK_INNER_SHARE
	58	}, {
	59	/* List terminator */
	60	0,
	61	}
	62	};
	63	struct mm_region *mem_map = sunxi_mem_map;
	64	#endif
	65
f630974c	66	static int gpio_init(void)
cba69eee	67	{
ff2b47f6	68	#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
379febac CYT	69	#if defined(CONFIG_MACH_SUN4I) \|\| \
	70	defined(CONFIG_MACH_SUN7I) \|\| \
	71	defined(CONFIG_MACH_SUN8I_R40)
ff2b47f6 CYT	72	/* disable GPB22,23 as uart0 tx,rx to avoid conflict */
	73	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
	74	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
	75	#endif
379febac	76	#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
6ad8c743 CYT	77	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
6ad8c743 CYT	78	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
487b3277	79	#else
6ad8c743 CYT	80	sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
6ad8c743 CYT	81	sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
487b3277	82	#endif
ff2b47f6	83	sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
379febac CYT	84	#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) \|\| \
	85	defined(CONFIG_MACH_SUN7I) \|\| \
	86	defined(CONFIG_MACH_SUN8I_R40))
487b3277 PK	87	sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
487b3277 PK	88	sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
ea520947	89	sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
ed41e62f	90	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	91	sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
487b3277 PK	92	sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
ea520947	93	sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
ed41e62f	94	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
487b3277 PK	95	sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
487b3277 PK	96	sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
77115397	97	sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
e506889c CYT	98	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
	99	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
	100	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
	101	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
7b82a229	102	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
1c27b7dc JK	103	sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
	104	sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
	105	sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
d96ebc46 SS	106	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
	107	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
	108	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
	109	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
d5a3357f	110	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
	111	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
	112	sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
	113	sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
c199489f IZ	114	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
	115	sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
	116	sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
	117	sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
1871a8ca HG	118	#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
	119	sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
	120	sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
	121	sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
ed41e62f	122	#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
487b3277 PK	123	sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
487b3277 PK	124	sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
ea520947	125	sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
5cd83b11 LI	126	#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
	127	sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
	128	sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
	129	sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
ed41e62f	130	#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
487b3277 PK	131	sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
487b3277 PK	132	sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
c757a50b	133	sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
f84269c5 HG	134	#else
	135	#error Unsupported console port number. Please fix pin mux settings in board.c
	136	#endif
cba69eee IC	137
	138	return 0;
	139	}
	140
eb77f5c9	141	#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
2a2ee2ac SG	142	static int spl_board_load_image(struct spl_image_info *spl_image,
2a2ee2ac SG	143	struct spl_boot_device *bootdev)
942cb0b6 SG	144	{
	145	debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
	146	return_to_fel(fel_stash.sp, fel_stash.lr);
36afd451 NK	147
36afd451 NK	148	return 0;
942cb0b6	149	}
ebc4ef61	150	SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
97d9df0a	151	#endif
942cb0b6	152
b56f6e2b	153	void s_init(void)
f630974c	154	{
583fede8 HG	155	/*
	156	* Undocumented magic taken from boot0, without this DRAM
	157	* access gets messed up (seems cache related).
	158	* The boot0 sources describe this as: "config ema for cache sram"
	159	*/
	160	#if defined CONFIG_MACH_SUN6I
f630974c	161	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
5f8afd70 HG	162	#elif defined CONFIG_MACH_SUN8I
5f8afd70 HG	163	__maybe_unused uint version;
583fede8 HG	164
	165	/* Unlock sram version info reg, read it, relock */
	166	setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
5f8afd70	167	version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
583fede8 HG	168	clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
583fede8 HG	169
5f8afd70 HG	170	/*
	171	* Ideally this would be a switch case, but we do not know exactly
	172	* which versions there are and which version needs which settings,
	173	* so reproduce the per SoC code from the BSP.
	174	*/
	175	#if defined CONFIG_MACH_SUN8I_A23
	176	if (version == 0x1650)
583fede8 HG	177	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
	178	else /* 0x1661 ? */
	179	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
5f8afd70 HG	180	#elif defined CONFIG_MACH_SUN8I_A33
	181	if (version != 0x1667)
	182	setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
	183	#endif
	184	/* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
	185	/* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
f630974c	186	#endif
583fede8	187
85db5831	188	#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
f630974c SG	189	/* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
	190	asm volatile(
	191	"mrc p15, 0, r0, c1, c0, 1\n"
	192	"orr r0, r0, #1 << 6\n"
1afd0f6f AP	193	"mcr p15, 0, r0, c1, c0, 1\n"
1afd0f6f AP	194	::: "r0");
f630974c	195	#endif
5823664f CYT	196	#if defined CONFIG_MACH_SUN6I \|\| defined CONFIG_MACH_SUN8I_H3
5823664f CYT	197	/* Enable non-secure access to some peripherals */
92369844 CYT	198	tzpc_init();
92369844 CYT	199	#endif
f630974c SG	200
	201	clock_init();
	202	timer_init();
	203	gpio_init();
a8f01ccf	204	#ifndef CONFIG_DM_I2C
f630974c	205	i2c_init_board();
a8f01ccf	206	#endif
fc8991c6	207	eth_init_board();
b56f6e2b	208	}
f630974c	209
b56f6e2b	210	#ifdef CONFIG_SPL_BUILD
8829076a	211	#endif
a151403f	212
b56f6e2b HG	213	/* The sunxi internal brom will try to loader external bootloader
b56f6e2b HG	214	* from mmc0, nand flash, mmc2.
b56f6e2b	215	*/
8829076a	216	uint32_t sunxi_get_boot_device(void)
b56f6e2b	217	{
ef36d9ae HG	218	int boot_source;
ef36d9ae HG	219
840fe95c	220	/*
a151403f DK	221	* When booting from the SD card or NAND memory, the "eGON.BT0"
	222	* signature is expected to be found in memory at the address 0x0004
	223	* (see the "mksunxiboot" tool, which generates this header).
840fe95c SS	224	*
	225	* When booting in the FEL mode over USB, this signature is patched in
	226	* memory and replaced with something else by the 'fel' tool. This other
	227	* signature is selected in such a way, that it can't be present in a
	228	* valid bootable SD card image (because the BROM would refuse to
	229	* execute the SPL in this case).
	230	*
a151403f DK	231	* This checks for the signature and if it is not found returns to
	232	* the FEL code in the BROM to wait and receive the main u-boot
	233	* binary over USB. If it is found, it determines where SPL was
	234	* read from.
840fe95c	235	*/
af654d14	236	if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
942cb0b6	237	return BOOT_DEVICE_BOARD;
a151403f	238
ef36d9ae HG	239	boot_source = readb(SPL_ADDR + 0x28);
	240	switch (boot_source) {
	241	case SUNXI_BOOTED_FROM_MMC0:
a151403f	242	return BOOT_DEVICE_MMC1;
ef36d9ae	243	case SUNXI_BOOTED_FROM_NAND:
a151403f	244	return BOOT_DEVICE_NAND;
ef36d9ae HG	245	case SUNXI_BOOTED_FROM_MMC2:
	246	return BOOT_DEVICE_MMC2;
	247	case SUNXI_BOOTED_FROM_SPI:
	248	return BOOT_DEVICE_SPI;
a151403f DK	249	}
a151403f DK	250
ef36d9ae	251	panic("Unknown boot source %d\n", boot_source);
a151403f	252	return -1; /* Never reached */
b56f6e2b HG	253	}
b56f6e2b HG	254
8829076a MR	255	#ifdef CONFIG_SPL_BUILD
	256	u32 spl_boot_device(void)
	257	{
	258	return sunxi_get_boot_device();
	259	}
	260
b56f6e2b HG	261	void board_init_f(ulong dummy)
b56f6e2b HG	262	{
6d0bdfdd	263	spl_init();
f630974c SG	264	preloader_console_init();
	265
	266	#ifdef CONFIG_SPL_I2C_SUPPORT
	267	/* Needed early by sunxi_board_init if PMU is enabled */
	268	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
	269	#endif
	270	sunxi_board_init();
f630974c SG	271	}
	272	#endif
	273
cba69eee IC	274	void reset_cpu(ulong addr)
cba69eee IC	275	{
6c7ae2bf	276	#if defined(CONFIG_SUNXI_GEN_SUN4I) \|\| defined(CONFIG_MACH_SUN8I_R40)
c7e79dec HG	277	static const struct sunxi_wdog *wdog =
	278	&((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	279
	280	/* Set the watchdog for its shortest interval (.5s) and wait */
	281	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	282	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
ae5de5a1 HG	283
	284	while (1) {
	285	/* sun5i sometimes gets stuck without this */
	286	writel(WDT_MODE_RESET_EN \| WDT_MODE_EN, &wdog->mode);
	287	}
6c7ae2bf	288	#elif defined(CONFIG_SUNXI_GEN_SUN6I)
78c396a1 CYT	289	static const struct sunxi_wdog *wdog =
	290	((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
	291
	292	/* Set the watchdog for its shortest interval (.5s) and wait */
	293	writel(WDT_CFG_RESET, &wdog->cfg);
	294	writel(WDT_MODE_EN, &wdog->mode);
	295	writel(WDT_CTRL_KEY \| WDT_CTRL_RESTART, &wdog->ctl);
fc175434	296	while (1) { }
78c396a1	297	#endif
cba69eee IC	298	}
cba69eee IC	299
d96ebc46	300	#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
cba69eee IC	301	void enable_caches(void)
	302	{
	303	/* Enable D-cache. I-cache is already enabled in start.S */
	304	dcache_enable();
	305	}
	306	#endif