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Commit | Line | Data |
---|---|---|
18138ab2 | 1 | if ARCH_TEGRA |
ddd960e6 | 2 | |
83061dbd | 3 | config SPL_GPIO |
53b5bf3c SG |
4 | default y |
5 | ||
77d2f7f5 SG |
6 | config SPL_LIBCOMMON_SUPPORT |
7 | default y | |
8 | ||
cc4288ef SG |
9 | config SPL_LIBGENERIC_SUPPORT |
10 | default y | |
11 | ||
2a736066 | 12 | config SPL_SERIAL |
e00f76ce SG |
13 | default y |
14 | ||
b64e0b92 TR |
15 | config TEGRA_CLKRST |
16 | bool | |
17 | ||
9e578192 TR |
18 | config TEGRA_GP_PADCTRL |
19 | bool | |
20 | ||
49626ea8 SW |
21 | config TEGRA_IVC |
22 | bool "Tegra IVC protocol" | |
23 | help | |
24 | IVC (Inter-VM Communication) protocol is a Tegra-specific IPC | |
25 | (Inter Processor Communication) framework. Within the context of | |
26 | U-Boot, it is typically used for communication between the main CPU | |
27 | and various auxiliary processors. | |
28 | ||
1a869c70 TR |
29 | config TEGRA_MC |
30 | bool | |
31 | ||
07ea02bc TR |
32 | config TEGRA_PINCTRL |
33 | bool | |
34 | ||
e19143b5 TR |
35 | config TEGRA_PMC |
36 | bool | |
37 | ||
f9ec2ec8 TR |
38 | config TEGRA_PMC_SECURE |
39 | bool | |
40 | depends on TEGRA_PMC | |
41 | ||
15bcc62d SW |
42 | config TEGRA_COMMON |
43 | bool "Tegra common options" | |
5ed063d1 | 44 | select BOARD_EARLY_INIT_F |
140a9eaf | 45 | select CLK |
56079ecc | 46 | select DM |
96350f72 | 47 | select DM_ETH |
56079ecc | 48 | select DM_GPIO |
15bcc62d | 49 | select DM_I2C |
f77f5e9b | 50 | select DM_KEYBOARD |
6a474db4 | 51 | select DM_MMC |
91c08afe | 52 | select DM_PWM |
140a9eaf | 53 | select DM_RESET |
15bcc62d SW |
54 | select DM_SERIAL |
55 | select DM_SPI | |
56 | select DM_SPI_FLASH | |
140a9eaf | 57 | select MISC |
15bcc62d | 58 | select OF_CONTROL |
5ed063d1 | 59 | select SPI |
08a00cba | 60 | imply CMD_DM |
221a949e | 61 | imply CRC32_VERIFY |
15bcc62d | 62 | |
140a9eaf SW |
63 | config TEGRA_NO_BPMP |
64 | bool "Tegra common options for SoCs without BPMP" | |
65 | select TEGRA_CAR | |
66 | select TEGRA_CAR_CLOCK | |
67 | select TEGRA_CAR_RESET | |
68 | ||
15bcc62d SW |
69 | config TEGRA_ARMV7_COMMON |
70 | bool "Tegra 32-bit common options" | |
3077026e | 71 | select BINMAN |
acf15001 | 72 | select CPU_V7A |
15bcc62d | 73 | select SPL |
0680f1b1 | 74 | select SPL_BOARD_INIT if SPL |
a2ac2b96 | 75 | select SPL_SKIP_LOWLEVEL_INIT_ONLY if SPL |
15bcc62d | 76 | select SUPPORT_SPL |
b64e0b92 | 77 | select TEGRA_CLKRST |
15bcc62d | 78 | select TEGRA_COMMON |
601800be | 79 | select TEGRA_GPIO |
9e578192 | 80 | select TEGRA_GP_PADCTRL |
1a869c70 | 81 | select TEGRA_MC |
140a9eaf | 82 | select TEGRA_NO_BPMP |
07ea02bc | 83 | select TEGRA_PINCTRL |
e19143b5 | 84 | select TEGRA_PMC |
15bcc62d SW |
85 | |
86 | config TEGRA_ARMV8_COMMON | |
87 | bool "Tegra 64-bit common options" | |
88 | select ARM64 | |
382de4a7 | 89 | select INIT_SP_RELATIVE |
ddecaaf3 | 90 | select LINUX_KERNEL_IMAGE_HEADER |
74a50ac2 | 91 | select POSITION_INDEPENDENT |
15bcc62d | 92 | select TEGRA_COMMON |
56079ecc | 93 | |
ddecaaf3 SW |
94 | if TEGRA_ARMV8_COMMON |
95 | config LNX_KRNL_IMG_TEXT_OFFSET_BASE | |
96 | default 0x80000000 | |
97 | endif | |
98 | ||
ddd960e6 MY |
99 | choice |
100 | prompt "Tegra SoC select" | |
a26cd049 | 101 | optional |
ddd960e6 MY |
102 | |
103 | config TEGRA20 | |
104 | bool "Tegra20 family" | |
8dda2e2f TR |
105 | select ARM_ERRATA_716044 |
106 | select ARM_ERRATA_742230 | |
107 | select ARM_ERRATA_751472 | |
56079ecc | 108 | select TEGRA_ARMV7_COMMON |
ddd960e6 MY |
109 | |
110 | config TEGRA30 | |
111 | bool "Tegra30 family" | |
8dda2e2f TR |
112 | select ARM_ERRATA_743622 |
113 | select ARM_ERRATA_751472 | |
56079ecc | 114 | select TEGRA_ARMV7_COMMON |
ddd960e6 MY |
115 | |
116 | config TEGRA114 | |
117 | bool "Tegra114 family" | |
56079ecc | 118 | select TEGRA_ARMV7_COMMON |
ddd960e6 MY |
119 | |
120 | config TEGRA124 | |
121 | bool "Tegra124 family" | |
56079ecc | 122 | select TEGRA_ARMV7_COMMON |
66de3eee SG |
123 | imply REGMAP |
124 | imply SYSCON | |
ddd960e6 | 125 | |
7aaa5a60 TW |
126 | config TEGRA210 |
127 | bool "Tegra210 family" | |
5afdcca0 | 128 | select GICV2 |
15bcc62d | 129 | select TEGRA_ARMV8_COMMON |
b64e0b92 | 130 | select TEGRA_CLKRST |
5ed063d1 | 131 | select TEGRA_GPIO |
9e578192 | 132 | select TEGRA_GP_PADCTRL |
1a869c70 | 133 | select TEGRA_MC |
140a9eaf | 134 | select TEGRA_NO_BPMP |
07ea02bc | 135 | select TEGRA_PINCTRL |
e19143b5 | 136 | select TEGRA_PMC |
f9ec2ec8 | 137 | select TEGRA_PMC_SECURE |
7aaa5a60 | 138 | |
c7ba99c8 SW |
139 | config TEGRA186 |
140 | bool "Tegra186 family" | |
0f67e239 | 141 | select DM_MAILBOX |
5afdcca0 | 142 | select GICV2 |
73dd5c4c | 143 | select TEGRA186_BPMP |
d9fd7008 | 144 | select TEGRA186_CLOCK |
c7ba99c8 | 145 | select TEGRA186_GPIO |
4dd99d14 | 146 | select TEGRA186_RESET |
c7ba99c8 | 147 | select TEGRA_ARMV8_COMMON |
0f67e239 | 148 | select TEGRA_HSP |
49626ea8 | 149 | select TEGRA_IVC |
c7ba99c8 | 150 | |
ddd960e6 MY |
151 | endchoice |
152 | ||
dd8204de SW |
153 | config TEGRA_DISCONNECT_UDC_ON_BOOT |
154 | bool "Disconnect USB device mode controller on boot" | |
836a56e7 | 155 | depends on CI_UDC |
dd8204de SW |
156 | default y |
157 | help | |
158 | When loading U-Boot into RAM over USB protocols using tools such as | |
159 | tegrarcm or L4T's exec-uboot.sh/tegraflash.py, Tegra's USB device | |
160 | mode controller is initialized and enumerated by the host PC running | |
161 | the tool. Unfortunately, these tools do not shut down the USB | |
162 | controller before executing the downloaded code, and so the host PC | |
163 | does not "de-enumerate" the USB device. This option shuts down the | |
164 | USB controller when U-Boot boots to avoid leaving a stale USB device | |
165 | present. | |
166 | ||
bd3ef278 TR |
167 | config CI_UDC_HAS_HOSTPC |
168 | def_bool y | |
169 | depends on CI_UDC && !TEGRA20 | |
170 | ||
b724bd7d SG |
171 | config SYS_MALLOC_F_LEN |
172 | default 0x1800 | |
173 | ||
09f455dc MY |
174 | source "arch/arm/mach-tegra/tegra20/Kconfig" |
175 | source "arch/arm/mach-tegra/tegra30/Kconfig" | |
176 | source "arch/arm/mach-tegra/tegra114/Kconfig" | |
177 | source "arch/arm/mach-tegra/tegra124/Kconfig" | |
7aaa5a60 | 178 | source "arch/arm/mach-tegra/tegra210/Kconfig" |
c7ba99c8 | 179 | source "arch/arm/mach-tegra/tegra186/Kconfig" |
ddd960e6 | 180 | |
42e6f852 SG |
181 | config CMD_ENTERRCM |
182 | bool "Enable 'enterrcm' command" | |
183 | default y | |
184 | help | |
185 | Tegra's boot ROM supports a mode whereby code may be downloaded and | |
186 | flash-programmed over a USB connection. On dev boards, this is | |
187 | typically entered by holding down a "force recovery" button and | |
188 | resetting the CPU. However, not all boards have such a button (one | |
189 | example is the Compulab Trimslice), so a method to enter RCM from | |
190 | software is useful. | |
191 | ||
192 | Even on boards other than Trimslice, controlling this over a UART | |
193 | may be useful, e.g. to allow simple remote control without the need | |
194 | for mechanical button actuators, or hooking up relays/... to the | |
195 | button. | |
196 | ||
ddd960e6 | 197 | endif |