[thirdparty/u-boot.git] / arch / arm / mach-tegra / arm64-mmu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 * (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
 *
 * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
 */

#include <common.h>
#include <asm/system.h>
#include <asm/armv8/mmu.h>

/* size: IO + NR_DRAM_BANKS + terminator */
struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
	{
		.virt = 0x0UL,
		.phys = 0x0UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
			 PTE_BLOCK_NON_SHARE |
			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
	}, {
		.virt = 0x80000000UL,
		.phys = 0x80000000UL,
		.size = 0x80000000UL,
		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
			 PTE_BLOCK_INNER_SHARE
	}, {
		/* List terminator */
		0,
	}
};

struct mm_region *mem_map = tegra_mem_map;
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
376cb1a4 SW	2	/*
	3	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	4	* Michal Simek <michal.simek@xilinx.com>
	5	* (This file derived from arch/arm/cpu/armv8/zynqmp/cpu.c)
	6	*
	7	* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
376cb1a4 SW	8	*/
	9
	10	#include <common.h>
	11	#include <asm/system.h>
	12	#include <asm/armv8/mmu.h>
	13
cdcf5558 SW	14	/* size: IO + NR_DRAM_BANKS + terminator */
cdcf5558 SW	15	struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
b30291a3	16	{
cd4b0c5f YS	17	.virt = 0x0UL,
cd4b0c5f YS	18	.phys = 0x0UL,
b30291a3 AG	19	.size = 0x80000000UL,
	20	.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) \|
	21	PTE_BLOCK_NON_SHARE \|
	22	PTE_BLOCK_PXN \| PTE_BLOCK_UXN
	23	}, {
cd4b0c5f YS	24	.virt = 0x80000000UL,
cd4b0c5f YS	25	.phys = 0x80000000UL,
d40d69ee	26	.size = 0x80000000UL,
b30291a3 AG	27	.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) \|
	28	PTE_BLOCK_INNER_SHARE
	29	}, {
	30	/* List terminator */
	31	0,
376cb1a4	32	}
b30291a3	33	};
376cb1a4	34
b30291a3	35	struct mm_region *mem_map = tegra_mem_map;