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3f82b1d3 TW |
1 | /* |
2 | * (C) Copyright 2010,2011 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
3f82b1d3 TW |
6 | */ |
7 | ||
8 | #include <common.h> | |
0521f984 | 9 | #include <dm.h> |
346451b5 | 10 | #include <errno.h> |
3f82b1d3 | 11 | #include <ns16550.h> |
c5b34a29 | 12 | #include <linux/compiler.h> |
3f82b1d3 | 13 | #include <asm/io.h> |
b4ba2be8 | 14 | #include <asm/arch/clock.h> |
6d6c0bae | 15 | #ifdef CONFIG_LCD |
1b24a50b | 16 | #include <asm/arch/display.h> |
6d6c0bae | 17 | #endif |
c0720afb | 18 | #include <asm/arch/funcmux.h> |
3f82b1d3 | 19 | #include <asm/arch/pinmux.h> |
8723626d | 20 | #include <asm/arch/pmu.h> |
6d6c0bae | 21 | #ifdef CONFIG_PWM_TEGRA |
e1ae0d1f | 22 | #include <asm/arch/pwm.h> |
6d6c0bae | 23 | #endif |
150c2493 | 24 | #include <asm/arch/tegra.h> |
73c38934 | 25 | #include <asm/arch-tegra/ap.h> |
150c2493 TW |
26 | #include <asm/arch-tegra/board.h> |
27 | #include <asm/arch-tegra/clk_rst.h> | |
28 | #include <asm/arch-tegra/pmc.h> | |
29 | #include <asm/arch-tegra/sys_proto.h> | |
30 | #include <asm/arch-tegra/uart.h> | |
31 | #include <asm/arch-tegra/warmboot.h> | |
6d6c0bae TW |
32 | #ifdef CONFIG_TEGRA_CLOCK_SCALING |
33 | #include <asm/arch/emc.h> | |
34 | #endif | |
35 | #ifdef CONFIG_USB_EHCI_TEGRA | |
7ae18f37 | 36 | #include <asm/arch-tegra/usb.h> |
16297cfb | 37 | #include <usb.h> |
6d6c0bae | 38 | #endif |
c9aa831e | 39 | #ifdef CONFIG_TEGRA_MMC |
190be1f9 | 40 | #include <asm/arch-tegra/tegra_mmc.h> |
c9aa831e TW |
41 | #include <asm/arch-tegra/mmc.h> |
42 | #endif | |
79c7a90f | 43 | #include <asm/arch-tegra/xusb-padctl.h> |
346451b5 | 44 | #include <power/as3722.h> |
cb445fb4 | 45 | #include <i2c.h> |
6d6c0bae | 46 | #include <spi.h> |
c5b34a29 | 47 | #include "emc.h" |
3f82b1d3 TW |
48 | |
49 | DECLARE_GLOBAL_DATA_PTR; | |
50 | ||
0521f984 SG |
51 | #ifdef CONFIG_SPL_BUILD |
52 | /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ | |
53 | U_BOOT_DEVICE(tegra_gpios) = { | |
54 | "gpio_tegra" | |
55 | }; | |
56 | #endif | |
57 | ||
19d7bf3d JH |
58 | __weak void pinmux_init(void) {} |
59 | __weak void pin_mux_usb(void) {} | |
60 | __weak void pin_mux_spi(void) {} | |
61 | __weak void gpio_early_init_uart(void) {} | |
62 | __weak void pin_mux_display(void) {} | |
0cd10c7a | 63 | |
dcd12518 | 64 | #if defined(CONFIG_TEGRA_NAND) |
19d7bf3d | 65 | __weak void pin_mux_nand(void) |
c0720afb LS |
66 | { |
67 | funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); | |
68 | } | |
dcd12518 | 69 | #endif |
c0720afb | 70 | |
5aff021c WN |
71 | /* |
72 | * Routine: power_det_init | |
73 | * Description: turn off power detects | |
74 | */ | |
75 | static void power_det_init(void) | |
76 | { | |
00a2749d | 77 | #if defined(CONFIG_TEGRA20) |
29f3e3f2 | 78 | struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
5aff021c WN |
79 | |
80 | /* turn off power detects */ | |
81 | writel(0, &pmc->pmc_pwr_det_latch); | |
82 | writel(0, &pmc->pmc_pwr_det); | |
83 | #endif | |
84 | } | |
85 | ||
ec746644 SG |
86 | __weak int tegra_board_id(void) |
87 | { | |
88 | return -1; | |
89 | } | |
90 | ||
7d874132 SG |
91 | #ifdef CONFIG_DISPLAY_BOARDINFO |
92 | int checkboard(void) | |
93 | { | |
ec746644 SG |
94 | int board_id = tegra_board_id(); |
95 | ||
96 | printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); | |
97 | if (board_id != -1) | |
98 | printf(", ID: %d\n", board_id); | |
99 | printf("\n"); | |
7d874132 SG |
100 | |
101 | return 0; | |
102 | } | |
103 | #endif /* CONFIG_DISPLAY_BOARDINFO */ | |
104 | ||
82776364 SG |
105 | __weak int tegra_lcd_pmic_init(int board_it) |
106 | { | |
107 | return 0; | |
108 | } | |
109 | ||
c96d709f SG |
110 | __weak int nvidia_board_init(void) |
111 | { | |
112 | return 0; | |
113 | } | |
114 | ||
3f82b1d3 TW |
115 | /* |
116 | * Routine: board_init | |
117 | * Description: Early hardware init. | |
118 | */ | |
119 | int board_init(void) | |
120 | { | |
c5b34a29 | 121 | __maybe_unused int err; |
82776364 | 122 | __maybe_unused int board_id; |
c5b34a29 | 123 | |
a04eba99 | 124 | /* Do clocks and UART first so that printf() works */ |
4ed59e70 SG |
125 | clock_init(); |
126 | clock_verify(); | |
127 | ||
fda6fac3 | 128 | #ifdef CONFIG_TEGRA_SPI |
e0284948 | 129 | pin_mux_spi(); |
e1ae0d1f | 130 | #endif |
b19f5749 | 131 | |
e1ae0d1f SG |
132 | #ifdef CONFIG_PWM_TEGRA |
133 | if (pwm_init(gd->fdt_blob)) | |
134 | debug("%s: Failed to init pwm\n", __func__); | |
1b24a50b SG |
135 | #endif |
136 | #ifdef CONFIG_LCD | |
716d9439 | 137 | pin_mux_display(); |
1b24a50b | 138 | tegra_lcd_check_next_stage(gd->fdt_blob, 0); |
9112ef8d | 139 | #endif |
3f82b1d3 TW |
140 | /* boot param addr */ |
141 | gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); | |
5aff021c WN |
142 | |
143 | power_det_init(); | |
144 | ||
1f2ba722 | 145 | #ifdef CONFIG_SYS_I2C_TEGRA |
8723626d SG |
146 | # ifdef CONFIG_TEGRA_PMU |
147 | if (pmu_set_nominal()) | |
148 | debug("Failed to select nominal voltages\n"); | |
c5b34a29 JZ |
149 | # ifdef CONFIG_TEGRA_CLOCK_SCALING |
150 | err = board_emc_init(); | |
151 | if (err) | |
152 | debug("Memory controller init failed: %d\n", err); | |
153 | # endif | |
154 | # endif /* CONFIG_TEGRA_PMU */ | |
346451b5 SG |
155 | #ifdef CONFIG_AS3722_POWER |
156 | err = as3722_init(NULL); | |
157 | if (err && err != -ENODEV) | |
158 | return err; | |
159 | #endif | |
1f2ba722 | 160 | #endif /* CONFIG_SYS_I2C_TEGRA */ |
3f82b1d3 | 161 | |
f10393e5 SG |
162 | #ifdef CONFIG_USB_EHCI_TEGRA |
163 | pin_mux_usb(); | |
f10393e5 | 164 | #endif |
16297cfb | 165 | |
1b24a50b | 166 | #ifdef CONFIG_LCD |
82776364 SG |
167 | board_id = tegra_board_id(); |
168 | err = tegra_lcd_pmic_init(board_id); | |
169 | if (err) | |
170 | return err; | |
1b24a50b SG |
171 | tegra_lcd_check_next_stage(gd->fdt_blob, 0); |
172 | #endif | |
f10393e5 | 173 | |
c0720afb LS |
174 | #ifdef CONFIG_TEGRA_NAND |
175 | pin_mux_nand(); | |
176 | #endif | |
177 | ||
79c7a90f TR |
178 | tegra_xusb_padctl_init(gd->fdt_blob); |
179 | ||
29f3e3f2 | 180 | #ifdef CONFIG_TEGRA_LP0 |
a49716aa AM |
181 | /* save Sdram params to PMC 2, 4, and 24 for WB0 */ |
182 | warmboot_save_sdram_params(); | |
183 | ||
67ac5797 SG |
184 | /* prepare the WB code to LP0 location */ |
185 | warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); | |
186 | #endif | |
c96d709f | 187 | return nvidia_board_init(); |
3f82b1d3 | 188 | } |
21ef6a10 | 189 | |
3e00dbdf | 190 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
cb7a1cf3 TR |
191 | static void __gpio_early_init(void) |
192 | { | |
193 | } | |
194 | ||
195 | void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); | |
196 | ||
3e00dbdf SG |
197 | int board_early_init_f(void) |
198 | { | |
6d6c0bae | 199 | pinmux_init(); |
f46a9456 | 200 | board_init_uart_f(); |
3e00dbdf SG |
201 | |
202 | /* Initialize periph GPIOs */ | |
cb7a1cf3 | 203 | gpio_early_init(); |
a04eba99 | 204 | gpio_early_init_uart(); |
1b24a50b SG |
205 | #ifdef CONFIG_LCD |
206 | tegra_lcd_early_init(gd->fdt_blob); | |
207 | #endif | |
0cd10c7a | 208 | |
3e00dbdf SG |
209 | return 0; |
210 | } | |
211 | #endif /* EARLY_INIT */ | |
1b24a50b SG |
212 | |
213 | int board_late_init(void) | |
214 | { | |
215 | #ifdef CONFIG_LCD | |
216 | /* Make sure we finish initing the LCD */ | |
217 | tegra_lcd_check_next_stage(gd->fdt_blob, 1); | |
73c38934 SW |
218 | #endif |
219 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) | |
220 | if (tegra_cpu_is_non_secure()) { | |
221 | printf("CPU is in NS mode\n"); | |
222 | setenv("cpu_ns_mode", "1"); | |
223 | } else { | |
224 | setenv("cpu_ns_mode", ""); | |
225 | } | |
1b24a50b SG |
226 | #endif |
227 | return 0; | |
228 | } | |
c9aa831e TW |
229 | |
230 | #if defined(CONFIG_TEGRA_MMC) | |
19d7bf3d | 231 | __weak void pin_mux_mmc(void) |
c9aa831e TW |
232 | { |
233 | } | |
234 | ||
c9aa831e TW |
235 | /* this is a weak define that we are overriding */ |
236 | int board_mmc_init(bd_t *bd) | |
237 | { | |
238 | debug("%s called\n", __func__); | |
239 | ||
240 | /* Enable muxes, etc. for SDMMC controllers */ | |
241 | pin_mux_mmc(); | |
242 | ||
243 | debug("%s: init MMC\n", __func__); | |
244 | tegra_mmc_init(); | |
245 | ||
246 | return 0; | |
247 | } | |
190be1f9 TW |
248 | |
249 | void pad_init_mmc(struct mmc_host *host) | |
250 | { | |
251 | #if defined(CONFIG_TEGRA30) | |
252 | enum periph_id id = host->mmc_id; | |
253 | u32 val; | |
254 | ||
255 | debug("%s: sdmmc address = %08x, id = %d\n", __func__, | |
256 | (unsigned int)host->reg, id); | |
257 | ||
258 | /* Set the pad drive strength for SDMMC1 or 3 only */ | |
259 | if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { | |
260 | debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", | |
261 | __func__); | |
262 | return; | |
263 | } | |
264 | ||
265 | val = readl(&host->reg->sdmemcmppadctl); | |
266 | val &= 0xFFFFFFF0; | |
267 | val |= MEMCOMP_PADCTRL_VREF; | |
268 | writel(val, &host->reg->sdmemcmppadctl); | |
269 | ||
270 | val = readl(&host->reg->autocalcfg); | |
271 | val &= 0xFFFF0000; | |
272 | val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; | |
273 | writel(val, &host->reg->autocalcfg); | |
274 | #endif /* T30 */ | |
275 | } | |
276 | #endif /* MMC */ |