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3f82b1d3 TW |
1 | /* |
2 | * (C) Copyright 2010,2011 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
3f82b1d3 TW |
6 | */ |
7 | ||
8 | #include <common.h> | |
0521f984 | 9 | #include <dm.h> |
346451b5 | 10 | #include <errno.h> |
3f82b1d3 | 11 | #include <ns16550.h> |
c5b34a29 | 12 | #include <linux/compiler.h> |
3f82b1d3 | 13 | #include <asm/io.h> |
b4ba2be8 | 14 | #include <asm/arch/clock.h> |
6d6c0bae | 15 | #ifdef CONFIG_LCD |
1b24a50b | 16 | #include <asm/arch/display.h> |
6d6c0bae | 17 | #endif |
c0720afb | 18 | #include <asm/arch/funcmux.h> |
3f82b1d3 | 19 | #include <asm/arch/pinmux.h> |
8723626d | 20 | #include <asm/arch/pmu.h> |
6d6c0bae | 21 | #ifdef CONFIG_PWM_TEGRA |
e1ae0d1f | 22 | #include <asm/arch/pwm.h> |
6d6c0bae | 23 | #endif |
150c2493 | 24 | #include <asm/arch/tegra.h> |
73c38934 | 25 | #include <asm/arch-tegra/ap.h> |
150c2493 TW |
26 | #include <asm/arch-tegra/board.h> |
27 | #include <asm/arch-tegra/clk_rst.h> | |
28 | #include <asm/arch-tegra/pmc.h> | |
29 | #include <asm/arch-tegra/sys_proto.h> | |
30 | #include <asm/arch-tegra/uart.h> | |
31 | #include <asm/arch-tegra/warmboot.h> | |
871d78ed | 32 | #include <asm/arch-tegra/gpu.h> |
6d6c0bae TW |
33 | #ifdef CONFIG_TEGRA_CLOCK_SCALING |
34 | #include <asm/arch/emc.h> | |
35 | #endif | |
36 | #ifdef CONFIG_USB_EHCI_TEGRA | |
7ae18f37 | 37 | #include <asm/arch-tegra/usb.h> |
16297cfb | 38 | #include <usb.h> |
6d6c0bae | 39 | #endif |
c9aa831e | 40 | #ifdef CONFIG_TEGRA_MMC |
190be1f9 | 41 | #include <asm/arch-tegra/tegra_mmc.h> |
c9aa831e TW |
42 | #include <asm/arch-tegra/mmc.h> |
43 | #endif | |
79c7a90f | 44 | #include <asm/arch-tegra/xusb-padctl.h> |
346451b5 | 45 | #include <power/as3722.h> |
cb445fb4 | 46 | #include <i2c.h> |
6d6c0bae | 47 | #include <spi.h> |
c5b34a29 | 48 | #include "emc.h" |
3f82b1d3 TW |
49 | |
50 | DECLARE_GLOBAL_DATA_PTR; | |
51 | ||
0521f984 SG |
52 | #ifdef CONFIG_SPL_BUILD |
53 | /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ | |
54 | U_BOOT_DEVICE(tegra_gpios) = { | |
55 | "gpio_tegra" | |
56 | }; | |
57 | #endif | |
58 | ||
19d7bf3d JH |
59 | __weak void pinmux_init(void) {} |
60 | __weak void pin_mux_usb(void) {} | |
61 | __weak void pin_mux_spi(void) {} | |
62 | __weak void gpio_early_init_uart(void) {} | |
63 | __weak void pin_mux_display(void) {} | |
66999892 | 64 | __weak void start_cpu_fan(void) {} |
0cd10c7a | 65 | |
dcd12518 | 66 | #if defined(CONFIG_TEGRA_NAND) |
19d7bf3d | 67 | __weak void pin_mux_nand(void) |
c0720afb LS |
68 | { |
69 | funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); | |
70 | } | |
dcd12518 | 71 | #endif |
c0720afb | 72 | |
5aff021c WN |
73 | /* |
74 | * Routine: power_det_init | |
75 | * Description: turn off power detects | |
76 | */ | |
77 | static void power_det_init(void) | |
78 | { | |
00a2749d | 79 | #if defined(CONFIG_TEGRA20) |
29f3e3f2 | 80 | struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
5aff021c WN |
81 | |
82 | /* turn off power detects */ | |
83 | writel(0, &pmc->pmc_pwr_det_latch); | |
84 | writel(0, &pmc->pmc_pwr_det); | |
85 | #endif | |
86 | } | |
87 | ||
ec746644 SG |
88 | __weak int tegra_board_id(void) |
89 | { | |
90 | return -1; | |
91 | } | |
92 | ||
7d874132 SG |
93 | #ifdef CONFIG_DISPLAY_BOARDINFO |
94 | int checkboard(void) | |
95 | { | |
ec746644 SG |
96 | int board_id = tegra_board_id(); |
97 | ||
98 | printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); | |
99 | if (board_id != -1) | |
100 | printf(", ID: %d\n", board_id); | |
101 | printf("\n"); | |
7d874132 SG |
102 | |
103 | return 0; | |
104 | } | |
105 | #endif /* CONFIG_DISPLAY_BOARDINFO */ | |
106 | ||
82776364 SG |
107 | __weak int tegra_lcd_pmic_init(int board_it) |
108 | { | |
109 | return 0; | |
110 | } | |
111 | ||
c96d709f SG |
112 | __weak int nvidia_board_init(void) |
113 | { | |
114 | return 0; | |
115 | } | |
116 | ||
3f82b1d3 TW |
117 | /* |
118 | * Routine: board_init | |
119 | * Description: Early hardware init. | |
120 | */ | |
121 | int board_init(void) | |
122 | { | |
c5b34a29 | 123 | __maybe_unused int err; |
82776364 | 124 | __maybe_unused int board_id; |
c5b34a29 | 125 | |
a04eba99 | 126 | /* Do clocks and UART first so that printf() works */ |
4ed59e70 SG |
127 | clock_init(); |
128 | clock_verify(); | |
129 | ||
871d78ed AC |
130 | config_gpu(); |
131 | ||
fda6fac3 | 132 | #ifdef CONFIG_TEGRA_SPI |
e0284948 | 133 | pin_mux_spi(); |
e1ae0d1f | 134 | #endif |
b19f5749 | 135 | |
e1ae0d1f SG |
136 | #ifdef CONFIG_PWM_TEGRA |
137 | if (pwm_init(gd->fdt_blob)) | |
138 | debug("%s: Failed to init pwm\n", __func__); | |
1b24a50b SG |
139 | #endif |
140 | #ifdef CONFIG_LCD | |
716d9439 | 141 | pin_mux_display(); |
1b24a50b | 142 | tegra_lcd_check_next_stage(gd->fdt_blob, 0); |
9112ef8d | 143 | #endif |
3f82b1d3 TW |
144 | /* boot param addr */ |
145 | gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); | |
5aff021c WN |
146 | |
147 | power_det_init(); | |
148 | ||
1f2ba722 | 149 | #ifdef CONFIG_SYS_I2C_TEGRA |
8723626d SG |
150 | # ifdef CONFIG_TEGRA_PMU |
151 | if (pmu_set_nominal()) | |
152 | debug("Failed to select nominal voltages\n"); | |
c5b34a29 JZ |
153 | # ifdef CONFIG_TEGRA_CLOCK_SCALING |
154 | err = board_emc_init(); | |
155 | if (err) | |
156 | debug("Memory controller init failed: %d\n", err); | |
157 | # endif | |
158 | # endif /* CONFIG_TEGRA_PMU */ | |
346451b5 SG |
159 | #ifdef CONFIG_AS3722_POWER |
160 | err = as3722_init(NULL); | |
161 | if (err && err != -ENODEV) | |
162 | return err; | |
163 | #endif | |
1f2ba722 | 164 | #endif /* CONFIG_SYS_I2C_TEGRA */ |
3f82b1d3 | 165 | |
f10393e5 SG |
166 | #ifdef CONFIG_USB_EHCI_TEGRA |
167 | pin_mux_usb(); | |
f10393e5 | 168 | #endif |
16297cfb | 169 | |
1b24a50b | 170 | #ifdef CONFIG_LCD |
82776364 SG |
171 | board_id = tegra_board_id(); |
172 | err = tegra_lcd_pmic_init(board_id); | |
173 | if (err) | |
174 | return err; | |
1b24a50b SG |
175 | tegra_lcd_check_next_stage(gd->fdt_blob, 0); |
176 | #endif | |
f10393e5 | 177 | |
c0720afb LS |
178 | #ifdef CONFIG_TEGRA_NAND |
179 | pin_mux_nand(); | |
180 | #endif | |
181 | ||
79c7a90f TR |
182 | tegra_xusb_padctl_init(gd->fdt_blob); |
183 | ||
29f3e3f2 | 184 | #ifdef CONFIG_TEGRA_LP0 |
a49716aa AM |
185 | /* save Sdram params to PMC 2, 4, and 24 for WB0 */ |
186 | warmboot_save_sdram_params(); | |
187 | ||
67ac5797 SG |
188 | /* prepare the WB code to LP0 location */ |
189 | warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); | |
190 | #endif | |
c96d709f | 191 | return nvidia_board_init(); |
3f82b1d3 | 192 | } |
21ef6a10 | 193 | |
3e00dbdf | 194 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
cb7a1cf3 TR |
195 | static void __gpio_early_init(void) |
196 | { | |
197 | } | |
198 | ||
199 | void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); | |
200 | ||
3e00dbdf SG |
201 | int board_early_init_f(void) |
202 | { | |
aa441877 TR |
203 | /* Do any special system timer/TSC setup */ |
204 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) | |
205 | if (!tegra_cpu_is_non_secure()) | |
206 | #endif | |
207 | arch_timer_init(); | |
208 | ||
6d6c0bae | 209 | pinmux_init(); |
f46a9456 | 210 | board_init_uart_f(); |
3e00dbdf SG |
211 | |
212 | /* Initialize periph GPIOs */ | |
cb7a1cf3 | 213 | gpio_early_init(); |
a04eba99 | 214 | gpio_early_init_uart(); |
1b24a50b SG |
215 | #ifdef CONFIG_LCD |
216 | tegra_lcd_early_init(gd->fdt_blob); | |
217 | #endif | |
0cd10c7a | 218 | |
3e00dbdf SG |
219 | return 0; |
220 | } | |
221 | #endif /* EARLY_INIT */ | |
1b24a50b SG |
222 | |
223 | int board_late_init(void) | |
224 | { | |
225 | #ifdef CONFIG_LCD | |
226 | /* Make sure we finish initing the LCD */ | |
227 | tegra_lcd_check_next_stage(gd->fdt_blob, 1); | |
73c38934 SW |
228 | #endif |
229 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) | |
230 | if (tegra_cpu_is_non_secure()) { | |
231 | printf("CPU is in NS mode\n"); | |
232 | setenv("cpu_ns_mode", "1"); | |
233 | } else { | |
234 | setenv("cpu_ns_mode", ""); | |
235 | } | |
1b24a50b | 236 | #endif |
66999892 TW |
237 | start_cpu_fan(); |
238 | ||
1b24a50b SG |
239 | return 0; |
240 | } | |
c9aa831e TW |
241 | |
242 | #if defined(CONFIG_TEGRA_MMC) | |
19d7bf3d | 243 | __weak void pin_mux_mmc(void) |
c9aa831e TW |
244 | { |
245 | } | |
246 | ||
c9aa831e TW |
247 | /* this is a weak define that we are overriding */ |
248 | int board_mmc_init(bd_t *bd) | |
249 | { | |
250 | debug("%s called\n", __func__); | |
251 | ||
252 | /* Enable muxes, etc. for SDMMC controllers */ | |
253 | pin_mux_mmc(); | |
254 | ||
255 | debug("%s: init MMC\n", __func__); | |
256 | tegra_mmc_init(); | |
257 | ||
258 | return 0; | |
259 | } | |
190be1f9 TW |
260 | |
261 | void pad_init_mmc(struct mmc_host *host) | |
262 | { | |
263 | #if defined(CONFIG_TEGRA30) | |
264 | enum periph_id id = host->mmc_id; | |
265 | u32 val; | |
266 | ||
267 | debug("%s: sdmmc address = %08x, id = %d\n", __func__, | |
268 | (unsigned int)host->reg, id); | |
269 | ||
270 | /* Set the pad drive strength for SDMMC1 or 3 only */ | |
271 | if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) { | |
272 | debug("%s: settings are only valid for SDMMC1/SDMMC3!\n", | |
273 | __func__); | |
274 | return; | |
275 | } | |
276 | ||
277 | val = readl(&host->reg->sdmemcmppadctl); | |
278 | val &= 0xFFFFFFF0; | |
279 | val |= MEMCOMP_PADCTRL_VREF; | |
280 | writel(val, &host->reg->sdmemcmppadctl); | |
281 | ||
282 | val = readl(&host->reg->autocalcfg); | |
283 | val &= 0xFFFF0000; | |
284 | val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED; | |
285 | writel(val, &host->reg->autocalcfg); | |
286 | #endif /* T30 */ | |
287 | } | |
288 | #endif /* MMC */ | |
00f782a9 TR |
289 | |
290 | #ifdef CONFIG_ARM64 | |
291 | /* | |
292 | * Most hardware on 64-bit Tegra is still restricted to DMA to the lower | |
293 | * 32-bits of the physical address space. Cap the maximum usable RAM area | |
294 | * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit | |
295 | * boundary that most devices can address. | |
424afc0a SW |
296 | * |
297 | * Additionally, ARM64 devices typically run a secure monitor in EL3 and | |
298 | * U-Boot in EL2, and set up some secure RAM carve-outs to contain the EL3 | |
299 | * code and data. These carve-outs are located at the top of 32-bit address | |
300 | * space. Restrict U-Boot's RAM usage to well below the location of those | |
301 | * carve-outs. Ideally, we would the secure monitor would inform U-Boot of | |
302 | * exactly which RAM it could use at run-time. However, I'm not sure how to | |
303 | * do that at present (and even if such a mechanism does exist, it would | |
304 | * likely not be generic across all forms of secure monitor). | |
00f782a9 TR |
305 | */ |
306 | ulong board_get_usable_ram_top(ulong total_size) | |
307 | { | |
424afc0a SW |
308 | if (gd->ram_top > 0xe0000000) |
309 | return 0xe0000000; | |
00f782a9 TR |
310 | |
311 | return gd->ram_top; | |
312 | } | |
313 | #endif |