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Commit | Line | Data |
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3f82b1d3 TW |
1 | /* |
2 | * (C) Copyright 2010,2011 | |
3 | * NVIDIA Corporation <www.nvidia.com> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
3f82b1d3 TW |
6 | */ |
7 | ||
8 | #include <common.h> | |
0521f984 | 9 | #include <dm.h> |
346451b5 | 10 | #include <errno.h> |
3f82b1d3 | 11 | #include <ns16550.h> |
03bc3f18 | 12 | #include <usb.h> |
3f82b1d3 | 13 | #include <asm/io.h> |
73c38934 | 14 | #include <asm/arch-tegra/ap.h> |
150c2493 TW |
15 | #include <asm/arch-tegra/board.h> |
16 | #include <asm/arch-tegra/clk_rst.h> | |
17 | #include <asm/arch-tegra/pmc.h> | |
18 | #include <asm/arch-tegra/sys_proto.h> | |
19 | #include <asm/arch-tegra/uart.h> | |
20 | #include <asm/arch-tegra/warmboot.h> | |
871d78ed | 21 | #include <asm/arch-tegra/gpu.h> |
03bc3f18 SG |
22 | #include <asm/arch-tegra/usb.h> |
23 | #include <asm/arch-tegra/xusb-padctl.h> | |
24 | #include <asm/arch/clock.h> | |
25 | #include <asm/arch/funcmux.h> | |
26 | #include <asm/arch/pinmux.h> | |
27 | #include <asm/arch/pmu.h> | |
28 | #include <asm/arch/tegra.h> | |
6d6c0bae TW |
29 | #ifdef CONFIG_TEGRA_CLOCK_SCALING |
30 | #include <asm/arch/emc.h> | |
31 | #endif | |
346451b5 | 32 | #include <power/as3722.h> |
c5b34a29 | 33 | #include "emc.h" |
3f82b1d3 TW |
34 | |
35 | DECLARE_GLOBAL_DATA_PTR; | |
36 | ||
0521f984 SG |
37 | #ifdef CONFIG_SPL_BUILD |
38 | /* TODO(sjg@chromium.org): Remove once SPL supports device tree */ | |
39 | U_BOOT_DEVICE(tegra_gpios) = { | |
40 | "gpio_tegra" | |
41 | }; | |
42 | #endif | |
43 | ||
19d7bf3d JH |
44 | __weak void pinmux_init(void) {} |
45 | __weak void pin_mux_usb(void) {} | |
46 | __weak void pin_mux_spi(void) {} | |
c0be77db | 47 | __weak void pin_mux_mmc(void) {} |
19d7bf3d JH |
48 | __weak void gpio_early_init_uart(void) {} |
49 | __weak void pin_mux_display(void) {} | |
66999892 | 50 | __weak void start_cpu_fan(void) {} |
0cd10c7a | 51 | |
dcd12518 | 52 | #if defined(CONFIG_TEGRA_NAND) |
19d7bf3d | 53 | __weak void pin_mux_nand(void) |
c0720afb LS |
54 | { |
55 | funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT); | |
56 | } | |
dcd12518 | 57 | #endif |
c0720afb | 58 | |
5aff021c WN |
59 | /* |
60 | * Routine: power_det_init | |
61 | * Description: turn off power detects | |
62 | */ | |
63 | static void power_det_init(void) | |
64 | { | |
00a2749d | 65 | #if defined(CONFIG_TEGRA20) |
29f3e3f2 | 66 | struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
5aff021c WN |
67 | |
68 | /* turn off power detects */ | |
69 | writel(0, &pmc->pmc_pwr_det_latch); | |
70 | writel(0, &pmc->pmc_pwr_det); | |
71 | #endif | |
72 | } | |
73 | ||
ec746644 SG |
74 | __weak int tegra_board_id(void) |
75 | { | |
76 | return -1; | |
77 | } | |
78 | ||
7d874132 SG |
79 | #ifdef CONFIG_DISPLAY_BOARDINFO |
80 | int checkboard(void) | |
81 | { | |
ec746644 SG |
82 | int board_id = tegra_board_id(); |
83 | ||
84 | printf("Board: %s", CONFIG_TEGRA_BOARD_STRING); | |
85 | if (board_id != -1) | |
86 | printf(", ID: %d\n", board_id); | |
87 | printf("\n"); | |
7d874132 SG |
88 | |
89 | return 0; | |
90 | } | |
91 | #endif /* CONFIG_DISPLAY_BOARDINFO */ | |
92 | ||
82776364 SG |
93 | __weak int tegra_lcd_pmic_init(int board_it) |
94 | { | |
95 | return 0; | |
96 | } | |
97 | ||
c96d709f SG |
98 | __weak int nvidia_board_init(void) |
99 | { | |
100 | return 0; | |
101 | } | |
102 | ||
3f82b1d3 TW |
103 | /* |
104 | * Routine: board_init | |
105 | * Description: Early hardware init. | |
106 | */ | |
107 | int board_init(void) | |
108 | { | |
c5b34a29 | 109 | __maybe_unused int err; |
82776364 | 110 | __maybe_unused int board_id; |
c5b34a29 | 111 | |
a04eba99 | 112 | /* Do clocks and UART first so that printf() works */ |
4ed59e70 SG |
113 | clock_init(); |
114 | clock_verify(); | |
115 | ||
eca676bd | 116 | tegra_gpu_config(); |
871d78ed | 117 | |
fda6fac3 | 118 | #ifdef CONFIG_TEGRA_SPI |
e0284948 | 119 | pin_mux_spi(); |
e1ae0d1f | 120 | #endif |
b19f5749 | 121 | |
1d2c0506 | 122 | #ifdef CONFIG_MMC_SDHCI_TEGRA |
c0be77db SW |
123 | pin_mux_mmc(); |
124 | #endif | |
125 | ||
3f2997a4 | 126 | /* Init is handled automatically in the driver-model case */ |
e007633b | 127 | #if defined(CONFIG_DM_VIDEO) |
716d9439 | 128 | pin_mux_display(); |
9112ef8d | 129 | #endif |
3f82b1d3 TW |
130 | /* boot param addr */ |
131 | gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100); | |
5aff021c WN |
132 | |
133 | power_det_init(); | |
134 | ||
1f2ba722 | 135 | #ifdef CONFIG_SYS_I2C_TEGRA |
8723626d SG |
136 | # ifdef CONFIG_TEGRA_PMU |
137 | if (pmu_set_nominal()) | |
138 | debug("Failed to select nominal voltages\n"); | |
c5b34a29 JZ |
139 | # ifdef CONFIG_TEGRA_CLOCK_SCALING |
140 | err = board_emc_init(); | |
141 | if (err) | |
142 | debug("Memory controller init failed: %d\n", err); | |
143 | # endif | |
144 | # endif /* CONFIG_TEGRA_PMU */ | |
56aceaf2 | 145 | #ifdef CONFIG_PMIC_AS3722 |
346451b5 SG |
146 | err = as3722_init(NULL); |
147 | if (err && err != -ENODEV) | |
148 | return err; | |
149 | #endif | |
1f2ba722 | 150 | #endif /* CONFIG_SYS_I2C_TEGRA */ |
3f82b1d3 | 151 | |
f10393e5 SG |
152 | #ifdef CONFIG_USB_EHCI_TEGRA |
153 | pin_mux_usb(); | |
f10393e5 | 154 | #endif |
16297cfb | 155 | |
e007633b | 156 | #if defined(CONFIG_DM_VIDEO) |
82776364 SG |
157 | board_id = tegra_board_id(); |
158 | err = tegra_lcd_pmic_init(board_id); | |
159 | if (err) | |
160 | return err; | |
135a87ef | 161 | #endif |
f10393e5 | 162 | |
c0720afb LS |
163 | #ifdef CONFIG_TEGRA_NAND |
164 | pin_mux_nand(); | |
165 | #endif | |
166 | ||
79c7a90f TR |
167 | tegra_xusb_padctl_init(gd->fdt_blob); |
168 | ||
29f3e3f2 | 169 | #ifdef CONFIG_TEGRA_LP0 |
a49716aa AM |
170 | /* save Sdram params to PMC 2, 4, and 24 for WB0 */ |
171 | warmboot_save_sdram_params(); | |
172 | ||
67ac5797 SG |
173 | /* prepare the WB code to LP0 location */ |
174 | warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE); | |
175 | #endif | |
c96d709f | 176 | return nvidia_board_init(); |
3f82b1d3 | 177 | } |
21ef6a10 | 178 | |
3e00dbdf | 179 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
cb7a1cf3 TR |
180 | static void __gpio_early_init(void) |
181 | { | |
182 | } | |
183 | ||
184 | void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init"))); | |
185 | ||
3e00dbdf SG |
186 | int board_early_init_f(void) |
187 | { | |
46864cc8 SG |
188 | if (!clock_early_init_done()) |
189 | clock_early_init(); | |
190 | ||
dd8204de SW |
191 | #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT) |
192 | #define USBCMD_FS2 (1 << 15) | |
193 | { | |
194 | struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000; | |
195 | writel(USBCMD_FS2, &usbctlr->usb_cmd); | |
196 | } | |
197 | #endif | |
198 | ||
aa441877 TR |
199 | /* Do any special system timer/TSC setup */ |
200 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) | |
201 | if (!tegra_cpu_is_non_secure()) | |
202 | #endif | |
203 | arch_timer_init(); | |
204 | ||
6d6c0bae | 205 | pinmux_init(); |
f46a9456 | 206 | board_init_uart_f(); |
3e00dbdf SG |
207 | |
208 | /* Initialize periph GPIOs */ | |
cb7a1cf3 | 209 | gpio_early_init(); |
a04eba99 | 210 | gpio_early_init_uart(); |
0cd10c7a | 211 | |
3e00dbdf SG |
212 | return 0; |
213 | } | |
214 | #endif /* EARLY_INIT */ | |
1b24a50b SG |
215 | |
216 | int board_late_init(void) | |
217 | { | |
73c38934 SW |
218 | #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE) |
219 | if (tegra_cpu_is_non_secure()) { | |
220 | printf("CPU is in NS mode\n"); | |
221 | setenv("cpu_ns_mode", "1"); | |
222 | } else { | |
223 | setenv("cpu_ns_mode", ""); | |
224 | } | |
1b24a50b | 225 | #endif |
66999892 TW |
226 | start_cpu_fan(); |
227 | ||
1b24a50b SG |
228 | return 0; |
229 | } | |
c9aa831e | 230 | |
bbc1b99e SW |
231 | /* |
232 | * In some SW environments, a memory carve-out exists to house a secure | |
233 | * monitor, a trusted OS, and/or various statically allocated media buffers. | |
234 | * | |
235 | * This carveout exists at the highest possible address that is within a | |
236 | * 32-bit physical address space. | |
237 | * | |
238 | * This function returns the total size of this carve-out. At present, the | |
239 | * returned value is hard-coded for simplicity. In the future, it may be | |
240 | * possible to determine the carve-out size: | |
241 | * - By querying some run-time information source, such as: | |
242 | * - A structure passed to U-Boot by earlier boot software. | |
243 | * - SoC registers. | |
244 | * - A call into the secure monitor. | |
245 | * - In the per-board U-Boot configuration header, based on knowledge of the | |
246 | * SW environment that U-Boot is being built for. | |
247 | * | |
248 | * For now, we support two configurations in U-Boot: | |
249 | * - 32-bit ports without any form of carve-out. | |
250 | * - 64 bit ports which are assumed to use a carve-out of a conservatively | |
251 | * hard-coded size. | |
252 | */ | |
253 | static ulong carveout_size(void) | |
254 | { | |
00f782a9 | 255 | #ifdef CONFIG_ARM64 |
bbc1b99e SW |
256 | return SZ_512M; |
257 | #else | |
258 | return 0; | |
259 | #endif | |
260 | } | |
261 | ||
262 | /* | |
263 | * Determine the amount of usable RAM below 4GiB, taking into account any | |
264 | * carve-out that may be assigned. | |
265 | */ | |
266 | static ulong usable_ram_size_below_4g(void) | |
267 | { | |
268 | ulong total_size_below_4g; | |
269 | ulong usable_size_below_4g; | |
270 | ||
271 | /* | |
272 | * The total size of RAM below 4GiB is the lesser address of: | |
273 | * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB). | |
274 | * (b) The size RAM physically present in the system. | |
275 | */ | |
276 | if (gd->ram_size < SZ_2G) | |
277 | total_size_below_4g = gd->ram_size; | |
278 | else | |
279 | total_size_below_4g = SZ_2G; | |
280 | ||
281 | /* Calculate usable RAM by subtracting out any carve-out size */ | |
282 | usable_size_below_4g = total_size_below_4g - carveout_size(); | |
283 | ||
284 | return usable_size_below_4g; | |
285 | } | |
286 | ||
287 | /* | |
288 | * Represent all available RAM in either one or two banks. | |
289 | * | |
290 | * The first bank describes any usable RAM below 4GiB. | |
291 | * The second bank describes any RAM above 4GiB. | |
292 | * | |
293 | * This split is driven by the following requirements: | |
294 | * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg | |
295 | * property for memory below and above the 4GiB boundary. The layout of that | |
296 | * DT property is directly driven by the entries in the U-Boot bank array. | |
297 | * - The potential existence of a carve-out at the end of RAM below 4GiB can | |
298 | * only be represented using multiple banks. | |
299 | * | |
300 | * Explicitly removing the carve-out RAM from the bank entries makes the RAM | |
301 | * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot | |
302 | * command-line. | |
303 | * | |
304 | * This does mean that the DT U-Boot passes to the Linux kernel will not | |
305 | * include this RAM in /memory/reg at all. An alternative would be to include | |
306 | * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node | |
307 | * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the | |
308 | * Linux kernel will ever need to access any RAM in* the carve-out via a CPU | |
309 | * mapping, so either way is acceptable. | |
310 | * | |
311 | * On 32-bit systems, we never define a bank for RAM above 4GiB, since the | |
312 | * start address of that bank cannot be represented in the 32-bit .size | |
313 | * field. | |
314 | */ | |
76b00aca | 315 | int dram_init_banksize(void) |
bbc1b99e SW |
316 | { |
317 | gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; | |
318 | gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); | |
319 | ||
e81ca884 SG |
320 | #ifdef CONFIG_PCI |
321 | gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; | |
322 | #endif | |
323 | ||
bbc1b99e SW |
324 | #ifdef CONFIG_PHYS_64BIT |
325 | if (gd->ram_size > SZ_2G) { | |
326 | gd->bd->bi_dram[1].start = 0x100000000; | |
327 | gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G; | |
328 | } else | |
329 | #endif | |
330 | { | |
331 | gd->bd->bi_dram[1].start = 0; | |
332 | gd->bd->bi_dram[1].size = 0; | |
333 | } | |
76b00aca SG |
334 | |
335 | return 0; | |
bbc1b99e SW |
336 | } |
337 | ||
00f782a9 TR |
338 | /* |
339 | * Most hardware on 64-bit Tegra is still restricted to DMA to the lower | |
340 | * 32-bits of the physical address space. Cap the maximum usable RAM area | |
341 | * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit | |
bbc1b99e SW |
342 | * boundary that most devices can address. Also, don't let U-Boot use any |
343 | * carve-out, as mentioned above. | |
424afc0a | 344 | * |
bbc1b99e SW |
345 | * This function is called before dram_init_banksize(), so we can't simply |
346 | * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size. | |
00f782a9 TR |
347 | */ |
348 | ulong board_get_usable_ram_top(ulong total_size) | |
349 | { | |
bbc1b99e | 350 | return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); |
00f782a9 | 351 | } |