[thirdparty/u-boot.git] / arch / arm / mach-tegra / tegra114 / cpu.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * (C) Copyright 2010-2014
 * NVIDIA Corporation <www.nvidia.com>
 */

#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/flow.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include <asm/arch-tegra/pmc.h>
#include "../cpu.h"

/* Tegra114-specific CPU init code */
static void enable_cpu_power_rail(void)
{
	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 reg;

	debug("%s entry\n", __func__);

	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);

	/*
	 * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
	 * set it for 25ms (102MHz * .025)
	 */
	reg = 0x26E8F0;
	writel(reg, &pmc->pmc_cpupwrgood_timer);

	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);

	/*
	 * Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
	 * to 408 to satisfy the requirement of having at least 16 CPU clock
	 * cycles before clamp removal.
	 */

	clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
	setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
}

static void enable_cpu_clocks(void)
{
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
	u32 reg;

	debug("%s entry\n", __func__);

	/* Wait for PLL-X to lock */
	do {
		reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
	} while ((reg & (1 << pllinfo->lock_det)) == 0);

	/* Wait until all clocks are stable */
	udelay(PLL_STABILIZATION_DELAY);

	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);

	/* Always enable the main CPU complex clocks */
	clock_enable(PERIPH_ID_CPU);
	clock_enable(PERIPH_ID_CPULP);
	clock_enable(PERIPH_ID_CPUG);
}

static void remove_cpu_resets(void)
{
	struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	u32 reg;

	debug("%s entry\n", __func__);
	/* Take the slow non-CPU partition out of reset */
	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);

	/* Take the fast non-CPU partition out of reset */
	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
	writel((reg | CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);

	/* Clear the SW-controlled reset of the slow cluster */
	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);

	/* Clear the SW-controlled reset of the fast cluster */
	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
	reg |= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
	reg |= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
	reg |= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
	reg |= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
}

/**
 * Tegra114 requires some special clock initialization, including setting up
 * the DVC I2C, turning on MSELECT and selecting the G CPU cluster
 */
void t114_init_clocks(void)
{
	struct clk_rst_ctlr *clkrst =
			(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	struct flow_ctlr *flow = (struct flow_ctlr *)NV_PA_FLOW_BASE;
	u32 val;

	debug("%s entry\n", __func__);

	/* Set active CPU cluster to G */
	clrbits_le32(&flow->cluster_control, 1);

	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);

	debug("Setting up PLLX\n");
	init_pllx();

	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
	writel(val, &clkrst->crc_clk_sys_rate);

	/* Enable clocks to required peripherals. TBD - minimize this list */
	debug("Enabling clocks\n");

	clock_set_enable(PERIPH_ID_CACHE2, 1);
	clock_set_enable(PERIPH_ID_GPIO, 1);
	clock_set_enable(PERIPH_ID_TMR, 1);
	clock_set_enable(PERIPH_ID_RTC, 1);
	clock_set_enable(PERIPH_ID_CPU, 1);
	clock_set_enable(PERIPH_ID_EMC, 1);
	clock_set_enable(PERIPH_ID_I2C5, 1);
	clock_set_enable(PERIPH_ID_FUSE, 1);
	clock_set_enable(PERIPH_ID_PMC, 1);
	clock_set_enable(PERIPH_ID_APBDMA, 1);
	clock_set_enable(PERIPH_ID_MEM, 1);
	clock_set_enable(PERIPH_ID_IRAMA, 1);
	clock_set_enable(PERIPH_ID_IRAMB, 1);
	clock_set_enable(PERIPH_ID_IRAMC, 1);
	clock_set_enable(PERIPH_ID_IRAMD, 1);
	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
	clock_set_enable(PERIPH_ID_MSELECT, 1);
	clock_set_enable(PERIPH_ID_EMC1, 1);
	clock_set_enable(PERIPH_ID_MC1, 1);
	clock_set_enable(PERIPH_ID_DVFS, 1);

	/*
	 * Set MSELECT clock source as PLLP (00), and ask for a clock
	 * divider that would set the MSELECT clock at 102MHz for a
	 * PLLP base of 408MHz.
	 */
	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
		CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));

	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);

	/* Give clocks time to stabilize */
	udelay(1000);

	/* Take required peripherals out of reset */
	debug("Taking periphs out of reset\n");
	reset_set_enable(PERIPH_ID_CACHE2, 0);
	reset_set_enable(PERIPH_ID_GPIO, 0);
	reset_set_enable(PERIPH_ID_TMR, 0);
	reset_set_enable(PERIPH_ID_COP, 0);
	reset_set_enable(PERIPH_ID_EMC, 0);
	reset_set_enable(PERIPH_ID_I2C5, 0);
	reset_set_enable(PERIPH_ID_FUSE, 0);
	reset_set_enable(PERIPH_ID_APBDMA, 0);
	reset_set_enable(PERIPH_ID_MEM, 0);
	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
	reset_set_enable(PERIPH_ID_MSELECT, 0);
	reset_set_enable(PERIPH_ID_EMC1, 0);
	reset_set_enable(PERIPH_ID_MC1, 0);
	reset_set_enable(PERIPH_ID_DVFS, 0);

	debug("%s exit\n", __func__);
}

static bool is_partition_powered(u32 partid)
{
	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
	u32 reg;

	/* Get power gate status */
	reg = readl(&pmc->pmc_pwrgate_status);
	return !!(reg & (1 << partid));
}

static bool is_clamp_enabled(u32 partid)
{
	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
	u32 reg;

	/* Get clamp status. */
	reg = readl(&pmc->pmc_clamp_status);
	return !!(reg & (1 << partid));
}

static void power_partition(u32 partid)
{
	struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;

	debug("%s: part ID = %08X\n", __func__, partid);
	/* Is the partition already on? */
	if (!is_partition_powered(partid)) {
		/* No, toggle the partition power state (OFF -> ON) */
		debug("power_partition, toggling state\n");
		writel(START_CP | partid, &pmc->pmc_pwrgate_toggle);

		/* Wait for the power to come up */
		while (!is_partition_powered(partid))
			;

		/* Wait for the clamp status to be cleared */
		while (is_clamp_enabled(partid))
			;

		/* Give I/O signals time to stabilize */
		udelay(IO_STABILIZATION_DELAY);
	}
}

void powerup_cpus(void)
{
	/* We boot to the fast cluster */
	debug("%s entry: G cluster\n", __func__);

	/* Power up the fast cluster rail partition */
	power_partition(CRAIL);

	/* Power up the fast cluster non-CPU partition */
	power_partition(C0NC);

	/* Power up the fast cluster CPU0 partition */
	power_partition(CE0);
}

void start_cpu(u32 reset_vector)
{
	u32 imme, inst;

	debug("%s entry, reset_vector = %x\n", __func__, reset_vector);

	t114_init_clocks();

	/* Enable VDD_CPU */
	enable_cpu_power_rail();

	/* Get the CPU(s) running */
	enable_cpu_clocks();

	/* Enable CoreSight */
	clock_enable_coresight(1);

	/* Take CPU(s) out of reset */
	remove_cpu_resets();

	/* Set the entry point for CPU execution from reset */

	/*
	 * A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
	 * See nvbug 1193357 for details.
	 */

	/* mov r0, #lsb(reset_vector) */
	imme = reset_vector & 0xffff;
	inst = imme & 0xfff;
	inst |= ((imme >> 12) << 16);
	inst |= 0xe3000000;
	writel(inst, 0x4003fff0);

	/* movt r0, #msb(reset_vector) */
	imme = (reset_vector >> 16) & 0xffff;
	inst = imme & 0xfff;
	inst |= ((imme >> 12) << 16);
	inst |= 0xe3400000;
	writel(inst, 0x4003fff4);

	/* bx r0 */
	writel(0xe12fff10, 0x4003fff8);

	/* b -12 */
	imme = (u32)-20;
	inst = (imme >> 2) & 0xffffff;
	inst |= 0xea000000;
	writel(inst, 0x4003fffc);

	/* Write to original location for compatibility */
	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);

	/* If the CPU(s) don't already have power, power 'em up */
	powerup_cpus();
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
4040ec10	2	/*
722e000c TW	3	* (C) Copyright 2010-2014
722e000c TW	4	* NVIDIA Corporation <www.nvidia.com>
4040ec10 TW	5	*/
	6
	7	#include <common.h>
	8	#include <asm/io.h>
	9	#include <asm/arch/clock.h>
	10	#include <asm/arch/flow.h>
	11	#include <asm/arch/pinmux.h>
	12	#include <asm/arch/tegra.h>
	13	#include <asm/arch-tegra/clk_rst.h>
	14	#include <asm/arch-tegra/pmc.h>
09f455dc	15	#include "../cpu.h"
4040ec10 TW	16
	17	/* Tegra114-specific CPU init code */
	18	static void enable_cpu_power_rail(void)
	19	{
	20	struct pmc_ctlr pmc = (struct pmc_ctlr )NV_PA_PMC_BASE;
	21	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
	22	u32 reg;
	23
722e000c	24	debug("%s entry\n", __func__);
4040ec10 TW	25
4040ec10 TW	26	/* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */
1fa3a634 SW	27	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6);
1fa3a634 SW	28	pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7);
4040ec10 TW	29
	30	/*
	31	* Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz),
	32	* set it for 25ms (102MHz * .025)
	33	*/
	34	reg = 0x26E8F0;
	35	writel(reg, &pmc->pmc_cpupwrgood_timer);
	36
	37	/* Set polarity to 0 (normal) and enable CPUPWRREQ_OE */
	38	clrbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_POL);
	39	setbits_le32(&pmc->pmc_cntrl, CPUPWRREQ_OE);
	40
	41	/*
	42	* Set CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2_0_CAR2PMC_CPU_ACK_WIDTH
	43	* to 408 to satisfy the requirement of having at least 16 CPU clock
	44	* cycles before clamp removal.
	45	*/
	46
	47	clrbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 0xFFF);
	48	setbits_le32(&clkrst->crc_cpu_softrst_ctrl2, 408);
	49	}
	50
	51	static void enable_cpu_clocks(void)
	52	{
	53	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
722e000c	54	struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
4040ec10 TW	55	u32 reg;
4040ec10 TW	56
722e000c	57	debug("%s entry\n", __func__);
4040ec10 TW	58
	59	/* Wait for PLL-X to lock */
	60	do {
	61	reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base);
722e000c	62	} while ((reg & (1 << pllinfo->lock_det)) == 0);
4040ec10 TW	63
	64	/* Wait until all clocks are stable */
	65	udelay(PLL_STABILIZATION_DELAY);
	66
	67	writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
	68	writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
	69
	70	/* Always enable the main CPU complex clocks */
	71	clock_enable(PERIPH_ID_CPU);
	72	clock_enable(PERIPH_ID_CPULP);
	73	clock_enable(PERIPH_ID_CPUG);
	74	}
	75
	76	static void remove_cpu_resets(void)
	77	{
	78	struct clk_rst_ctlr clkrst = (struct clk_rst_ctlr )NV_PA_CLK_RST_BASE;
	79	u32 reg;
	80
722e000c	81	debug("%s entry\n", __func__);
4040ec10 TW	82	/* Take the slow non-CPU partition out of reset */
	83	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
	84	writel((reg \| CLR_NONCPURESET), &clkrst->crc_rst_cpulp_cmplx_clr);
	85
	86	/* Take the fast non-CPU partition out of reset */
	87	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
	88	writel((reg \| CLR_NONCPURESET), &clkrst->crc_rst_cpug_cmplx_clr);
	89
	90	/* Clear the SW-controlled reset of the slow cluster */
	91	reg = readl(&clkrst->crc_rst_cpulp_cmplx_clr);
	92	reg \|= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
	93	writel(reg, &clkrst->crc_rst_cpulp_cmplx_clr);
	94
	95	/* Clear the SW-controlled reset of the fast cluster */
	96	reg = readl(&clkrst->crc_rst_cpug_cmplx_clr);
	97	reg \|= (CLR_CPURESET0+CLR_DBGRESET0+CLR_CORERESET0+CLR_CXRESET0);
	98	reg \|= (CLR_CPURESET1+CLR_DBGRESET1+CLR_CORERESET1+CLR_CXRESET1);
	99	reg \|= (CLR_CPURESET2+CLR_DBGRESET2+CLR_CORERESET2+CLR_CXRESET2);
	100	reg \|= (CLR_CPURESET3+CLR_DBGRESET3+CLR_CORERESET3+CLR_CXRESET3);
	101	writel(reg, &clkrst->crc_rst_cpug_cmplx_clr);
	102	}
	103
	104	/**
722e000c	105	* Tegra114 requires some special clock initialization, including setting up
4040ec10 TW	106	* the DVC I2C, turning on MSELECT and selecting the G CPU cluster
	107	*/
	108	void t114_init_clocks(void)
	109	{
	110	struct clk_rst_ctlr *clkrst =
	111	(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
	112	struct flow_ctlr flow = (struct flow_ctlr )NV_PA_FLOW_BASE;
	113	u32 val;
	114
722e000c	115	debug("%s entry\n", __func__);
4040ec10 TW	116
	117	/* Set active CPU cluster to G */
	118	clrbits_le32(&flow->cluster_control, 1);
	119
4040ec10 TW	120	writel(SUPER_SCLK_ENB_MASK, &clkrst->crc_super_sclk_div);
	121
	122	debug("Setting up PLLX\n");
	123	init_pllx();
	124
	125	val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT);
	126	writel(val, &clkrst->crc_clk_sys_rate);
	127
	128	/* Enable clocks to required peripherals. TBD - minimize this list */
	129	debug("Enabling clocks\n");
	130
	131	clock_set_enable(PERIPH_ID_CACHE2, 1);
	132	clock_set_enable(PERIPH_ID_GPIO, 1);
	133	clock_set_enable(PERIPH_ID_TMR, 1);
	134	clock_set_enable(PERIPH_ID_RTC, 1);
	135	clock_set_enable(PERIPH_ID_CPU, 1);
	136	clock_set_enable(PERIPH_ID_EMC, 1);
	137	clock_set_enable(PERIPH_ID_I2C5, 1);
	138	clock_set_enable(PERIPH_ID_FUSE, 1);
	139	clock_set_enable(PERIPH_ID_PMC, 1);
	140	clock_set_enable(PERIPH_ID_APBDMA, 1);
	141	clock_set_enable(PERIPH_ID_MEM, 1);
	142	clock_set_enable(PERIPH_ID_IRAMA, 1);
	143	clock_set_enable(PERIPH_ID_IRAMB, 1);
	144	clock_set_enable(PERIPH_ID_IRAMC, 1);
	145	clock_set_enable(PERIPH_ID_IRAMD, 1);
	146	clock_set_enable(PERIPH_ID_CORESIGHT, 1);
	147	clock_set_enable(PERIPH_ID_MSELECT, 1);
	148	clock_set_enable(PERIPH_ID_EMC1, 1);
	149	clock_set_enable(PERIPH_ID_MC1, 1);
	150	clock_set_enable(PERIPH_ID_DVFS, 1);
	151
4040ec10	152	/*
d94c2dbd TW	153	* Set MSELECT clock source as PLLP (00), and ask for a clock
	154	* divider that would set the MSELECT clock at 102MHz for a
	155	* PLLP base of 408MHz.
4040ec10 TW	156	*/
4040ec10 TW	157	clock_ll_set_source_divisor(PERIPH_ID_MSELECT, 0,
d94c2dbd	158	CLK_DIVIDER(NVBL_PLLP_KHZ, 102000));
4040ec10 TW	159
	160	/* I2C5 (DVC) gets CLK_M and a divisor of 17 */
	161	clock_ll_set_source_divisor(PERIPH_ID_I2C5, 3, 16);
	162
	163	/* Give clocks time to stabilize */
	164	udelay(1000);
	165
	166	/* Take required peripherals out of reset */
	167	debug("Taking periphs out of reset\n");
	168	reset_set_enable(PERIPH_ID_CACHE2, 0);
	169	reset_set_enable(PERIPH_ID_GPIO, 0);
	170	reset_set_enable(PERIPH_ID_TMR, 0);
	171	reset_set_enable(PERIPH_ID_COP, 0);
	172	reset_set_enable(PERIPH_ID_EMC, 0);
	173	reset_set_enable(PERIPH_ID_I2C5, 0);
	174	reset_set_enable(PERIPH_ID_FUSE, 0);
	175	reset_set_enable(PERIPH_ID_APBDMA, 0);
	176	reset_set_enable(PERIPH_ID_MEM, 0);
	177	reset_set_enable(PERIPH_ID_CORESIGHT, 0);
	178	reset_set_enable(PERIPH_ID_MSELECT, 0);
	179	reset_set_enable(PERIPH_ID_EMC1, 0);
	180	reset_set_enable(PERIPH_ID_MC1, 0);
702b8728	181	reset_set_enable(PERIPH_ID_DVFS, 0);
4040ec10	182
722e000c	183	debug("%s exit\n", __func__);
4040ec10 TW	184	}
4040ec10 TW	185
cad38a57	186	static bool is_partition_powered(u32 partid)
4040ec10 TW	187	{
	188	struct pmc_ctlr pmc = (struct pmc_ctlr )NV_PA_PMC_BASE;
	189	u32 reg;
	190
	191	/* Get power gate status */
	192	reg = readl(&pmc->pmc_pwrgate_status);
cad38a57	193	return !!(reg & (1 << partid));
4040ec10 TW	194	}
4040ec10 TW	195
cad38a57	196	static bool is_clamp_enabled(u32 partid)
4040ec10 TW	197	{
	198	struct pmc_ctlr pmc = (struct pmc_ctlr )NV_PA_PMC_BASE;
	199	u32 reg;
	200
9399e540 SW	201	/* Get clamp status. */
9399e540 SW	202	reg = readl(&pmc->pmc_clamp_status);
cad38a57	203	return !!(reg & (1 << partid));
4040ec10 TW	204	}
4040ec10 TW	205
cad38a57	206	static void power_partition(u32 partid)
4040ec10 TW	207	{
	208	struct pmc_ctlr pmc = (struct pmc_ctlr )NV_PA_PMC_BASE;
	209
cad38a57	210	debug("%s: part ID = %08X\n", __func__, partid);
4040ec10	211	/* Is the partition already on? */
cad38a57	212	if (!is_partition_powered(partid)) {
4040ec10 TW	213	/* No, toggle the partition power state (OFF -> ON) */
4040ec10 TW	214	debug("power_partition, toggling state\n");
41cd530d	215	writel(START_CP \| partid, &pmc->pmc_pwrgate_toggle);
4040ec10 TW	216
4040ec10 TW	217	/* Wait for the power to come up */
cad38a57	218	while (!is_partition_powered(partid))
4040ec10 TW	219	;
	220
	221	/* Wait for the clamp status to be cleared */
cad38a57	222	while (is_clamp_enabled(partid))
4040ec10 TW	223	;
	224
	225	/* Give I/O signals time to stabilize */
	226	udelay(IO_STABILIZATION_DELAY);
	227	}
	228	}
	229
	230	void powerup_cpus(void)
	231	{
4040ec10	232	/* We boot to the fast cluster */
722e000c TW	233	debug("%s entry: G cluster\n", __func__);
722e000c TW	234
4040ec10	235	/* Power up the fast cluster rail partition */
cad38a57	236	power_partition(CRAIL);
4040ec10 TW	237
4040ec10 TW	238	/* Power up the fast cluster non-CPU partition */
cad38a57	239	power_partition(C0NC);
4040ec10 TW	240
4040ec10 TW	241	/* Power up the fast cluster CPU0 partition */
cad38a57	242	power_partition(CE0);
4040ec10 TW	243	}
	244
	245	void start_cpu(u32 reset_vector)
	246	{
16bb08d1 SW	247	u32 imme, inst;
16bb08d1 SW	248
722e000c	249	debug("%s entry, reset_vector = %x\n", __func__, reset_vector);
4040ec10 TW	250
	251	t114_init_clocks();
	252
	253	/* Enable VDD_CPU */
	254	enable_cpu_power_rail();
	255
	256	/* Get the CPU(s) running */
	257	enable_cpu_clocks();
	258
	259	/* Enable CoreSight */
	260	clock_enable_coresight(1);
	261
	262	/* Take CPU(s) out of reset */
	263	remove_cpu_resets();
	264
16bb08d1 SW	265	/* Set the entry point for CPU execution from reset */
16bb08d1 SW	266
4040ec10	267	/*
16bb08d1 SW	268	* A01P with patched boot ROM; vector hard-coded to 0x4003fffc.
16bb08d1 SW	269	* See nvbug 1193357 for details.
4040ec10	270	*/
16bb08d1 SW	271
	272	/* mov r0, #lsb(reset_vector) */
	273	imme = reset_vector & 0xffff;
	274	inst = imme & 0xfff;
	275	inst \|= ((imme >> 12) << 16);
	276	inst \|= 0xe3000000;
	277	writel(inst, 0x4003fff0);
	278
	279	/* movt r0, #msb(reset_vector) */
	280	imme = (reset_vector >> 16) & 0xffff;
	281	inst = imme & 0xfff;
	282	inst \|= ((imme >> 12) << 16);
	283	inst \|= 0xe3400000;
	284	writel(inst, 0x4003fff4);
	285
	286	/* bx r0 */
	287	writel(0xe12fff10, 0x4003fff8);
	288
	289	/* b -12 */
	290	imme = (u32)-20;
	291	inst = (imme >> 2) & 0xffffff;
	292	inst \|= 0xea000000;
	293	writel(inst, 0x4003fffc);
	294
722e000c	295	/* Write to original location for compatibility */
16bb08d1	296	writel(reset_vector, EXCEP_VECTOR_CPU_RESET_VECTOR);
4040ec10 TW	297
	298	/* If the CPU(s) don't already have power, power 'em up */
	299	powerup_cpus();
	300	}