[people/ms/u-boot.git] / arch / arm / mach-tegra / xusb-padctl-common.h

/*
 * Copyright (c) 2014-2015, NVIDIA CORPORATION.  All rights reserved.
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
#define _TEGRA_XUSB_PADCTL_COMMON_H_

#include <common.h>
#include <fdtdec.h>

#include <asm/io.h>
#include <asm/arch-tegra/xusb-padctl.h>

struct tegra_xusb_padctl_lane {
	const char *name;

	unsigned int offset;
	unsigned int shift;
	unsigned int mask;
	unsigned int iddq;

	const unsigned int *funcs;
	unsigned int num_funcs;
};

struct tegra_xusb_phy_ops {
	int (*prepare)(struct tegra_xusb_phy *phy);
	int (*enable)(struct tegra_xusb_phy *phy);
	int (*disable)(struct tegra_xusb_phy *phy);
	int (*unprepare)(struct tegra_xusb_phy *phy);
};

struct tegra_xusb_phy {
	unsigned int type;
	const struct tegra_xusb_phy_ops *ops;
	struct tegra_xusb_padctl *padctl;
};

struct tegra_xusb_padctl_pin {
	const struct tegra_xusb_padctl_lane *lane;

	unsigned int func;
	int iddq;
};

#define MAX_GROUPS 5
#define MAX_PINS 7

struct tegra_xusb_padctl_group {
	const char *name;

	const char *pins[MAX_PINS];
	unsigned int num_pins;

	const char *func;
	int iddq;
};

struct tegra_xusb_padctl_soc {
	const struct tegra_xusb_padctl_lane *lanes;
	unsigned int num_lanes;
	const char *const *functions;
	unsigned int num_functions;
	struct tegra_xusb_phy *phys;
	unsigned int num_phys;
};

struct tegra_xusb_padctl_config {
	const char *name;

	struct tegra_xusb_padctl_group groups[MAX_GROUPS];
	unsigned int num_groups;
};

struct tegra_xusb_padctl {
	const struct tegra_xusb_padctl_soc *socdata;
	struct tegra_xusb_padctl_config config;
	struct fdt_resource regs;
	unsigned int enable;

};
extern struct tegra_xusb_padctl padctl;

static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
			       unsigned long offset)
{
	return readl(padctl->regs.start + offset);
}

static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
				 u32 value, unsigned long offset)
{
	writel(value, padctl->regs.start + offset);
}

int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
	const struct tegra_xusb_padctl_soc *socdata);

#endif
Commit	Line	Data
1680d7b6 SW	1	/*
	2	* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0
	5	*/
	6
	7	#ifndef _TEGRA_XUSB_PADCTL_COMMON_H_
	8	#define _TEGRA_XUSB_PADCTL_COMMON_H_
	9
	10	#include <common.h>
	11	#include <fdtdec.h>
	12
	13	#include <asm/io.h>
	14	#include <asm/arch-tegra/xusb-padctl.h>
	15
	16	struct tegra_xusb_padctl_lane {
	17	const char *name;
	18
	19	unsigned int offset;
	20	unsigned int shift;
	21	unsigned int mask;
	22	unsigned int iddq;
	23
	24	const unsigned int *funcs;
	25	unsigned int num_funcs;
	26	};
	27
	28	struct tegra_xusb_phy_ops {
	29	int (prepare)(struct tegra_xusb_phy phy);
	30	int (enable)(struct tegra_xusb_phy phy);
	31	int (disable)(struct tegra_xusb_phy phy);
	32	int (unprepare)(struct tegra_xusb_phy phy);
	33	};
	34
	35	struct tegra_xusb_phy {
095e6583	36	unsigned int type;
1680d7b6	37	const struct tegra_xusb_phy_ops *ops;
1680d7b6 SW	38	struct tegra_xusb_padctl *padctl;
	39	};
	40
	41	struct tegra_xusb_padctl_pin {
	42	const struct tegra_xusb_padctl_lane *lane;
	43
	44	unsigned int func;
	45	int iddq;
	46	};
	47
4e4b5574 SW	48	#define MAX_GROUPS 5
4e4b5574 SW	49	#define MAX_PINS 7
1680d7b6 SW	50
	51	struct tegra_xusb_padctl_group {
	52	const char *name;
	53
	54	const char *pins[MAX_PINS];
	55	unsigned int num_pins;
	56
	57	const char *func;
	58	int iddq;
	59	};
	60
095e6583 SW	61	struct tegra_xusb_padctl_soc {
	62	const struct tegra_xusb_padctl_lane *lanes;
	63	unsigned int num_lanes;
	64	const char const functions;
	65	unsigned int num_functions;
	66	struct tegra_xusb_phy *phys;
	67	unsigned int num_phys;
	68	};
	69
1680d7b6 SW	70	struct tegra_xusb_padctl_config {
	71	const char *name;
	72
	73	struct tegra_xusb_padctl_group groups[MAX_GROUPS];
	74	unsigned int num_groups;
	75	};
	76
	77	struct tegra_xusb_padctl {
095e6583 SW	78	const struct tegra_xusb_padctl_soc *socdata;
095e6583 SW	79	struct tegra_xusb_padctl_config config;
1680d7b6	80	struct fdt_resource regs;
1680d7b6 SW	81	unsigned int enable;
1680d7b6 SW	82
1680d7b6	83	};
095e6583	84	extern struct tegra_xusb_padctl padctl;
1680d7b6 SW	85
	86	static inline u32 padctl_readl(struct tegra_xusb_padctl *padctl,
	87	unsigned long offset)
	88	{
	89	return readl(padctl->regs.start + offset);
	90	}
	91
	92	static inline void padctl_writel(struct tegra_xusb_padctl *padctl,
	93	u32 value, unsigned long offset)
	94	{
	95	writel(value, padctl->regs.start + offset);
	96	}
	97
095e6583 SW	98	int tegra_xusb_process_nodes(const void *fdt, int nodes[], unsigned int count,
095e6583 SW	99	const struct tegra_xusb_padctl_soc *socdata);
1680d7b6 SW	100
1680d7b6 SW	101	#endif