[people/ms/u-boot.git] / arch / arm / mach-uniphier / arm32 / debug_ll.S

/*
 * On-chip UART initializaion for low-level debugging
 *
 * Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <linux/serial_reg.h>
#include <linux/linkage.h>

#include "../bcu/bcu-regs.h"
#include "../sc-regs.h"
#include "../sg-regs.h"

#if !defined(CONFIG_DEBUG_SEMIHOSTING)
#include CONFIG_DEBUG_LL_INCLUDE
#endif

#define BAUDRATE		115200
#define DIV_ROUND(x, d)		(((x) + ((d) / 2)) / (d))

ENTRY(debug_ll_init)
	ldr		r0, =SG_REVISION
	ldr		r1, [r0]
	and		r1, r1, #SG_REVISION_TYPE_MASK
	mov		r1, r1, lsr #SG_REVISION_TYPE_SHIFT

#if defined(CONFIG_ARCH_UNIPHIER_LD4)
#define UNIPHIER_LD4_UART_CLK		36864000
	cmp		r1, #0x26
	bne		ld4_end

	ldr		r0, =SG_IECTRL
	ldr		r1, [r0]
	orr		r1, r1, #1
	str		r1, [r0]

	sg_set_pinsel	88, 1, 8, 4, r0, r1	@ HSDOUT6 -> TXD0

	ldr		r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)

	b		init_uart
ld4_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
#define UNIPHIER_PRO4_UART_CLK		73728000
	cmp		r1, #0x28
	bne		pro4_end

	sg_set_pinsel	128, 0, 4, 8, r0, r1	@ TXD0 -> TXD0

	ldr		r0, =SG_LOADPINCTRL
	mov		r1, #1
	str		r1, [r0]

	ldr		r0, =SC_CLKCTRL
	ldr		r1, [r0]
	orr		r1, r1, #SC_CLKCTRL_CEN_PERI
	str		r1, [r0]

	ldr		r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)

	b		init_uart
pro4_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
#define UNIPHIER_SLD8_UART_CLK		80000000
	cmp		r1, #0x29
	bne		sld8_end

	ldr		r0, =SG_IECTRL
	ldr		r1, [r0]
	orr		r1, r1, #1
	str		r1, [r0]

	sg_set_pinsel	70, 3, 8, 4, r0, r1	@ HSDOUT0 -> TXD0

	ldr		r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)

	b		init_uart
sld8_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
#define UNIPHIER_PRO5_UART_CLK		73728000
	cmp		r1, #0x2A
	bne		pro5_end

	sg_set_pinsel	47, 0, 4, 8, r0, r1	@ TXD0 -> TXD0
	sg_set_pinsel	49, 0, 4, 8, r0, r1	@ TXD1 -> TXD1
	sg_set_pinsel	51, 0, 4, 8, r0, r1	@ TXD2 -> TXD2
	sg_set_pinsel	53, 0, 4, 8, r0, r1	@ TXD3 -> TXD3

	ldr		r0, =SG_LOADPINCTRL
	mov		r1, #1
	str		r1, [r0]

	ldr		r0, =SC_CLKCTRL
	ldr		r1, [r0]
	orr		r1, r1, #SC_CLKCTRL_CEN_PERI
	str		r1, [r0]

	ldr		r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)

	b		init_uart
pro5_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
#define UNIPHIER_PXS2_UART_CLK		88900000
	cmp		r1, #0x2E
	bne		pxs2_end

	ldr		r0, =SG_IECTRL
	ldr		r1, [r0]
	orr		r1, r1, #1
	str		r1, [r0]

	sg_set_pinsel	217, 8, 8, 4, r0, r1	@ TXD0 -> TXD0
	sg_set_pinsel	115, 8, 8, 4, r0, r1	@ TXD1 -> TXD1
	sg_set_pinsel	113, 8, 8, 4, r0, r1	@ TXD2 -> TXD2
	sg_set_pinsel	219, 8, 8, 4, r0, r1	@ TXD3 -> TXD3

	ldr		r0, =SC_CLKCTRL
	ldr		r1, [r0]
	orr		r1, r1, #SC_CLKCTRL_CEN_PERI
	str		r1, [r0]

	ldr		r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)

	b		init_uart
pxs2_end:
#endif
#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
#define UNIPHIER_LD6B_UART_CLK		88900000
	cmp		r1, #0x2F
	bne		ld6b_end

	ldr		r0, =SG_IECTRL
	ldr		r1, [r0]
	orr		r1, r1, #1
	str		r1, [r0]

	sg_set_pinsel	135, 3, 8, 4, r0, r1	@ PORT10 -> TXD0
	sg_set_pinsel	115, 0, 8, 4, r0, r1	@ TXD1 -> TXD1
	sg_set_pinsel	113, 2, 8, 4, r0, r1	@ SBO0 -> TXD2

	ldr		r0, =SC_CLKCTRL
	ldr		r1, [r0]
	orr		r1, r1, #SC_CLKCTRL_CEN_PERI
	str		r1, [r0]

	ldr		r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)

	b		init_uart
ld6b_end:
#endif
	mov		pc, lr

init_uart:
	addruart	r0, r1, r2
	mov		r1, #UART_LCR_WLEN8 << 8
	str		r1, [r0, #0x10]
	str		r3, [r0, #0x24]

	mov		pc, lr
ENDPROC(debug_ll_init)
Commit	Line	Data
e6eecca5 MY	1	/*
	2	* On-chip UART initializaion for low-level debugging
	3	*
	4	* Copyright (C) 2014-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <linux/serial_reg.h>
	10	#include <linux/linkage.h>
107b3fb4	11
fe5ea57b MY	12	#include "../bcu/bcu-regs.h"
	13	#include "../sc-regs.h"
	14	#include "../sg-regs.h"
e6eecca5 MY	15
	16	#if !defined(CONFIG_DEBUG_SEMIHOSTING)
	17	#include CONFIG_DEBUG_LL_INCLUDE
	18	#endif
	19
	20	#define BAUDRATE 115200
	21	#define DIV_ROUND(x, d) (((x) + ((d) / 2)) / (d))
	22
	23	ENTRY(debug_ll_init)
	24	ldr r0, =SG_REVISION
	25	ldr r1, [r0]
	26	and r1, r1, #SG_REVISION_TYPE_MASK
	27	mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
	28
ea65c980 MY	29	#if defined(CONFIG_ARCH_UNIPHIER_LD4)
ea65c980 MY	30	#define UNIPHIER_LD4_UART_CLK 36864000
e6eecca5	31	cmp r1, #0x26
5b660066	32	bne ld4_end
e6eecca5 MY	33
	34	ldr r0, =SG_IECTRL
	35	ldr r1, [r0]
	36	orr r1, r1, #1
	37	str r1, [r0]
	38
	39	sg_set_pinsel 88, 1, 8, 4, r0, r1 @ HSDOUT6 -> TXD0
	40
ea65c980	41	ldr r3, =DIV_ROUND(UNIPHIER_LD4_UART_CLK, 16 * BAUDRATE)
e6eecca5 MY	42
e6eecca5 MY	43	b init_uart
5b660066	44	ld4_end:
e6eecca5	45	#endif
ea65c980 MY	46	#if defined(CONFIG_ARCH_UNIPHIER_PRO4)
ea65c980 MY	47	#define UNIPHIER_PRO4_UART_CLK 73728000
e6eecca5	48	cmp r1, #0x28
5b660066	49	bne pro4_end
e6eecca5 MY	50
	51	sg_set_pinsel 128, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
	52
	53	ldr r0, =SG_LOADPINCTRL
	54	mov r1, #1
	55	str r1, [r0]
	56
	57	ldr r0, =SC_CLKCTRL
	58	ldr r1, [r0]
	59	orr r1, r1, #SC_CLKCTRL_CEN_PERI
	60	str r1, [r0]
	61
ea65c980	62	ldr r3, =DIV_ROUND(UNIPHIER_PRO4_UART_CLK, 16 * BAUDRATE)
e6eecca5 MY	63
e6eecca5 MY	64	b init_uart
5b660066	65	pro4_end:
e6eecca5	66	#endif
ea65c980 MY	67	#if defined(CONFIG_ARCH_UNIPHIER_SLD8)
ea65c980 MY	68	#define UNIPHIER_SLD8_UART_CLK 80000000
e6eecca5	69	cmp r1, #0x29
5b660066	70	bne sld8_end
e6eecca5 MY	71
	72	ldr r0, =SG_IECTRL
	73	ldr r1, [r0]
	74	orr r1, r1, #1
	75	str r1, [r0]
	76
	77	sg_set_pinsel 70, 3, 8, 4, r0, r1 @ HSDOUT0 -> TXD0
	78
ea65c980	79	ldr r3, =DIV_ROUND(UNIPHIER_SLD8_UART_CLK, 16 * BAUDRATE)
e6eecca5 MY	80
e6eecca5 MY	81	b init_uart
5b660066	82	sld8_end:
e6eecca5	83	#endif
ea65c980 MY	84	#if defined(CONFIG_ARCH_UNIPHIER_PRO5)
ea65c980 MY	85	#define UNIPHIER_PRO5_UART_CLK 73728000
28f40d4a	86	cmp r1, #0x2A
5b660066	87	bne pro5_end
28f40d4a MY	88
	89	sg_set_pinsel 47, 0, 4, 8, r0, r1 @ TXD0 -> TXD0
	90	sg_set_pinsel 49, 0, 4, 8, r0, r1 @ TXD1 -> TXD1
	91	sg_set_pinsel 51, 0, 4, 8, r0, r1 @ TXD2 -> TXD2
	92	sg_set_pinsel 53, 0, 4, 8, r0, r1 @ TXD3 -> TXD3
	93
	94	ldr r0, =SG_LOADPINCTRL
	95	mov r1, #1
	96	str r1, [r0]
	97
	98	ldr r0, =SC_CLKCTRL
	99	ldr r1, [r0]
	100	orr r1, r1, #SC_CLKCTRL_CEN_PERI
	101	str r1, [r0]
	102
ea65c980	103	ldr r3, =DIV_ROUND(UNIPHIER_PRO5_UART_CLK, 16 * BAUDRATE)
28f40d4a MY	104
28f40d4a MY	105	b init_uart
5b660066	106	pro5_end:
28f40d4a	107	#endif
ea65c980 MY	108	#if defined(CONFIG_ARCH_UNIPHIER_PXS2)
ea65c980 MY	109	#define UNIPHIER_PXS2_UART_CLK 88900000
019df879	110	cmp r1, #0x2E
5b660066	111	bne pxs2_end
019df879 MY	112
	113	ldr r0, =SG_IECTRL
	114	ldr r1, [r0]
	115	orr r1, r1, #1
	116	str r1, [r0]
	117
	118	sg_set_pinsel 217, 8, 8, 4, r0, r1 @ TXD0 -> TXD0
	119	sg_set_pinsel 115, 8, 8, 4, r0, r1 @ TXD1 -> TXD1
	120	sg_set_pinsel 113, 8, 8, 4, r0, r1 @ TXD2 -> TXD2
	121	sg_set_pinsel 219, 8, 8, 4, r0, r1 @ TXD3 -> TXD3
	122
	123	ldr r0, =SC_CLKCTRL
	124	ldr r1, [r0]
	125	orr r1, r1, #SC_CLKCTRL_CEN_PERI
	126	str r1, [r0]
	127
ea65c980	128	ldr r3, =DIV_ROUND(UNIPHIER_PXS2_UART_CLK, 16 * BAUDRATE)
019df879 MY	129
019df879 MY	130	b init_uart
5b660066	131	pxs2_end:
019df879	132	#endif
ea65c980 MY	133	#if defined(CONFIG_ARCH_UNIPHIER_LD6B)
ea65c980 MY	134	#define UNIPHIER_LD6B_UART_CLK 88900000
019df879	135	cmp r1, #0x2F
5b660066	136	bne ld6b_end
019df879 MY	137
	138	ldr r0, =SG_IECTRL
	139	ldr r1, [r0]
	140	orr r1, r1, #1
	141	str r1, [r0]
	142
	143	sg_set_pinsel 135, 3, 8, 4, r0, r1 @ PORT10 -> TXD0
	144	sg_set_pinsel 115, 0, 8, 4, r0, r1 @ TXD1 -> TXD1
	145	sg_set_pinsel 113, 2, 8, 4, r0, r1 @ SBO0 -> TXD2
	146
	147	ldr r0, =SC_CLKCTRL
	148	ldr r1, [r0]
	149	orr r1, r1, #SC_CLKCTRL_CEN_PERI
	150	str r1, [r0]
	151
ea65c980	152	ldr r3, =DIV_ROUND(UNIPHIER_LD6B_UART_CLK, 16 * BAUDRATE)
019df879 MY	153
019df879 MY	154	b init_uart
5b660066	155	ld6b_end:
019df879	156	#endif
5d076486	157	mov pc, lr
e6eecca5 MY	158
	159	init_uart:
	160	addruart r0, r1, r2
	161	mov r1, #UART_LCR_WLEN8 << 8
	162	str r1, [r0, #0x10]
	163	str r3, [r0, #0x24]
	164
	165	mov pc, lr
	166	ENDPROC(debug_ll_init)