[people/ms/u-boot.git] / arch / arm / mach-uniphier / arm32 / lowlevel_init.S

/*
 * Copyright (C) 2012-2015 Panasonic Corporation
 * Copyright (C) 2015-2016 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <linux/linkage.h>
#include <linux/sizes.h>
#include <asm/system.h>

ENTRY(lowlevel_init)
	mov	r8, lr			@ persevere link reg across call

	/*
	 * The UniPhier Boot ROM loads SPL code to the L2 cache.
	 * But CPUs can only do instruction fetch now because start.S has
	 * cleared C and M bits.
	 * First we need to turn on MMU and Dcache again to get back
	 * data access to L2.
	 */
	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
	orr	r0, r0, #(CR_C | CR_M)	@ enable MMU and Dcache
	mcr	p15, 0, r0, c1, c0, 0

#ifdef CONFIG_DEBUG_LL
	bl	debug_ll_init
#endif

	bl	setup_init_ram		@ RAM area for stack and page table

	/*
	 * Now we are using the page table embedded in the Boot ROM.
	 * It is not handy since it is not a straight mapped table for sLD3.
	 * Also, the access to the external bus is prohibited.  What we need
	 * to do next is to create a page table and switch over to it.
	 */
	bl	create_page_table
	bl	__v7_flush_dcache_all

	/* Disable MMU and Dcache before switching Page Table */
	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
	bic	r0, r0, #(CR_C | CR_M)	@ disable MMU and Dcache
	mcr	p15, 0, r0, c1, c0, 0

	bl	enable_mmu

	mov	lr, r8			@ restore link
	mov	pc, lr			@ back to my caller
ENDPROC(lowlevel_init)

ENTRY(enable_mmu)
	mrc	p15, 0, r0, c2, c0, 2	@ TTBCR (Translation Table Base Control Register)
	bic	r0, r0, #0x37
	orr	r0, r0, #0x20		@ disable TTBR1
	mcr	p15, 0, r0, c2, c0, 2

	orr	r0, r12, #0x8		@ Outer Cacheability for table walks: WBWA
	mcr	p15, 0, r0, c2, c0, 0   @ TTBR0

	mov	r0, #0
	mcr	p15, 0, r0, c8, c7, 0	@ invalidate TLBs

	mov	r0, #-1			@ manager for all domains (No permission check)
	mcr	p15, 0, r0, c3, c0, 0   @ DACR (Domain Access Control Register)

	dsb
	isb
	/*
	 * MMU on:
	 * TLBs was already invalidated in "../start.S"
	 * So, we don't need to invalidate it here.
	 */
	mrc	p15, 0, r0, c1, c0, 0	@ SCTLR (System Control Register)
	orr	r0, r0, #(CR_C | CR_M)	@ MMU and Dcache enable
	mcr	p15, 0, r0, c1, c0, 0

	mov	pc, lr
ENDPROC(enable_mmu)

/*
 * For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
 * It is large enough for tmp RAM.
 */
#define BOOT_RAM_SIZE	(SZ_32K)
#define BOOT_RAM_BASE	((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
#define BOOT_RAM_WAYS	(0x00000100)	@ way 8

#define SSCO_BASE		0x506c0000
#define SSCOPE			0x244
#define SSCOQM			0x248
#define SSCOQAD			0x24c
#define SSCOQSZ			0x250
#define SSCOQWN			0x258
#define SSCOPPQSEF		0x25c
#define SSCOLPQS		0x260

ENTRY(setup_init_ram)
	ldr	r1, = SSCO_BASE
	mrc	p15, 0, r0, c2, c0, 0	@ TTBR0
	ldr	r0, [r0, #0x400]	@ entry for virtual address 0x100*****
	bfc	r0, #0, #20
	cmp	r0, #0x50000000		@ is sLD3 page table?
	biceq	r1, r1, #0xc0000000	@ sLD3 ROM maps 0x5******* to 0x1*******

	/* Touch to zero for the boot way */
0:	ldr	r0, = 0x00408006	@ touch to zero with address range
	str	r0, [r1, #SSCOQM]
	ldr	r0, = BOOT_RAM_BASE
	str	r0, [r1, #SSCOQAD]
	ldr	r0, = BOOT_RAM_SIZE
	str	r0, [r1, #SSCOQSZ]
	ldr	r0, = BOOT_RAM_WAYS
	str	r0, [r1, #SSCOQWN]
	ldr	r0, [r1, #SSCOPPQSEF]
	cmp	r0, #0			@ check if the command is successfully set
	bne	0b			@ try again if an error occurs

1:	ldr	r0, [r1, #SSCOLPQS]
	cmp	r0, #0x4
	bne	1b			@ wait until the operation is completed
	str	r0, [r1, #SSCOLPQS]	@ clear the complete notification flag

	mov	pc, lr
ENDPROC(setup_init_ram)

#define DEVICE	0x00002002 /* Non-shareable Device */
#define NORMAL	0x0000000e /* Normal Memory Write-Back, No Write-Allocate */

ENTRY(create_page_table)
	ldr	r0, = DEVICE
	ldr	r1, = BOOT_RAM_BASE
	mov	r12, r1			@ r12 is preserved during D-cache flush
0:	str	r0, [r1], #4		@ specify all the sections as Device
	adds	r0, r0, #0x00100000
	bcc	0b

	ldr	r0, = NORMAL
	str	r0, [r12]		@ mark the first section as Normal
	add	r0, r0, #0x00100000
	str	r0, [r12, #4]		@ mark the second section as Normal
	mov	pc, lr
ENDPROC(create_page_table)
Commit	Line	Data
5894ca00	1	/*
4bab70a7 MY	2	* Copyright (C) 2012-2015 Panasonic Corporation
	3	* Copyright (C) 2015-2016 Socionext Inc.
	4	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	5	*
	6	* SPDX-License-Identifier: GPL-2.0+
	7	*/
	8
	9	#include <config.h>
	10	#include <linux/linkage.h>
105a9e70	11	#include <linux/sizes.h>
5894ca00	12	#include <asm/system.h>
107b3fb4	13
5894ca00 MY	14	ENTRY(lowlevel_init)
	15	mov r8, lr @ persevere link reg across call
	16
	17	/*
	18	* The UniPhier Boot ROM loads SPL code to the L2 cache.
	19	* But CPUs can only do instruction fetch now because start.S has
	20	* cleared C and M bits.
	21	* First we need to turn on MMU and Dcache again to get back
	22	* data access to L2.
	23	*/
4d13b1b7 MY	24	mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
4d13b1b7 MY	25	orr r0, r0, #(CR_C \| CR_M) @ enable MMU and Dcache
5894ca00 MY	26	mcr p15, 0, r0, c1, c0, 0
5894ca00 MY	27
b4ad44ba	28	#ifdef CONFIG_DEBUG_LL
e6eecca5	29	bl debug_ll_init
b4ad44ba MY	30	#endif
b4ad44ba MY	31
4cb9399e	32	bl setup_init_ram @ RAM area for stack and page table
4b50369f	33
5894ca00 MY	34	/*
	35	* Now we are using the page table embedded in the Boot ROM.
	36	* It is not handy since it is not a straight mapped table for sLD3.
4b50369f MY	37	* Also, the access to the external bus is prohibited. What we need
4b50369f MY	38	* to do next is to create a page table and switch over to it.
5894ca00	39	*/
4b50369f	40	bl create_page_table
c09d2905	41	bl __v7_flush_dcache_all
5894ca00 MY	42
5894ca00 MY	43	/* Disable MMU and Dcache before switching Page Table */
4d13b1b7	44	mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
5894ca00 MY	45	bic r0, r0, #(CR_C \| CR_M) @ disable MMU and Dcache
	46	mcr p15, 0, r0, c1, c0, 0
	47
	48	bl enable_mmu
	49
5894ca00 MY	50	mov lr, r8 @ restore link
	51	mov pc, lr @ back to my caller
	52	ENDPROC(lowlevel_init)
	53
	54	ENTRY(enable_mmu)
	55	mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register)
	56	bic r0, r0, #0x37
	57	orr r0, r0, #0x20 @ disable TTBR1
	58	mcr p15, 0, r0, c2, c0, 2
	59
4b50369f	60	orr r0, r12, #0x8 @ Outer Cacheability for table walks: WBWA
5894ca00 MY	61	mcr p15, 0, r0, c2, c0, 0 @ TTBR0
	62
	63	mov r0, #0
	64	mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs
	65
	66	mov r0, #-1 @ manager for all domains (No permission check)
	67	mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register)
	68
	69	dsb
	70	isb
	71	/*
	72	* MMU on:
	73	* TLBs was already invalidated in "../start.S"
	74	* So, we don't need to invalidate it here.
	75	*/
4d13b1b7	76	mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register)
5894ca00 MY	77	orr r0, r0, #(CR_C \| CR_M) @ MMU and Dcache enable
	78	mcr p15, 0, r0, c1, c0, 0
	79
	80	mov pc, lr
	81	ENDPROC(enable_mmu)
	82
105a9e70 MY	83	/*
	84	* For PH1-Pro4 or older SoCs, the size of WAY is 32KB.
	85	* It is large enough for tmp RAM.
	86	*/
4b50369f MY	87	#define BOOT_RAM_SIZE (SZ_32K)
4b50369f MY	88	#define BOOT_RAM_BASE ((CONFIG_SPL_STACK) - (BOOT_RAM_SIZE))
0efbbc5c MY	89	#define BOOT_RAM_WAYS (0x00000100) @ way 8
	90
	91	#define SSCO_BASE 0x506c0000
	92	#define SSCOPE 0x244
	93	#define SSCOQM 0x248
	94	#define SSCOQAD 0x24c
	95	#define SSCOQSZ 0x250
	96	#define SSCOQWN 0x258
	97	#define SSCOPPQSEF 0x25c
	98	#define SSCOLPQS 0x260
5894ca00 MY	99
5894ca00 MY	100	ENTRY(setup_init_ram)
0efbbc5c	101	ldr r1, = SSCO_BASE
82d075e7 MY	102	mrc p15, 0, r0, c2, c0, 0 @ TTBR0
	103	ldr r0, [r0, #0x400] @ entry for virtual address 0x100*****
	104	bfc r0, #0, #20
	105	cmp r0, #0x50000000 @ is sLD3 page table?
	106	biceq r1, r1, #0xc0000000 @ sLD3 ROM maps 0x5***** to 0x1*****
0efbbc5c MY	107
	108	/* Touch to zero for the boot way */
	109	0: ldr r0, = 0x00408006 @ touch to zero with address range
	110	str r0, [r1, #SSCOQM]
4b50369f	111	ldr r0, = BOOT_RAM_BASE
0efbbc5c	112	str r0, [r1, #SSCOQAD]
5894ca00	113	ldr r0, = BOOT_RAM_SIZE
0efbbc5c MY	114	str r0, [r1, #SSCOQSZ]
	115	ldr r0, = BOOT_RAM_WAYS
	116	str r0, [r1, #SSCOQWN]
	117	ldr r0, [r1, #SSCOPPQSEF]
5894ca00	118	cmp r0, #0 @ check if the command is successfully set
4d13b1b7	119	bne 0b @ try again if an error occurs
5894ca00	120
0efbbc5c	121	1: ldr r0, [r1, #SSCOLPQS]
5894ca00 MY	122	cmp r0, #0x4
5894ca00 MY	123	bne 1b @ wait until the operation is completed
0efbbc5c	124	str r0, [r1, #SSCOLPQS] @ clear the complete notification flag
5894ca00 MY	125
	126	mov pc, lr
	127	ENDPROC(setup_init_ram)
4b50369f MY	128
	129	#define DEVICE 0x00002002 /* Non-shareable Device */
	130	#define NORMAL 0x0000000e /* Normal Memory Write-Back, No Write-Allocate */
	131
	132	ENTRY(create_page_table)
	133	ldr r0, = DEVICE
	134	ldr r1, = BOOT_RAM_BASE
	135	mov r12, r1 @ r12 is preserved during D-cache flush
	136	0: str r0, [r1], #4 @ specify all the sections as Device
	137	adds r0, r0, #0x00100000
	138	bcc 0b
	139
	140	ldr r0, = NORMAL
	141	str r0, [r12] @ mark the first section as Normal
	142	add r0, r0, #0x00100000
	143	str r0, [r12, #4] @ mark the second section as Normal
	144	mov pc, lr
	145	ENDPROC(create_page_table)