projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 682e09ff MY |
1 | /* |
| 2 | * Copyright (C) 2016 Socionext Inc. | |
| 3 | * Author: Masahiro Yamada <yamada.masahiro@socionext.com> | |
| 4 | * | |
| 5 | * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | */ | |
| 7 | ||
| 546197b9 | 8 | #include <linux/delay.h> |
| 682e09ff MY |
9 | |
| 10 | #include "../init.h" | |
| 11 | #include "../sc64-regs.h" | |
| 12 | #include "pll.h" | |
| 13 | ||
| a55957b9 MY |
14 | /* PLL type: SSC */ |
| 15 | #define SC_CPLLCTRL (SC_BASE_ADDR | 0x1400) /* CPU/ARM */ | |
| 16 | #define SC_SPLLCTRL (SC_BASE_ADDR | 0x1410) /* misc */ | |
| 17 | #define SC_SPLL2CTRL (SC_BASE_ADDR | 0x1420) /* DSP */ | |
| 18 | #define SC_MPLLCTRL (SC_BASE_ADDR | 0x1430) /* Video codec */ | |
| 19 | #define SC_VPPLLCTRL (SC_BASE_ADDR | 0x1440) /* VPE etc. */ | |
| 20 | #define SC_GPPLLCTRL (SC_BASE_ADDR | 0x1450) /* GPU/Mali */ | |
| 21 | #define SC_DPLL0CTRL (SC_BASE_ADDR | 0x1460) /* DDR memory 0 */ | |
| 22 | #define SC_DPLL1CTRL (SC_BASE_ADDR | 0x1470) /* DDR memory 1 */ | |
| 23 | #define SC_DPLL2CTRL (SC_BASE_ADDR | 0x1480) /* DDR memory 2 */ | |
| 24 | ||
| 25 | /* PLL type: VPLL27 */ | |
| 26 | #define SC_VPLL27FCTRL (SC_BASE_ADDR | 0x1500) | |
| 27 | #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1520) | |
| 28 | ||
| 29 | /* PLL type: DSPLL */ | |
| 30 | #define SC_VPLL8KCTRL (SC_BASE_ADDR | 0x1540) | |
| 31 | #define SC_A2PLLCTRL (SC_BASE_ADDR | 0x15C0) | |
| 32 | ||
| a314a245 | 33 | void uniphier_ld20_pll_init(void) |
| 682e09ff | 34 | { |
| 682e09ff MY |
35 | uniphier_ld20_sscpll_init(SC_CPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); |
| 36 | /* do nothing for SPLL */ | |
| 37 | uniphier_ld20_sscpll_init(SC_SPLL2CTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); | |
| 38 | uniphier_ld20_sscpll_init(SC_MPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); | |
| 39 | uniphier_ld20_sscpll_init(SC_VPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 4); | |
| 40 | uniphier_ld20_sscpll_init(SC_GPPLLCTRL, UNIPHIER_PLL_FREQ_DEFAULT, 0, 2); | |
| 41 | ||
| 42 | mdelay(1); | |
| 43 | ||
| 29532623 MY |
44 | uniphier_ld20_sscpll_ssc_en(SC_CPLLCTRL); |
| 45 | uniphier_ld20_sscpll_ssc_en(SC_SPLL2CTRL); | |
| 46 | uniphier_ld20_sscpll_ssc_en(SC_MPLLCTRL); | |
| 47 | uniphier_ld20_sscpll_ssc_en(SC_VPPLLCTRL); | |
| 48 | uniphier_ld20_sscpll_ssc_en(SC_GPPLLCTRL); | |
| 49 | uniphier_ld20_sscpll_ssc_en(SC_DPLL0CTRL); | |
| 50 | uniphier_ld20_sscpll_ssc_en(SC_DPLL1CTRL); | |
| 51 | uniphier_ld20_sscpll_ssc_en(SC_DPLL2CTRL); | |
| 682e09ff MY |
52 | |
| 53 | uniphier_ld20_vpll27_init(SC_VPLL27FCTRL); | |
| 54 | uniphier_ld20_vpll27_init(SC_VPLL27ACTRL); | |
| 55 | ||
| 56 | uniphier_ld20_dspll_init(SC_VPLL8KCTRL); | |
| 57 | uniphier_ld20_dspll_init(SC_A2PLLCTRL); | |
| 682e09ff | 58 | } |