[thirdparty/u-boot.git] / arch / arm / mach-uniphier / dram / cmd_ddrmphy.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2015-2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 */

#include <common.h>
#include <stdio.h>
#include <linux/io.h>
#include <linux/printk.h>
#include <linux/sizes.h>

#include "../soc-info.h"
#include "ddrmphy-regs.h"

/* Select either decimal or hexadecimal */
#if 1
#define PRINTF_FORMAT "%2d"
#else
#define PRINTF_FORMAT "%02x"
#endif
/* field separator */
#define FS "   "

#define ptr_to_uint(p)	((unsigned int)(unsigned long)(p))

#define UNIPHIER_MAX_NR_DDRMPHY		3

struct uniphier_ddrmphy_param {
	unsigned int soc_id;
	unsigned int nr_phy;
	struct {
		resource_size_t base;
		unsigned int nr_zq;
		unsigned int nr_dx;
	} phy[UNIPHIER_MAX_NR_DDRMPHY];
};

static const struct uniphier_ddrmphy_param uniphier_ddrmphy_param[] = {
	{
		.soc_id = UNIPHIER_PXS2_ID,
		.nr_phy = 3,
		.phy = {
			{ .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
			{ .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
			{ .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
		},
	},
	{
		.soc_id = UNIPHIER_LD6B_ID,
		.nr_phy = 3,
		.phy = {
			{ .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
			{ .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
			{ .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
		},
	},
};
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrmphy_param, uniphier_ddrmphy_param)

static void print_bdl(void __iomem *reg, int n)
{
	u32 val = readl(reg);
	int i;

	for (i = 0; i < n; i++)
		printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
}

static void dump_loop(const struct uniphier_ddrmphy_param *param,
		      void (*callback)(void __iomem *))
{
	void __iomem *phy_base, *dx_base;
	int phy, dx;

	for (phy = 0; phy < param->nr_phy; phy++) {
		phy_base = ioremap(param->phy[phy].base, SZ_4K);
		dx_base = phy_base + MPHY_DX_BASE;

		for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
			printf("PHY%dDX%d:", phy, dx);
			(*callback)(dx_base);
			dx_base += MPHY_DX_STRIDE;
			printf("\n");
		}

		iounmap(phy_base);
	}
}

static void zq_dump(const struct uniphier_ddrmphy_param *param)
{
	void __iomem *phy_base, *zq_base;
	u32 val;
	int phy, zq, i;

	printf("\n--- Impedance Data ---\n");
	printf("           ZPD  ZPU  OPD  OPU  ZDV  ODV\n");

	for (phy = 0; phy < param->nr_phy; phy++) {
		phy_base = ioremap(param->phy[phy].base, SZ_4K);
		zq_base = phy_base + MPHY_ZQ_BASE;

		for (zq = 0; zq < param->phy[phy].nr_zq; zq++) {
			printf("PHY%dZQ%d:", phy, zq);

			val = readl(zq_base + MPHY_ZQ_DR);
			for (i = 0; i < 4; i++) {
				printf(FS PRINTF_FORMAT, val & 0x7f);
				val >>= 7;
			}

			val = readl(zq_base + MPHY_ZQ_PR);
			for (i = 0; i < 2; i++) {
				printf(FS PRINTF_FORMAT, val & 0xf);
				val >>= 4;
			}

			zq_base += MPHY_ZQ_STRIDE;
			printf("\n");
		}

		iounmap(phy_base);
	}
}

static void __wbdl_dump(void __iomem *dx_base)
{
	print_bdl(dx_base + MPHY_DX_BDLR0, 4);
	print_bdl(dx_base + MPHY_DX_BDLR1, 4);
	print_bdl(dx_base + MPHY_DX_BDLR2, 2);

	printf(FS "(+" PRINTF_FORMAT ")",
	       readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
}

static void wbdl_dump(const struct uniphier_ddrmphy_param *param)
{
	printf("\n--- Write Bit Delay Line ---\n");
	printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  DQS  (WDQD)\n");

	dump_loop(param, &__wbdl_dump);
}

static void __rbdl_dump(void __iomem *dx_base)
{
	print_bdl(dx_base + MPHY_DX_BDLR3, 4);
	print_bdl(dx_base + MPHY_DX_BDLR4, 4);
	print_bdl(dx_base + MPHY_DX_BDLR5, 1);

	printf(FS "(+" PRINTF_FORMAT ")",
	       (readl(dx_base + MPHY_DX_LCDLR1) >> 8) & 0xff);

	printf(FS "(+" PRINTF_FORMAT ")",
	       (readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
}

static void rbdl_dump(const struct uniphier_ddrmphy_param *param)
{
	printf("\n--- Read Bit Delay Line ---\n");
	printf("           DQ0  DQ1  DQ2  DQ3  DQ4  DQ5  DQ6  DQ7   DM  (RDQSD) (RDQSND)\n");

	dump_loop(param, &__rbdl_dump);
}

static void __wld_dump(void __iomem *dx_base)
{
	int rank;
	u32 lcdlr0 = readl(dx_base + MPHY_DX_LCDLR0);
	u32 gtr = readl(dx_base + MPHY_DX_GTR);

	for (rank = 0; rank < 4; rank++) {
		u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
		u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */

		printf(FS PRINTF_FORMAT "%sT", wld,
		       wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
	}
}

static void wld_dump(const struct uniphier_ddrmphy_param *param)
{
	printf("\n--- Write Leveling Delay ---\n");
	printf("           Rank0   Rank1   Rank2   Rank3\n");

	dump_loop(param, &__wld_dump);
}

static void __dqsgd_dump(void __iomem *dx_base)
{
	int rank;
	u32 lcdlr2 = readl(dx_base + MPHY_DX_LCDLR2);
	u32 gtr = readl(dx_base + MPHY_DX_GTR);

	for (rank = 0; rank < 4; rank++) {
		u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
		u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */

		printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
	}
}

static void dqsgd_dump(const struct uniphier_ddrmphy_param *param)
{
	printf("\n--- DQS Gating Delay ---\n");
	printf("           Rank0   Rank1   Rank2   Rank3\n");

	dump_loop(param, &__dqsgd_dump);
}

static void __mdl_dump(void __iomem *dx_base)
{
	int i;
	u32 mdl = readl(dx_base + MPHY_DX_MDLR);

	for (i = 0; i < 3; i++)
		printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
}

static void mdl_dump(const struct uniphier_ddrmphy_param *param)
{
	printf("\n--- Master Delay Line ---\n");
	printf("          IPRD TPRD MDLD\n");

	dump_loop(param, &__mdl_dump);
}

#define REG_DUMP(x)							\
	{ int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst;	\
		printf("%3d: %-10s: %p : %08x\n",			\
		       ofst >> MPHY_SHIFT, #x, reg, readl(reg)); }

#define DX_REG_DUMP(dx, x)						\
	{ int ofst = MPHY_DX_BASE + MPHY_DX_STRIDE * (dx) +		\
			MPHY_DX_## x;					\
		void __iomem *reg = phy_base + ofst;			\
		printf("%3d: DX%d%-7s: %p : %08x\n",			\
		       ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }

static void reg_dump(const struct uniphier_ddrmphy_param *param)
{
	void __iomem *phy_base;
	int phy, dx;

	printf("\n--- DDR Multi PHY registers ---\n");

	for (phy = 0; phy < param->nr_phy; phy++) {
		phy_base = ioremap(param->phy[phy].base, SZ_4K);

		printf("== PHY%d (base: %08x) ==\n", phy,
		       ptr_to_uint(phy_base));
		printf(" No: Name      : Address  : Data\n");

		REG_DUMP(RIDR);
		REG_DUMP(PIR);
		REG_DUMP(PGCR0);
		REG_DUMP(PGCR1);
		REG_DUMP(PGCR2);
		REG_DUMP(PGCR3);
		REG_DUMP(PGSR0);
		REG_DUMP(PGSR1);
		REG_DUMP(PLLCR);
		REG_DUMP(PTR0);
		REG_DUMP(PTR1);
		REG_DUMP(PTR2);
		REG_DUMP(PTR3);
		REG_DUMP(PTR4);
		REG_DUMP(ACMDLR);
		REG_DUMP(ACBDLR0);
		REG_DUMP(DXCCR);
		REG_DUMP(DSGCR);
		REG_DUMP(DCR);
		REG_DUMP(DTPR0);
		REG_DUMP(DTPR1);
		REG_DUMP(DTPR2);
		REG_DUMP(DTPR3);
		REG_DUMP(MR0);
		REG_DUMP(MR1);
		REG_DUMP(MR2);
		REG_DUMP(MR3);

		for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
			DX_REG_DUMP(dx, GCR0);
			DX_REG_DUMP(dx, GCR1);
			DX_REG_DUMP(dx, GCR2);
			DX_REG_DUMP(dx, GCR3);
			DX_REG_DUMP(dx, GTR);
		}

		iounmap(phy_base);
	}
}

static int do_ddrm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
	const struct uniphier_ddrmphy_param *param;
	char *cmd;

	param = uniphier_get_ddrmphy_param();
	if (!param) {
		pr_err("unsupported SoC\n");
		return CMD_RET_FAILURE;
	}

	if (argc == 1)
		cmd = "all";
	else
		cmd = argv[1];

	if (!strcmp(cmd, "zq") || !strcmp(cmd, "all"))
		zq_dump(param);

	if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
		wbdl_dump(param);

	if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
		rbdl_dump(param);

	if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
		wld_dump(param);

	if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
		dqsgd_dump(param);

	if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
		mdl_dump(param);

	if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
		reg_dump(param);

	return CMD_RET_SUCCESS;
}

U_BOOT_CMD(
	ddrm,	2,	1,	do_ddrm,
	"UniPhier DDR Multi PHY parameters dumper",
	"- dump all of the following\n"
	"ddrm zq - dump Impedance Data\n"
	"ddrm wbdl - dump Write Bit Delay\n"
	"ddrm rbdl - dump Read Bit Delay\n"
	"ddrm wld - dump Write Leveling\n"
	"ddrm dqsgd - dump DQS Gating Delay\n"
	"ddrm mdl - dump Master Delay Line\n"
	"ddrm reg - dump registers\n"
);
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
93d92d46	2	/*
513cfacc MY	3	* Copyright (C) 2015-2017 Socionext Inc.
513cfacc MY	4	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
93d92d46 MY	5	*/
	6
	7	#include <common.h>
dd74b945	8	#include <stdio.h>
93d92d46	9	#include <linux/io.h>
dd74b945	10	#include <linux/printk.h>
513cfacc	11	#include <linux/sizes.h>
93d92d46	12
513cfacc	13	#include "../soc-info.h"
93d92d46 MY	14	#include "ddrmphy-regs.h"
	15
	16	/* Select either decimal or hexadecimal */
	17	#if 1
	18	#define PRINTF_FORMAT "%2d"
	19	#else
	20	#define PRINTF_FORMAT "%02x"
	21	#endif
	22	/* field separator */
	23	#define FS " "
	24
513cfacc MY	25	#define ptr_to_uint(p) ((unsigned int)(unsigned long)(p))
	26
	27	#define UNIPHIER_MAX_NR_DDRMPHY 3
	28
	29	struct uniphier_ddrmphy_param {
	30	unsigned int soc_id;
	31	unsigned int nr_phy;
	32	struct {
	33	resource_size_t base;
	34	unsigned int nr_zq;
	35	unsigned int nr_dx;
	36	} phy[UNIPHIER_MAX_NR_DDRMPHY];
	37	};
	38
	39	static const struct uniphier_ddrmphy_param uniphier_ddrmphy_param[] = {
	40	{
	41	.soc_id = UNIPHIER_PXS2_ID,
	42	.nr_phy = 3,
	43	.phy = {
	44	{ .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
	45	{ .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
	46	{ .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
	47	},
	48	},
	49	{
	50	.soc_id = UNIPHIER_LD6B_ID,
	51	.nr_phy = 3,
	52	.phy = {
	53	{ .base = 0x5b830000, .nr_zq = 3, .nr_dx = 4, },
	54	{ .base = 0x5ba30000, .nr_zq = 3, .nr_dx = 4, },
	55	{ .base = 0x5bc30000, .nr_zq = 2, .nr_dx = 2, },
	56	},
	57	},
	58	};
	59	UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_ddrmphy_param, uniphier_ddrmphy_param)
93d92d46 MY	60
	61	static void print_bdl(void __iomem *reg, int n)
	62	{
	63	u32 val = readl(reg);
	64	int i;
	65
	66	for (i = 0; i < n; i++)
	67	printf(FS PRINTF_FORMAT, (val >> i * 8) & 0x1f);
	68	}
	69
513cfacc MY	70	static void dump_loop(const struct uniphier_ddrmphy_param *param,
513cfacc MY	71	void (callback)(void __iomem ))
93d92d46	72	{
513cfacc MY	73	void __iomem phy_base, dx_base;
513cfacc MY	74	int phy, dx;
93d92d46	75
513cfacc MY	76	for (phy = 0; phy < param->nr_phy; phy++) {
	77	phy_base = ioremap(param->phy[phy].base, SZ_4K);
	78	dx_base = phy_base + MPHY_DX_BASE;
93d92d46	79
513cfacc MY	80	for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
513cfacc MY	81	printf("PHY%dDX%d:", phy, dx);
93d92d46	82	(*callback)(dx_base);
fada9eaf	83	dx_base += MPHY_DX_STRIDE;
93d92d46 MY	84	printf("\n");
93d92d46 MY	85	}
513cfacc MY	86
513cfacc MY	87	iounmap(phy_base);
93d92d46 MY	88	}
	89	}
	90
513cfacc	91	static void zq_dump(const struct uniphier_ddrmphy_param *param)
93d92d46	92	{
513cfacc MY	93	void __iomem phy_base, zq_base;
	94	u32 val;
	95	int phy, zq, i;
93d92d46 MY	96
93d92d46 MY	97	printf("\n--- Impedance Data ---\n");
513cfacc	98	printf(" ZPD ZPU OPD OPU ZDV ODV\n");
93d92d46	99
513cfacc MY	100	for (phy = 0; phy < param->nr_phy; phy++) {
	101	phy_base = ioremap(param->phy[phy].base, SZ_4K);
	102	zq_base = phy_base + MPHY_ZQ_BASE;
93d92d46	103
513cfacc MY	104	for (zq = 0; zq < param->phy[phy].nr_zq; zq++) {
513cfacc MY	105	printf("PHY%dZQ%d:", phy, zq);
93d92d46	106
513cfacc	107	val = readl(zq_base + MPHY_ZQ_DR);
93d92d46	108	for (i = 0; i < 4; i++) {
513cfacc MY	109	printf(FS PRINTF_FORMAT, val & 0x7f);
513cfacc MY	110	val >>= 7;
93d92d46 MY	111	}
93d92d46 MY	112
513cfacc	113	val = readl(zq_base + MPHY_ZQ_PR);
93d92d46	114	for (i = 0; i < 2; i++) {
513cfacc MY	115	printf(FS PRINTF_FORMAT, val & 0xf);
513cfacc MY	116	val >>= 4;
93d92d46 MY	117	}
93d92d46 MY	118
fada9eaf	119	zq_base += MPHY_ZQ_STRIDE;
93d92d46 MY	120	printf("\n");
93d92d46 MY	121	}
513cfacc MY	122
513cfacc MY	123	iounmap(phy_base);
93d92d46 MY	124	}
	125	}
	126
	127	static void __wbdl_dump(void __iomem *dx_base)
	128	{
fada9eaf MY	129	print_bdl(dx_base + MPHY_DX_BDLR0, 4);
	130	print_bdl(dx_base + MPHY_DX_BDLR1, 4);
	131	print_bdl(dx_base + MPHY_DX_BDLR2, 2);
93d92d46 MY	132
93d92d46 MY	133	printf(FS "(+" PRINTF_FORMAT ")",
fada9eaf	134	readl(dx_base + MPHY_DX_LCDLR1) & 0xff);
93d92d46 MY	135	}
93d92d46 MY	136
513cfacc	137	static void wbdl_dump(const struct uniphier_ddrmphy_param *param)
93d92d46 MY	138	{
93d92d46 MY	139	printf("\n--- Write Bit Delay Line ---\n");
513cfacc	140	printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
93d92d46	141
513cfacc	142	dump_loop(param, &__wbdl_dump);
93d92d46 MY	143	}
	144
	145	static void __rbdl_dump(void __iomem *dx_base)
	146	{
fada9eaf MY	147	print_bdl(dx_base + MPHY_DX_BDLR3, 4);
	148	print_bdl(dx_base + MPHY_DX_BDLR4, 4);
	149	print_bdl(dx_base + MPHY_DX_BDLR5, 1);
93d92d46 MY	150
93d92d46 MY	151	printf(FS "(+" PRINTF_FORMAT ")",
fada9eaf	152	(readl(dx_base + MPHY_DX_LCDLR1) >> 8) & 0xff);
93d92d46 MY	153
93d92d46 MY	154	printf(FS "(+" PRINTF_FORMAT ")",
fada9eaf	155	(readl(dx_base + MPHY_DX_LCDLR1) >> 16) & 0xff);
93d92d46 MY	156	}
93d92d46 MY	157
513cfacc	158	static void rbdl_dump(const struct uniphier_ddrmphy_param *param)
93d92d46 MY	159	{
93d92d46 MY	160	printf("\n--- Read Bit Delay Line ---\n");
513cfacc	161	printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD) (RDQSND)\n");
93d92d46	162
513cfacc	163	dump_loop(param, &__rbdl_dump);
93d92d46 MY	164	}
	165
	166	static void __wld_dump(void __iomem *dx_base)
	167	{
	168	int rank;
fada9eaf MY	169	u32 lcdlr0 = readl(dx_base + MPHY_DX_LCDLR0);
fada9eaf MY	170	u32 gtr = readl(dx_base + MPHY_DX_GTR);
93d92d46 MY	171
	172	for (rank = 0; rank < 4; rank++) {
	173	u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
	174	u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
	175
	176	printf(FS PRINTF_FORMAT "%sT", wld,
	177	wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
	178	}
	179	}
	180
513cfacc	181	static void wld_dump(const struct uniphier_ddrmphy_param *param)
93d92d46 MY	182	{
93d92d46 MY	183	printf("\n--- Write Leveling Delay ---\n");
513cfacc	184	printf(" Rank0 Rank1 Rank2 Rank3\n");
93d92d46	185
513cfacc	186	dump_loop(param, &__wld_dump);
93d92d46 MY	187	}
	188
	189	static void __dqsgd_dump(void __iomem *dx_base)
	190	{
	191	int rank;
fada9eaf MY	192	u32 lcdlr2 = readl(dx_base + MPHY_DX_LCDLR2);
fada9eaf MY	193	u32 gtr = readl(dx_base + MPHY_DX_GTR);
93d92d46 MY	194
	195	for (rank = 0; rank < 4; rank++) {
	196	u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
	197	u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
	198
	199	printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
	200	}
	201	}
	202
513cfacc	203	static void dqsgd_dump(const struct uniphier_ddrmphy_param *param)
93d92d46 MY	204	{
93d92d46 MY	205	printf("\n--- DQS Gating Delay ---\n");
513cfacc	206	printf(" Rank0 Rank1 Rank2 Rank3\n");
93d92d46	207
513cfacc	208	dump_loop(param, &__dqsgd_dump);
93d92d46 MY	209	}
	210
	211	static void __mdl_dump(void __iomem *dx_base)
	212	{
	213	int i;
fada9eaf	214	u32 mdl = readl(dx_base + MPHY_DX_MDLR);
93d92d46 MY	215
	216	for (i = 0; i < 3; i++)
	217	printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
	218	}
	219
513cfacc	220	static void mdl_dump(const struct uniphier_ddrmphy_param *param)
93d92d46 MY	221	{
93d92d46 MY	222	printf("\n--- Master Delay Line ---\n");
513cfacc	223	printf(" IPRD TPRD MDLD\n");
93d92d46	224
513cfacc	225	dump_loop(param, &__mdl_dump);
93d92d46 MY	226	}
	227
	228	#define REG_DUMP(x) \
fada9eaf	229	{ int ofst = MPHY_ ## x; void __iomem *reg = phy_base + ofst; \
93d92d46	230	printf("%3d: %-10s: %p : %08x\n", \
fada9eaf	231	ofst >> MPHY_SHIFT, #x, reg, readl(reg)); }
93d92d46 MY	232
93d92d46 MY	233	#define DX_REG_DUMP(dx, x) \
fada9eaf MY	234	{ int ofst = MPHY_DX_BASE + MPHY_DX_STRIDE * (dx) + \
fada9eaf MY	235	MPHY_DX_## x; \
93d92d46 MY	236	void __iomem *reg = phy_base + ofst; \
93d92d46 MY	237	printf("%3d: DX%d%-7s: %p : %08x\n", \
fada9eaf	238	ofst >> MPHY_SHIFT, (dx), #x, reg, readl(reg)); }
93d92d46	239
513cfacc	240	static void reg_dump(const struct uniphier_ddrmphy_param *param)
93d92d46	241	{
93d92d46	242	void __iomem *phy_base;
513cfacc	243	int phy, dx;
93d92d46	244
513cfacc	245	printf("\n--- DDR Multi PHY registers ---\n");
93d92d46	246
513cfacc MY	247	for (phy = 0; phy < param->nr_phy; phy++) {
513cfacc MY	248	phy_base = ioremap(param->phy[phy].base, SZ_4K);
93d92d46	249
513cfacc MY	250	printf("== PHY%d (base: %08x) ==\n", phy,
513cfacc MY	251	ptr_to_uint(phy_base));
93d92d46 MY	252	printf(" No: Name : Address : Data\n");
	253
	254	REG_DUMP(RIDR);
	255	REG_DUMP(PIR);
	256	REG_DUMP(PGCR0);
	257	REG_DUMP(PGCR1);
	258	REG_DUMP(PGCR2);
	259	REG_DUMP(PGCR3);
	260	REG_DUMP(PGSR0);
	261	REG_DUMP(PGSR1);
	262	REG_DUMP(PLLCR);
	263	REG_DUMP(PTR0);
	264	REG_DUMP(PTR1);
	265	REG_DUMP(PTR2);
	266	REG_DUMP(PTR3);
	267	REG_DUMP(PTR4);
	268	REG_DUMP(ACMDLR);
	269	REG_DUMP(ACBDLR0);
	270	REG_DUMP(DXCCR);
	271	REG_DUMP(DSGCR);
	272	REG_DUMP(DCR);
	273	REG_DUMP(DTPR0);
	274	REG_DUMP(DTPR1);
	275	REG_DUMP(DTPR2);
	276	REG_DUMP(DTPR3);
	277	REG_DUMP(MR0);
	278	REG_DUMP(MR1);
	279	REG_DUMP(MR2);
	280	REG_DUMP(MR3);
	281
513cfacc	282	for (dx = 0; dx < param->phy[phy].nr_dx; dx++) {
93d92d46 MY	283	DX_REG_DUMP(dx, GCR0);
	284	DX_REG_DUMP(dx, GCR1);
	285	DX_REG_DUMP(dx, GCR2);
	286	DX_REG_DUMP(dx, GCR3);
	287	DX_REG_DUMP(dx, GTR);
	288	}
513cfacc MY	289
513cfacc MY	290	iounmap(phy_base);
93d92d46 MY	291	}
	292	}
	293
	294	static int do_ddrm(cmd_tbl_t cmdtp, int flag, int argc, char const argv[])
	295	{
513cfacc MY	296	const struct uniphier_ddrmphy_param *param;
	297	char *cmd;
	298
	299	param = uniphier_get_ddrmphy_param();
	300	if (!param) {
dd74b945	301	pr_err("unsupported SoC\n");
513cfacc MY	302	return CMD_RET_FAILURE;
513cfacc MY	303	}
93d92d46 MY	304
	305	if (argc == 1)
	306	cmd = "all";
513cfacc MY	307	else
513cfacc MY	308	cmd = argv[1];
93d92d46 MY	309
93d92d46 MY	310	if (!strcmp(cmd, "zq") \|\| !strcmp(cmd, "all"))
513cfacc	311	zq_dump(param);
93d92d46 MY	312
93d92d46 MY	313	if (!strcmp(cmd, "wbdl") \|\| !strcmp(cmd, "all"))
513cfacc	314	wbdl_dump(param);
93d92d46 MY	315
93d92d46 MY	316	if (!strcmp(cmd, "rbdl") \|\| !strcmp(cmd, "all"))
513cfacc	317	rbdl_dump(param);
93d92d46 MY	318
93d92d46 MY	319	if (!strcmp(cmd, "wld") \|\| !strcmp(cmd, "all"))
513cfacc	320	wld_dump(param);
93d92d46 MY	321
93d92d46 MY	322	if (!strcmp(cmd, "dqsgd") \|\| !strcmp(cmd, "all"))
513cfacc	323	dqsgd_dump(param);
93d92d46 MY	324
93d92d46 MY	325	if (!strcmp(cmd, "mdl") \|\| !strcmp(cmd, "all"))
513cfacc	326	mdl_dump(param);
93d92d46 MY	327
93d92d46 MY	328	if (!strcmp(cmd, "reg") \|\| !strcmp(cmd, "all"))
513cfacc	329	reg_dump(param);
93d92d46	330
513cfacc	331	return CMD_RET_SUCCESS;
93d92d46 MY	332	}
	333
	334	U_BOOT_CMD(
	335	ddrm, 2, 1, do_ddrm,
513cfacc	336	"UniPhier DDR Multi PHY parameters dumper",
c21fc7e2	337	"- dump all of the following\n"
93d92d46 MY	338	"ddrm zq - dump Impedance Data\n"
	339	"ddrm wbdl - dump Write Bit Delay\n"
	340	"ddrm rbdl - dump Read Bit Delay\n"
	341	"ddrm wld - dump Write Leveling\n"
	342	"ddrm dqsgd - dump DQS Gating Delay\n"
	343	"ddrm mdl - dump Master Delay Line\n"
	344	"ddrm reg - dump registers\n"
	345	);