[thirdparty/u-boot.git] / arch / arm / mach-uniphier / dram_init.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2012-2015 Panasonic Corporation
 * Copyright (C) 2015-2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 */

#include <common.h>
#include <linux/errno.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/printk.h>
#include <linux/sizes.h>
#include <asm/global_data.h>

#include "sg-regs.h"
#include "soc-info.h"

DECLARE_GLOBAL_DATA_PTR;

struct uniphier_memif_data {
	unsigned int soc_id;
	unsigned long sparse_ch1_base;
	int have_ch2;
};

static const struct uniphier_memif_data uniphier_memif_data[] = {
	{
		.soc_id = UNIPHIER_LD4_ID,
		.sparse_ch1_base = 0xc0000000,
	},
	{
		.soc_id = UNIPHIER_PRO4_ID,
		.sparse_ch1_base = 0xa0000000,
	},
	{
		.soc_id = UNIPHIER_SLD8_ID,
		.sparse_ch1_base = 0xc0000000,
	},
	{
		.soc_id = UNIPHIER_PRO5_ID,
		.sparse_ch1_base = 0xc0000000,
	},
	{
		.soc_id = UNIPHIER_PXS2_ID,
		.sparse_ch1_base = 0xc0000000,
		.have_ch2 = 1,
	},
	{
		.soc_id = UNIPHIER_LD6B_ID,
		.sparse_ch1_base = 0xc0000000,
		.have_ch2 = 1,
	},
	{
		.soc_id = UNIPHIER_LD11_ID,
		.sparse_ch1_base = 0xc0000000,
	},
	{
		.soc_id = UNIPHIER_LD20_ID,
		.sparse_ch1_base = 0xc0000000,
		.have_ch2 = 1,
	},
	{
		.soc_id = UNIPHIER_PXS3_ID,
		.sparse_ch1_base = 0xc0000000,
		.have_ch2 = 1,
	},
};
UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)

struct uniphier_dram_map {
	unsigned long base;
	unsigned long size;
};

static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
{
	const struct uniphier_memif_data *data;
	unsigned long size;
	u32 val;

	data = uniphier_get_memif_data();
	if (!data) {
		pr_err("unsupported SoC\n");
		return -EINVAL;
	}

	val = readl(SG_MEMCONF);

	/* set up ch0 */
	dram_map[0].base = CONFIG_SYS_SDRAM_BASE;

	switch (val & SG_MEMCONF_CH0_SZ_MASK) {
	case SG_MEMCONF_CH0_SZ_64M:
		size = SZ_64M;
		break;
	case SG_MEMCONF_CH0_SZ_128M:
		size = SZ_128M;
		break;
	case SG_MEMCONF_CH0_SZ_256M:
		size = SZ_256M;
		break;
	case SG_MEMCONF_CH0_SZ_512M:
		size = SZ_512M;
		break;
	case SG_MEMCONF_CH0_SZ_1G:
		size = SZ_1G;
		break;
	default:
		pr_err("error: invalid value is set to MEMCONF ch0 size\n");
		return -EINVAL;
	}

	if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
		size *= 2;

	dram_map[0].size = size;

	/* set up ch1 */
	dram_map[1].base = dram_map[0].base + size;

	if (val & SG_MEMCONF_SPARSEMEM) {
		if (dram_map[1].base > data->sparse_ch1_base) {
			pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
			pr_warn("Only ch0 is available\n");
			dram_map[1].base = 0;
			return 0;
		}

		dram_map[1].base = data->sparse_ch1_base;
	}

	switch (val & SG_MEMCONF_CH1_SZ_MASK) {
	case SG_MEMCONF_CH1_SZ_64M:
		size = SZ_64M;
		break;
	case SG_MEMCONF_CH1_SZ_128M:
		size = SZ_128M;
		break;
	case SG_MEMCONF_CH1_SZ_256M:
		size = SZ_256M;
		break;
	case SG_MEMCONF_CH1_SZ_512M:
		size = SZ_512M;
		break;
	case SG_MEMCONF_CH1_SZ_1G:
		size = SZ_1G;
		break;
	default:
		pr_err("error: invalid value is set to MEMCONF ch1 size\n");
		return -EINVAL;
	}

	if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
		size *= 2;

	dram_map[1].size = size;

	if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
		return 0;

	/* set up ch2 */
	dram_map[2].base = dram_map[1].base + size;

	switch (val & SG_MEMCONF_CH2_SZ_MASK) {
	case SG_MEMCONF_CH2_SZ_64M:
		size = SZ_64M;
		break;
	case SG_MEMCONF_CH2_SZ_128M:
		size = SZ_128M;
		break;
	case SG_MEMCONF_CH2_SZ_256M:
		size = SZ_256M;
		break;
	case SG_MEMCONF_CH2_SZ_512M:
		size = SZ_512M;
		break;
	case SG_MEMCONF_CH2_SZ_1G:
		size = SZ_1G;
		break;
	default:
		pr_err("error: invalid value is set to MEMCONF ch2 size\n");
		return -EINVAL;
	}

	if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
		size *= 2;

	dram_map[2].size = size;

	return 0;
}

int dram_init(void)
{
	struct uniphier_dram_map dram_map[3] = {};
	int ret, i;

	gd->ram_size = 0;

	ret = uniphier_memconf_decode(dram_map);
	if (ret)
		return ret;

	for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
		unsigned long max_size;

		if (!dram_map[i].size)
			break;

		/*
		 * U-Boot relocates itself to the tail of the memory region,
		 * but it does not expect sparse memory.  We use the first
		 * contiguous chunk here.
		 */
		if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
							dram_map[i].base)
			break;

		/*
		 * Do not use memory that exceeds 32bit address range.  U-Boot
		 * relocates itself to the end of the effectively available RAM.
		 * This could be a problem for DMA engines that do not support
		 * 64bit address (SDMA of SDHCI, UniPhier AV-ether, etc.)
		 */
		if (dram_map[i].base >= 1ULL << 32)
			break;

		max_size = (1ULL << 32) - dram_map[i].base;

		if (dram_map[i].size > max_size) {
			gd->ram_size += max_size;
			break;
		}

		gd->ram_size += dram_map[i].size;
	}

	/*
	 * LD20 uses the last 64 byte for each channel for dynamic
	 * DDR PHY training
	 */
	if (uniphier_get_soc_id() == UNIPHIER_LD20_ID)
		gd->ram_size -= 64;

	return 0;
}

int dram_init_banksize(void)
{
	struct uniphier_dram_map dram_map[3] = {};
	int i;

	uniphier_memconf_decode(dram_map);

	for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
		if (i >= ARRAY_SIZE(gd->bd->bi_dram))
			break;

		gd->bd->bi_dram[i].start = dram_map[i].base;
		gd->bd->bi_dram[i].size = dram_map[i].size;
	}

	return 0;
}
Commit	Line	Data
83d290c5	1	// SPDX-License-Identifier: GPL-2.0+
5894ca00	2	/*
3e9952be MY	3	* Copyright (C) 2012-2015 Panasonic Corporation
	4	* Copyright (C) 2015-2017 Socionext Inc.
	5	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	6	*/
	7
	8	#include <common.h>
0f4ec05b	9	#include <linux/errno.h>
3b7fc3ff	10	#include <linux/io.h>
dd74b945 MY	11	#include <linux/kernel.h>
dd74b945 MY	12	#include <linux/printk.h>
3e9952be	13	#include <linux/sizes.h>
dd74b945	14	#include <asm/global_data.h>
cf88affa	15
3e9952be	16	#include "sg-regs.h"
51ea5a06 MY	17	#include "soc-info.h"
51ea5a06 MY	18
cf88affa MY	19	DECLARE_GLOBAL_DATA_PTR;
cf88affa MY	20
3e9952be MY	21	struct uniphier_memif_data {
	22	unsigned int soc_id;
	23	unsigned long sparse_ch1_base;
	24	int have_ch2;
	25	};
	26
	27	static const struct uniphier_memif_data uniphier_memif_data[] = {
3e9952be MY	28	{
	29	.soc_id = UNIPHIER_LD4_ID,
	30	.sparse_ch1_base = 0xc0000000,
	31	},
	32	{
	33	.soc_id = UNIPHIER_PRO4_ID,
	34	.sparse_ch1_base = 0xa0000000,
	35	},
	36	{
	37	.soc_id = UNIPHIER_SLD8_ID,
	38	.sparse_ch1_base = 0xc0000000,
	39	},
	40	{
	41	.soc_id = UNIPHIER_PRO5_ID,
	42	.sparse_ch1_base = 0xc0000000,
	43	},
	44	{
	45	.soc_id = UNIPHIER_PXS2_ID,
	46	.sparse_ch1_base = 0xc0000000,
	47	.have_ch2 = 1,
	48	},
	49	{
	50	.soc_id = UNIPHIER_LD6B_ID,
	51	.sparse_ch1_base = 0xc0000000,
	52	.have_ch2 = 1,
	53	},
	54	{
	55	.soc_id = UNIPHIER_LD11_ID,
	56	.sparse_ch1_base = 0xc0000000,
	57	},
	58	{
	59	.soc_id = UNIPHIER_LD20_ID,
	60	.sparse_ch1_base = 0xc0000000,
	61	.have_ch2 = 1,
	62	},
	63	{
	64	.soc_id = UNIPHIER_PXS3_ID,
	65	.sparse_ch1_base = 0xc0000000,
	66	.have_ch2 = 1,
	67	},
	68	};
	69	UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
	70
04cd4e72 MY	71	struct uniphier_dram_map {
	72	unsigned long base;
	73	unsigned long size;
	74	};
	75
	76	static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
cf88affa	77	{
3e9952be MY	78	const struct uniphier_memif_data *data;
	79	unsigned long size;
	80	u32 val;
cf88affa	81
3e9952be MY	82	data = uniphier_get_memif_data();
	83	if (!data) {
	84	pr_err("unsupported SoC\n");
	85	return -EINVAL;
	86	}
cf88affa	87
3e9952be	88	val = readl(SG_MEMCONF);
5894ca00	89
3e9952be	90	/* set up ch0 */
04cd4e72	91	dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
3e9952be MY	92
	93	switch (val & SG_MEMCONF_CH0_SZ_MASK) {
	94	case SG_MEMCONF_CH0_SZ_64M:
	95	size = SZ_64M;
	96	break;
	97	case SG_MEMCONF_CH0_SZ_128M:
	98	size = SZ_128M;
	99	break;
	100	case SG_MEMCONF_CH0_SZ_256M:
	101	size = SZ_256M;
	102	break;
	103	case SG_MEMCONF_CH0_SZ_512M:
	104	size = SZ_512M;
	105	break;
	106	case SG_MEMCONF_CH0_SZ_1G:
	107	size = SZ_1G;
	108	break;
	109	default:
0f5bf09c	110	pr_err("error: invalid value is set to MEMCONF ch0 size\n");
cf88affa	111	return -EINVAL;
ac2a1030 MY	112	}
ac2a1030 MY	113
3e9952be MY	114	if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
	115	size *= 2;
	116
04cd4e72	117	dram_map[0].size = size;
3e9952be MY	118
3e9952be MY	119	/* set up ch1 */
04cd4e72	120	dram_map[1].base = dram_map[0].base + size;
3e9952be MY	121
3e9952be MY	122	if (val & SG_MEMCONF_SPARSEMEM) {
04cd4e72	123	if (dram_map[1].base > data->sparse_ch1_base) {
3e9952be MY	124	pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
3e9952be MY	125	pr_warn("Only ch0 is available\n");
04cd4e72	126	dram_map[1].base = 0;
3e9952be MY	127	return 0;
	128	}
	129
04cd4e72	130	dram_map[1].base = data->sparse_ch1_base;
3e9952be MY	131	}
	132
	133	switch (val & SG_MEMCONF_CH1_SZ_MASK) {
	134	case SG_MEMCONF_CH1_SZ_64M:
	135	size = SZ_64M;
	136	break;
	137	case SG_MEMCONF_CH1_SZ_128M:
	138	size = SZ_128M;
	139	break;
	140	case SG_MEMCONF_CH1_SZ_256M:
	141	size = SZ_256M;
	142	break;
	143	case SG_MEMCONF_CH1_SZ_512M:
	144	size = SZ_512M;
	145	break;
	146	case SG_MEMCONF_CH1_SZ_1G:
	147	size = SZ_1G;
	148	break;
	149	default:
0f5bf09c	150	pr_err("error: invalid value is set to MEMCONF ch1 size\n");
ac2a1030	151	return -EINVAL;
3e9952be MY	152	}
	153
	154	if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
	155	size *= 2;
ac2a1030	156
04cd4e72	157	dram_map[1].size = size;
cf88affa	158
bed1624d	159	if (!data->have_ch2 \|\| val & SG_MEMCONF_CH2_DISABLE)
3e9952be	160	return 0;
cf88affa	161
3e9952be	162	/* set up ch2 */
04cd4e72	163	dram_map[2].base = dram_map[1].base + size;
3e9952be MY	164
	165	switch (val & SG_MEMCONF_CH2_SZ_MASK) {
	166	case SG_MEMCONF_CH2_SZ_64M:
	167	size = SZ_64M;
	168	break;
	169	case SG_MEMCONF_CH2_SZ_128M:
	170	size = SZ_128M;
	171	break;
	172	case SG_MEMCONF_CH2_SZ_256M:
	173	size = SZ_256M;
	174	break;
	175	case SG_MEMCONF_CH2_SZ_512M:
	176	size = SZ_512M;
	177	break;
	178	case SG_MEMCONF_CH2_SZ_1G:
	179	size = SZ_1G;
	180	break;
	181	default:
0f5bf09c	182	pr_err("error: invalid value is set to MEMCONF ch2 size\n");
3e9952be MY	183	return -EINVAL;
	184	}
	185
	186	if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
	187	size *= 2;
	188
04cd4e72	189	dram_map[2].size = size;
5894ca00	190
5894ca00 MY	191	return 0;
5894ca00 MY	192	}
cf88affa	193
3e9952be	194	int dram_init(void)
cf88affa	195	{
04cd4e72	196	struct uniphier_dram_map dram_map[3] = {};
3e9952be MY	197	int ret, i;
	198
	199	gd->ram_size = 0;
	200
04cd4e72	201	ret = uniphier_memconf_decode(dram_map);
3e9952be MY	202	if (ret)
	203	return ret;
	204
04cd4e72	205	for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
be893a5c	206	unsigned long max_size;
3e9952be	207
04cd4e72	208	if (!dram_map[i].size)
3e9952be MY	209	break;
	210
	211	/*
	212	* U-Boot relocates itself to the tail of the memory region,
	213	* but it does not expect sparse memory. We use the first
	214	* contiguous chunk here.
	215	*/
04cd4e72 MY	216	if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
04cd4e72 MY	217	dram_map[i].base)
3e9952be MY	218	break;
3e9952be MY	219
be893a5c MY	220	/*
	221	* Do not use memory that exceeds 32bit address range. U-Boot
	222	* relocates itself to the end of the effectively available RAM.
	223	* This could be a problem for DMA engines that do not support
	224	* 64bit address (SDMA of SDHCI, UniPhier AV-ether, etc.)
	225	*/
	226	if (dram_map[i].base >= 1ULL << 32)
	227	break;
	228
	229	max_size = (1ULL << 32) - dram_map[i].base;
	230
	231	if (dram_map[i].size > max_size) {
	232	gd->ram_size += max_size;
	233	break;
	234	}
	235
04cd4e72	236	gd->ram_size += dram_map[i].size;
ac2a1030 MY	237	}
ac2a1030 MY	238
a322eb9f MY	239	/*
	240	* LD20 uses the last 64 byte for each channel for dynamic
	241	* DDR PHY training
	242	*/
	243	if (uniphier_get_soc_id() == UNIPHIER_LD20_ID)
	244	gd->ram_size -= 64;
	245
3e9952be MY	246	return 0;
	247	}
	248
76b00aca	249	int dram_init_banksize(void)
3e9952be	250	{
04cd4e72	251	struct uniphier_dram_map dram_map[3] = {};
3e9952be	252	int i;
ac2a1030	253
04cd4e72	254	uniphier_memconf_decode(dram_map);
cf88affa	255
04cd4e72	256	for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
3e9952be MY	257	if (i >= ARRAY_SIZE(gd->bd->bi_dram))
3e9952be MY	258	break;
cf88affa	259
04cd4e72 MY	260	gd->bd->bi_dram[i].start = dram_map[i].base;
04cd4e72 MY	261	gd->bd->bi_dram[i].size = dram_map[i].size;
cf88affa	262	}
76b00aca SG	263
76b00aca SG	264	return 0;
cf88affa	265	}