projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5894ca00 MY |
1 | /* |
| 2 | * UniPhier SC (System Control) block registers | |
| 3 | * | |
| 3365b4eb | 4 | * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
| 5894ca00 MY |
5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ | |
| 7 | */ | |
| 8 | ||
| 9 | #ifndef ARCH_SC_REGS_H | |
| 10 | #define ARCH_SC_REGS_H | |
| 11 | ||
| 8497ccc4 | 12 | #if defined(CONFIG_ARCH_UNIPHIER_PH1_SLD3) |
| 3365b4eb MY |
13 | #define SC_BASE_ADDR 0xf1840000 |
| 14 | #else | |
| 5894ca00 | 15 | #define SC_BASE_ADDR 0x61840000 |
| 3365b4eb | 16 | #endif |
| 5894ca00 | 17 | |
| 5894ca00 MY |
18 | #define SC_DPLLCTRL (SC_BASE_ADDR | 0x1200) |
| 19 | #define SC_DPLLCTRL_SSC_EN (0x1 << 31) | |
| 20 | #define SC_DPLLCTRL_FOUTMODE_MASK (0xf << 16) | |
| 21 | #define SC_DPLLCTRL_SSC_RATE (0x1 << 15) | |
| 22 | ||
| 23 | #define SC_DPLLCTRL2 (SC_BASE_ADDR | 0x1204) | |
| 24 | #define SC_DPLLCTRL2_NRSTDS (0x1 << 28) | |
| 25 | ||
| 26 | #define SC_DPLLCTRL3 (SC_BASE_ADDR | 0x1208) | |
| 27 | #define SC_DPLLCTRL3_LPFSEL_COEF2 (0x0 << 31) | |
| 28 | #define SC_DPLLCTRL3_LPFSEL_COEF3 (0x1 << 31) | |
| 29 | ||
| 30 | #define SC_UPLLCTRL (SC_BASE_ADDR | 0x1210) | |
| 31 | ||
| 32 | #define SC_VPLL27ACTRL (SC_BASE_ADDR | 0x1270) | |
| 33 | #define SC_VPLL27ACTRL2 (SC_BASE_ADDR | 0x1274) | |
| 34 | #define SC_VPLL27ACTRL3 (SC_BASE_ADDR | 0x1278) | |
| 35 | ||
| 36 | #define SC_VPLL27BCTRL (SC_BASE_ADDR | 0x1290) | |
| 37 | #define SC_VPLL27BCTRL2 (SC_BASE_ADDR | 0x1294) | |
| 38 | #define SC_VPLL27BCTRL3 (SC_BASE_ADDR | 0x1298) | |
| 39 | ||
| 40 | #define SC_RSTCTRL (SC_BASE_ADDR | 0x2000) | |
| 1535163a MY |
41 | #define SC_RSTCTRL_NRST_USB3B0 (0x1 << 17) /* USB3 #0 bus */ |
| 42 | #define SC_RSTCTRL_NRST_USB3C0 (0x1 << 16) /* USB3 #0 core */ | |
| 5894ca00 | 43 | #define SC_RSTCTRL_NRST_ETHER (0x1 << 12) |
| 42ca6982 | 44 | #define SC_RSTCTRL_NRST_STDMAC (0x1 << 10) |
| 1535163a | 45 | #define SC_RSTCTRL_NRST_GIO (0x1 << 6) |
| 5894ca00 MY |
46 | #define SC_RSTCTRL_NRST_UMC1 (0x1 << 5) |
| 47 | #define SC_RSTCTRL_NRST_UMC0 (0x1 << 4) | |
| 48 | #define SC_RSTCTRL_NRST_NAND (0x1 << 2) | |
| 49 | ||
| 50 | #define SC_RSTCTRL2 (SC_BASE_ADDR | 0x2004) | |
| 1535163a MY |
51 | #define SC_RSTCTRL2_NRST_USB3B1 (0x1 << 17) /* USB3 #1 bus */ |
| 52 | #define SC_RSTCTRL2_NRST_USB3C1 (0x1 << 16) /* USB3 #1 core */ | |
| 53 | ||
| 5894ca00 MY |
54 | #define SC_RSTCTRL3 (SC_BASE_ADDR | 0x2008) |
| 55 | ||
| 56 | #define SC_CLKCTRL (SC_BASE_ADDR | 0x2104) | |
| 1535163a MY |
57 | #define SC_CLKCTRL_CEN_USB31 (0x1 << 17) /* USB3 #1 */ |
| 58 | #define SC_CLKCTRL_CEN_USB30 (0x1 << 16) /* USB3 #0 */ | |
| f267b81e MY |
59 | #define SC_CLKCTRL_CEN_ETHER (0x1 << 12) |
| 60 | #define SC_CLKCTRL_CEN_MIO (0x1 << 11) | |
| 42ca6982 | 61 | #define SC_CLKCTRL_CEN_STDMAC (0x1 << 10) |
| 1535163a | 62 | #define SC_CLKCTRL_CEN_GIO (0x1 << 6) |
| f267b81e MY |
63 | #define SC_CLKCTRL_CEN_UMC (0x1 << 4) |
| 64 | #define SC_CLKCTRL_CEN_NAND (0x1 << 2) | |
| 65 | #define SC_CLKCTRL_CEN_SBC (0x1 << 1) | |
| 66 | #define SC_CLKCTRL_CEN_PERI (0x1 << 0) | |
| 5894ca00 MY |
67 | |
| 68 | /* System reset control register */ | |
| 69 | #define SC_IRQTIMSET (SC_BASE_ADDR | 0x3000) | |
| 70 | #define SC_SLFRSTSEL (SC_BASE_ADDR | 0x3010) | |
| 71 | #define SC_SLFRSTCTL (SC_BASE_ADDR | 0x3014) | |
| 72 | ||
| 73 | #endif /* ARCH_SC_REGS_H */ |