]>
Commit | Line | Data |
---|---|---|
5894ca00 | 1 | /* |
9fc5f9da | 2 | * Copyright (C) 2012-2015 Masahiro Yamada <yamada.masahiro@socionext.com> |
5894ca00 MY |
3 | * |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <config.h> | |
8 | #include <linux/linkage.h> | |
105a9e70 | 9 | #include <linux/sizes.h> |
5894ca00 | 10 | #include <asm/system.h> |
107b3fb4 MY |
11 | |
12 | #include "ssc-regs.h" | |
5894ca00 MY |
13 | |
14 | ENTRY(lowlevel_init) | |
15 | mov r8, lr @ persevere link reg across call | |
16 | ||
17 | /* | |
18 | * The UniPhier Boot ROM loads SPL code to the L2 cache. | |
19 | * But CPUs can only do instruction fetch now because start.S has | |
20 | * cleared C and M bits. | |
21 | * First we need to turn on MMU and Dcache again to get back | |
22 | * data access to L2. | |
23 | */ | |
4d13b1b7 MY |
24 | mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) |
25 | orr r0, r0, #(CR_C | CR_M) @ enable MMU and Dcache | |
5894ca00 MY |
26 | mcr p15, 0, r0, c1, c0, 0 |
27 | ||
b4ad44ba | 28 | #ifdef CONFIG_DEBUG_LL |
e6eecca5 | 29 | bl debug_ll_init |
b4ad44ba MY |
30 | #endif |
31 | ||
5894ca00 MY |
32 | /* |
33 | * Now we are using the page table embedded in the Boot ROM. | |
34 | * It is not handy since it is not a straight mapped table for sLD3. | |
35 | * What we need to do next is to switch over to the page table in SPL. | |
36 | */ | |
37 | ldr r3, =init_page_table @ page table must be 16KB aligned | |
38 | ||
39 | /* Disable MMU and Dcache before switching Page Table */ | |
4d13b1b7 | 40 | mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) |
5894ca00 MY |
41 | bic r0, r0, #(CR_C | CR_M) @ disable MMU and Dcache |
42 | mcr p15, 0, r0, c1, c0, 0 | |
43 | ||
44 | bl enable_mmu | |
45 | ||
5894ca00 MY |
46 | bl setup_init_ram @ RAM area for temporary stack pointer |
47 | ||
48 | mov lr, r8 @ restore link | |
49 | mov pc, lr @ back to my caller | |
50 | ENDPROC(lowlevel_init) | |
51 | ||
52 | ENTRY(enable_mmu) | |
53 | mrc p15, 0, r0, c2, c0, 2 @ TTBCR (Translation Table Base Control Register) | |
54 | bic r0, r0, #0x37 | |
55 | orr r0, r0, #0x20 @ disable TTBR1 | |
56 | mcr p15, 0, r0, c2, c0, 2 | |
57 | ||
58 | orr r0, r3, #0x8 @ Outer Cacheability for table walks: WBWA | |
59 | mcr p15, 0, r0, c2, c0, 0 @ TTBR0 | |
60 | ||
61 | mov r0, #0 | |
62 | mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs | |
63 | ||
64 | mov r0, #-1 @ manager for all domains (No permission check) | |
65 | mcr p15, 0, r0, c3, c0, 0 @ DACR (Domain Access Control Register) | |
66 | ||
67 | dsb | |
68 | isb | |
69 | /* | |
70 | * MMU on: | |
71 | * TLBs was already invalidated in "../start.S" | |
72 | * So, we don't need to invalidate it here. | |
73 | */ | |
4d13b1b7 | 74 | mrc p15, 0, r0, c1, c0, 0 @ SCTLR (System Control Register) |
5894ca00 MY |
75 | orr r0, r0, #(CR_C | CR_M) @ MMU and Dcache enable |
76 | mcr p15, 0, r0, c1, c0, 0 | |
77 | ||
78 | mov pc, lr | |
79 | ENDPROC(enable_mmu) | |
80 | ||
105a9e70 MY |
81 | /* |
82 | * For PH1-Pro4 or older SoCs, the size of WAY is 32KB. | |
83 | * It is large enough for tmp RAM. | |
84 | */ | |
85 | #define BOOT_RAM_SIZE (SZ_32K) | |
5894ca00 MY |
86 | #define BOOT_WAY_BITS (0x00000100) /* way 8 */ |
87 | ||
88 | ENTRY(setup_init_ram) | |
89 | /* | |
90 | * Touch to zero for the boot way | |
91 | */ | |
92 | 0: | |
93 | /* | |
94 | * set SSCOQM, SSCOQAD, SSCOQSZ, SSCOQWN in this order | |
95 | */ | |
96 | ldr r0, = 0x00408006 @ touch to zero with address range | |
97 | ldr r1, = SSCOQM | |
98 | str r0, [r1] | |
ce3a6390 | 99 | ldr r0, = (CONFIG_SPL_STACK - BOOT_RAM_SIZE) @ base address |
5894ca00 MY |
100 | ldr r1, = SSCOQAD |
101 | str r0, [r1] | |
102 | ldr r0, = BOOT_RAM_SIZE | |
103 | ldr r1, = SSCOQSZ | |
104 | str r0, [r1] | |
105 | ldr r0, = BOOT_WAY_BITS | |
106 | ldr r1, = SSCOQWN | |
107 | str r0, [r1] | |
108 | ldr r1, = SSCOPPQSEF | |
109 | ldr r0, [r1] | |
110 | cmp r0, #0 @ check if the command is successfully set | |
4d13b1b7 | 111 | bne 0b @ try again if an error occurs |
5894ca00 MY |
112 | |
113 | ldr r1, = SSCOLPQS | |
114 | 1: | |
115 | ldr r0, [r1] | |
116 | cmp r0, #0x4 | |
117 | bne 1b @ wait until the operation is completed | |
118 | str r0, [r1] @ clear the complete notification flag | |
119 | ||
120 | mov pc, lr | |
121 | ENDPROC(setup_init_ram) |