[people/ms/u-boot.git] / arch / arm / mach-uniphier / pll / pll-init-sld8.c

/*
 * Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <linux/io.h>

#include "../init.h"
#include "../sc-regs.h"
#include "../sg-regs.h"

static void dpll_init(void)
{
	u32 tmp;
	/*
	 * Set DPLL SSC parameters for DPLLCTRL3
	 * [23]    DIVN_TEST    0x1
	 * [22:16] DIVN         0x50
	 * [10]    FREFSEL_TEST 0x1
	 * [9:8]   FREFSEL      0x2
	 * [4]     ICPD_TEST    0x1
	 * [3:0]   ICPD         0xb
	 */
	tmp = readl(SC_DPLLCTRL3);
	tmp &= ~0x00ff0717;
	tmp |= 0x00d0061b;
	writel(tmp, SC_DPLLCTRL3);

	/*
	 * Set DPLL SSC parameters for DPLLCTRL
	 *                    <-1%>          <-2%>
	 * [29:20] SSC_UPCNT 132 (0x084)    132  (0x084)
	 * [14:0]  SSC_dK    6335(0x18bf)   12710(0x31a6)
	 */
	tmp = readl(SC_DPLLCTRL);
	tmp &= ~0x3ff07fff;
#ifdef CONFIG_DPLL_SSC_RATE_1PER
	tmp |= 0x084018bf;
#else
	tmp |= 0x084031a6;
#endif
	writel(tmp, SC_DPLLCTRL);

	/*
	 * Set DPLL SSC parameters for DPLLCTRL2
	 * [31:29]  SSC_STEP     0
	 * [27]     SSC_REG_REF  1
	 * [26:20]  SSC_M        79     (0x4f)
	 * [19:0]   SSC_K        964689 (0xeb851)
	 */
	tmp = readl(SC_DPLLCTRL2);
	tmp &= ~0xefffffff;
	tmp |= 0x0cfeb851;
	writel(tmp, SC_DPLLCTRL2);
}

static void upll_init(void)
{
	u32 tmp, clk_mode_upll, clk_mode_axosel;

	tmp = readl(SG_PINMON0);
	clk_mode_upll   = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;

	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
	tmp = readl(SC_UPLLCTRL);
	tmp &= ~0x18000000;
	writel(tmp, SC_UPLLCTRL);

	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
		if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
		    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
			/* AXO: 25MHz */
			tmp &= ~0x07ffffff;
			tmp |= 0x0228f5c0;
		} else {
			/* AXO: default 24.576MHz */
			tmp &= ~0x07ffffff;
			tmp |= 0x02328000;
		}
	}

	writel(tmp, SC_UPLLCTRL);

	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
	tmp |= 0x08000000;
	writel(tmp, SC_UPLLCTRL);

	/* wait 10 usec */
	udelay(10);

	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
	tmp |= 0x10000000;
	writel(tmp, SC_UPLLCTRL);
}

static void vpll_init(void)
{
	u32 tmp, clk_mode_axosel;

	tmp = readl(SG_PINMON0);
	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;

	/* set 1 to VPLA27WP and VPLA27WP */
	tmp = readl(SC_VPLL27ACTRL);
	tmp |= 0x00000001;
	writel(tmp, SC_VPLL27ACTRL);
	tmp = readl(SC_VPLL27BCTRL);
	tmp |= 0x00000001;
	writel(tmp, SC_VPLL27BCTRL);

	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
	tmp = readl(SC_VPLL27ACTRL3);
	tmp &= ~0x10000000;
	writel(tmp, SC_VPLL27ACTRL3);
	tmp = readl(SC_VPLL27BCTRL3);
	tmp &= ~0x10000000;
	writel(tmp, SC_VPLL27BCTRL3);

	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
	tmp = readl(SC_VPLL27ACTRL2);
	tmp &= ~0x10000000;
	writel(tmp, SC_VPLL27ACTRL2);
	tmp = readl(SC_VPLL27BCTRL2);
	tmp &= ~0x10000000;
	writel(tmp, SC_VPLL27BCTRL2);

	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
	tmp = readl(SC_VPLL27ACTRL2);
	tmp &= ~0x0000007f;
	tmp |= 0x00000020;
	writel(tmp, SC_VPLL27ACTRL2);
	tmp = readl(SC_VPLL27BCTRL2);
	tmp &= ~0x0000007f;
	tmp |= 0x00000020;
	writel(tmp, SC_VPLL27BCTRL2);

	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U ||
	    clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
		/* AXO: 25MHz */
		tmp = readl(SC_VPLL27ACTRL3);
		tmp &= ~0x000fffff;
		tmp |= 0x00066664;
		writel(tmp, SC_VPLL27ACTRL3);
		tmp = readl(SC_VPLL27BCTRL3);
		tmp &= ~0x000fffff;
		tmp |= 0x00066664;
		writel(tmp, SC_VPLL27BCTRL3);
	} else {
		/* AXO: default 24.576MHz */
		tmp = readl(SC_VPLL27ACTRL3);
		tmp &= ~0x000fffff;
		tmp |= 0x000f5800;
		writel(tmp, SC_VPLL27ACTRL3);
		tmp = readl(SC_VPLL27BCTRL3);
		tmp &= ~0x000fffff;
		tmp |= 0x000f5800;
		writel(tmp, SC_VPLL27BCTRL3);
	}

	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
	tmp = readl(SC_VPLL27ACTRL3);
	tmp |= 0x10000000;
	writel(tmp, SC_VPLL27ACTRL3);
	tmp = readl(SC_VPLL27BCTRL3);
	tmp |= 0x10000000;
	writel(tmp, SC_VPLL27BCTRL3);

	/* wait 10 usec */
	udelay(10);

	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
	tmp = readl(SC_VPLL27ACTRL2);
	tmp |= 0x10000000;
	writel(tmp, SC_VPLL27ACTRL2);
	tmp = readl(SC_VPLL27BCTRL2);
	tmp |= 0x10000000;
	writel(tmp, SC_VPLL27BCTRL2);

	/* set 0 to VPLA27WP and VPLA27WP */
	tmp = readl(SC_VPLL27ACTRL);
	tmp &= ~0x00000001;
	writel(tmp, SC_VPLL27ACTRL);
	tmp = readl(SC_VPLL27BCTRL);
	tmp |= ~0x00000001;
	writel(tmp, SC_VPLL27BCTRL);
}

int ph1_sld8_pll_init(const struct uniphier_board_data *bd)
{
	dpll_init();
	upll_init();
	vpll_init();

	/*
	 * Wait 500 usec until dpll get stable
	 * We wait 10 usec in upll_init() and vpll_init()
	 * so 20 usec can be saved here.
	 */
	udelay(480);

	return 0;
}
Commit	Line	Data
5894ca00	1	/*
f6e7f07c	2	* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
f6e7f07c	8	#include <linux/io.h>
107b3fb4 MY	9
	10	#include "../init.h"
	11	#include "../sc-regs.h"
	12	#include "../sg-regs.h"
5894ca00	13
ec79c798	14	static void dpll_init(void)
5894ca00 MY	15	{
	16	u32 tmp;
	17	/*
	18	* Set DPLL SSC parameters for DPLLCTRL3
	19	* [23] DIVN_TEST 0x1
	20	* [22:16] DIVN 0x50
	21	* [10] FREFSEL_TEST 0x1
	22	* [9:8] FREFSEL 0x2
	23	* [4] ICPD_TEST 0x1
	24	* [3:0] ICPD 0xb
	25	*/
	26	tmp = readl(SC_DPLLCTRL3);
	27	tmp &= ~0x00ff0717;
	28	tmp \|= 0x00d0061b;
	29	writel(tmp, SC_DPLLCTRL3);
	30
	31	/*
	32	* Set DPLL SSC parameters for DPLLCTRL
	33	* <-1%> <-2%>
	34	* [29:20] SSC_UPCNT 132 (0x084) 132 (0x084)
	35	* [14:0] SSC_dK 6335(0x18bf) 12710(0x31a6)
	36	*/
	37	tmp = readl(SC_DPLLCTRL);
	38	tmp &= ~0x3ff07fff;
	39	#ifdef CONFIG_DPLL_SSC_RATE_1PER
	40	tmp \|= 0x084018bf;
	41	#else
	42	tmp \|= 0x084031a6;
	43	#endif
	44	writel(tmp, SC_DPLLCTRL);
	45
	46	/*
	47	* Set DPLL SSC parameters for DPLLCTRL2
	48	* [31:29] SSC_STEP 0
	49	* [27] SSC_REG_REF 1
	50	* [26:20] SSC_M 79 (0x4f)
	51	* [19:0] SSC_K 964689 (0xeb851)
	52	*/
	53	tmp = readl(SC_DPLLCTRL2);
	54	tmp &= ~0xefffffff;
	55	tmp \|= 0x0cfeb851;
	56	writel(tmp, SC_DPLLCTRL2);
	57	}
	58
ec79c798	59	static void upll_init(void)
5894ca00 MY	60	{
	61	u32 tmp, clk_mode_upll, clk_mode_axosel;
	62
	63	tmp = readl(SG_PINMON0);
	64	clk_mode_upll = tmp & SG_PINMON0_CLK_MODE_UPLLSRC_MASK;
	65	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
	66
	67	/* set 0 to SNRT(UPLLCTRL.bit28) and K_LD(UPLLCTRL.bit[27]) */
	68	tmp = readl(SC_UPLLCTRL);
	69	tmp &= ~0x18000000;
	70	writel(tmp, SC_UPLLCTRL);
	71
	72	if (clk_mode_upll == SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT) {
	73	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U \|\|
	74	clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
	75	/* AXO: 25MHz */
	76	tmp &= ~0x07ffffff;
	77	tmp \|= 0x0228f5c0;
	78	} else {
	79	/* AXO: default 24.576MHz */
	80	tmp &= ~0x07ffffff;
	81	tmp \|= 0x02328000;
	82	}
	83	}
	84
	85	writel(tmp, SC_UPLLCTRL);
	86
	87	/* set 1 to K_LD(UPLLCTRL.bit[27]) */
	88	tmp \|= 0x08000000;
	89	writel(tmp, SC_UPLLCTRL);
	90
	91	/* wait 10 usec */
	92	udelay(10);
	93
	94	/* set 1 to SNRT(UPLLCTRL.bit[28]) */
	95	tmp \|= 0x10000000;
	96	writel(tmp, SC_UPLLCTRL);
	97	}
	98
ec79c798	99	static void vpll_init(void)
5894ca00 MY	100	{
	101	u32 tmp, clk_mode_axosel;
	102
	103	tmp = readl(SG_PINMON0);
	104	clk_mode_axosel = tmp & SG_PINMON0_CLK_MODE_AXOSEL_MASK;
	105
	106	/* set 1 to VPLA27WP and VPLA27WP */
	107	tmp = readl(SC_VPLL27ACTRL);
	108	tmp \|= 0x00000001;
	109	writel(tmp, SC_VPLL27ACTRL);
	110	tmp = readl(SC_VPLL27BCTRL);
	111	tmp \|= 0x00000001;
	112	writel(tmp, SC_VPLL27BCTRL);
	113
	114	/* Set 0 to VPLA_K_LD and VPLB_K_LD */
	115	tmp = readl(SC_VPLL27ACTRL3);
	116	tmp &= ~0x10000000;
	117	writel(tmp, SC_VPLL27ACTRL3);
	118	tmp = readl(SC_VPLL27BCTRL3);
	119	tmp &= ~0x10000000;
	120	writel(tmp, SC_VPLL27BCTRL3);
	121
	122	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
	123	tmp = readl(SC_VPLL27ACTRL2);
	124	tmp &= ~0x10000000;
	125	writel(tmp, SC_VPLL27ACTRL2);
	126	tmp = readl(SC_VPLL27BCTRL2);
	127	tmp &= ~0x10000000;
	128	writel(tmp, SC_VPLL27BCTRL2);
	129
	130	/* Set 0x20 to VPLA_SNRST and VPLB_SNRST */
	131	tmp = readl(SC_VPLL27ACTRL2);
	132	tmp &= ~0x0000007f;
	133	tmp \|= 0x00000020;
	134	writel(tmp, SC_VPLL27ACTRL2);
	135	tmp = readl(SC_VPLL27BCTRL2);
	136	tmp &= ~0x0000007f;
	137	tmp \|= 0x00000020;
	138	writel(tmp, SC_VPLL27BCTRL2);
	139
	140	if (clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U \|\|
	141	clk_mode_axosel == SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A) {
	142	/* AXO: 25MHz */
	143	tmp = readl(SC_VPLL27ACTRL3);
	144	tmp &= ~0x000fffff;
	145	tmp \|= 0x00066664;
	146	writel(tmp, SC_VPLL27ACTRL3);
	147	tmp = readl(SC_VPLL27BCTRL3);
	148	tmp &= ~0x000fffff;
	149	tmp \|= 0x00066664;
	150	writel(tmp, SC_VPLL27BCTRL3);
	151	} else {
	152	/* AXO: default 24.576MHz */
	153	tmp = readl(SC_VPLL27ACTRL3);
	154	tmp &= ~0x000fffff;
	155	tmp \|= 0x000f5800;
	156	writel(tmp, SC_VPLL27ACTRL3);
	157	tmp = readl(SC_VPLL27BCTRL3);
	158	tmp &= ~0x000fffff;
	159	tmp \|= 0x000f5800;
	160	writel(tmp, SC_VPLL27BCTRL3);
	161	}
	162
	163	/* Set 1 to VPLA_K_LD and VPLB_K_LD */
164	tmp = readl(SC_VPLL27ACTRL3);
165	tmp \|= 0x10000000;
166	writel(tmp, SC_VPLL27ACTRL3);
167	tmp = readl(SC_VPLL27BCTRL3);
168	tmp \|= 0x10000000;
169	writel(tmp, SC_VPLL27BCTRL3);
170
171	/* wait 10 usec */
172	udelay(10);
173
174	/* Set 0 to VPLA_SNRST and VPLB_SNRST */
175	tmp = readl(SC_VPLL27ACTRL2);
176	tmp \|= 0x10000000;
177	writel(tmp, SC_VPLL27ACTRL2);
178	tmp = readl(SC_VPLL27BCTRL2);
179	tmp \|= 0x10000000;
180	writel(tmp, SC_VPLL27BCTRL2);
181
182	/* set 0 to VPLA27WP and VPLA27WP */
183	tmp = readl(SC_VPLL27ACTRL);
184	tmp &= ~0x00000001;
185	writel(tmp, SC_VPLL27ACTRL);
186	tmp = readl(SC_VPLL27BCTRL);
187	tmp \|= ~0x00000001;
188	writel(tmp, SC_VPLL27BCTRL);
189	}
190
323d1f9d	191	int ph1_sld8_pll_init(const struct uniphier_board_data *bd)
5894ca00 MY	192	{
	193	dpll_init();
	194	upll_init();
	195	vpll_init();
	196
	197	/*
	198	* Wait 500 usec until dpll get stable
	199	* We wait 10 usec in upll_init() and vpll_init()
	200	* so 20 usec can be saved here.
	201	*/
	202	udelay(480);
323d1f9d MY	203
323d1f9d MY	204	return 0;
5894ca00	205	}