[thirdparty/u-boot.git] / arch / arm / mach-uniphier / sg-regs.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * UniPhier SG (SoC Glue) block registers
 *
 * Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
 * Copyright (C) 2016-2017 Socionext Inc.
 *   Author: Masahiro Yamada <yamada.masahiro@socionext.com>
 */

#ifndef UNIPHIER_SG_REGS_H
#define UNIPHIER_SG_REGS_H

/* Base Address */
#define SG_CTRL_BASE			0x5f800000
#define SG_DBG_BASE			0x5f900000

/* Revision */
#define SG_REVISION			(SG_CTRL_BASE | 0x0000)

/* Memory Configuration */
#define SG_MEMCONF			(SG_CTRL_BASE | 0x0400)

#define SG_MEMCONF_CH0_SZ_MASK		((0x1 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_64M		((0x0 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_SZ_128M		((0x0 << 10) | (0x02 << 0))
#define SG_MEMCONF_CH0_SZ_256M		((0x0 << 10) | (0x03 << 0))
#define SG_MEMCONF_CH0_SZ_512M		((0x1 << 10) | (0x00 << 0))
#define SG_MEMCONF_CH0_SZ_1G		((0x1 << 10) | (0x01 << 0))
#define SG_MEMCONF_CH0_NUM_MASK		(0x1 << 8)
#define SG_MEMCONF_CH0_NUM_1		(0x1 << 8)
#define SG_MEMCONF_CH0_NUM_2		(0x0 << 8)

#define SG_MEMCONF_CH1_SZ_MASK		((0x1 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_64M		((0x0 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_SZ_128M		((0x0 << 11) | (0x02 << 2))
#define SG_MEMCONF_CH1_SZ_256M		((0x0 << 11) | (0x03 << 2))
#define SG_MEMCONF_CH1_SZ_512M		((0x1 << 11) | (0x00 << 2))
#define SG_MEMCONF_CH1_SZ_1G		((0x1 << 11) | (0x01 << 2))
#define SG_MEMCONF_CH1_NUM_MASK		(0x1 << 9)
#define SG_MEMCONF_CH1_NUM_1		(0x1 << 9)
#define SG_MEMCONF_CH1_NUM_2		(0x0 << 9)

#define SG_MEMCONF_CH2_SZ_MASK		((0x1 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_64M		((0x0 << 26) | (0x01 << 16))
#define SG_MEMCONF_CH2_SZ_128M		((0x0 << 26) | (0x02 << 16))
#define SG_MEMCONF_CH2_SZ_256M		((0x0 << 26) | (0x03 << 16))
#define SG_MEMCONF_CH2_SZ_512M		((0x1 << 26) | (0x00 << 16))
#define SG_MEMCONF_CH2_SZ_1G		((0x1 << 26) | (0x01 << 16))
#define SG_MEMCONF_CH2_NUM_MASK		(0x1 << 24)
#define SG_MEMCONF_CH2_NUM_1		(0x1 << 24)
#define SG_MEMCONF_CH2_NUM_2		(0x0 << 24)
/* PH1-LD6b, ProXstream2, PH1-LD20 only */
#define SG_MEMCONF_CH2_DISABLE		(0x1 << 21)

#define SG_MEMCONF_SPARSEMEM		(0x1 << 4)

#define SG_USBPHYCTRL			(SG_CTRL_BASE | 0x500)
#define SG_ETPHYPSHUT			(SG_CTRL_BASE | 0x554)
#define SG_ETPHYCNT			(SG_CTRL_BASE | 0x550)

/* Pin Control */
#define SG_PINCTRL_BASE			(SG_CTRL_BASE | 0x1000)

/* PH1-Pro4, PH1-Pro5 */
#define SG_LOADPINCTRL			(SG_CTRL_BASE | 0x1700)

/* Input Enable */
#define SG_IECTRL			(SG_CTRL_BASE | 0x1d00)

/* Pin Monitor */
#define SG_PINMON0			(SG_DBG_BASE | 0x0100)
#define SG_PINMON2			(SG_DBG_BASE | 0x0108)

#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK	(0x3 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT	(0x0 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A	(0x2 << 19)
#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B	(0x3 << 19)

#define SG_PINMON0_CLK_MODE_AXOSEL_MASK		(0x3 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ	(0x0 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ	(0x1 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ	(0x2 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ	(0x3 << 16)

#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT	(0x0 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U	(0x1 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ	(0x2 << 16)
#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A	(0x3 << 16)

#ifdef __ASSEMBLY__

	.macro	sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
	ldr	\ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
	ldr	\rd, [\ra]
	and	\rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
	orr	\rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
	str	\rd, [\ra]
	.endm

#else

#include <linux/types.h>
#include <linux/io.h>

static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
				 unsigned mux_bits, unsigned reg_stride)
{
	unsigned shift = pin * mux_bits % 32;
	unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
	u32 mask = (1U << mux_bits) - 1;
	u32 tmp;

	tmp = readl(reg);
	tmp &= ~(mask << shift);
	tmp |= (mask & muxval) << shift;
	writel(tmp, reg);
}

static inline void sg_set_iectrl(unsigned pin)
{
	unsigned bit = pin % 32;
	unsigned long reg = SG_IECTRL + pin / 32 * 4;
	u32 tmp;

	tmp = readl(reg);
	tmp |= 1 << bit;
	writel(tmp, reg);
}

static inline void sg_set_iectrl_range(unsigned min, unsigned max)
{
	int i;

	for (i = min; i <= max; i++)
		sg_set_iectrl(i);
}

#endif /* __ASSEMBLY__ */

#endif /* UNIPHIER_SG_REGS_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5894ca00 MY	2	/*
	3	* UniPhier SG (SoC Glue) block registers
	4	*
e27d6c7d MY	5	* Copyright (C) 2011-2015 Copyright (C) 2011-2015 Panasonic Corporation
	6	* Copyright (C) 2016-2017 Socionext Inc.
	7	* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5894ca00 MY	8	*/
5894ca00 MY	9
e27d6c7d MY	10	#ifndef UNIPHIER_SG_REGS_H
e27d6c7d MY	11	#define UNIPHIER_SG_REGS_H
5894ca00 MY	12
	13	/* Base Address */
	14	#define SG_CTRL_BASE 0x5f800000
	15	#define SG_DBG_BASE 0x5f900000
	16
	17	/* Revision */
	18	#define SG_REVISION (SG_CTRL_BASE \| 0x0000)
5894ca00 MY	19
	20	/* Memory Configuration */
	21	#define SG_MEMCONF (SG_CTRL_BASE \| 0x0400)
	22
323d1f9d	23	#define SG_MEMCONF_CH0_SZ_MASK ((0x1 << 10) \| (0x03 << 0))
367a0d51 MY	24	#define SG_MEMCONF_CH0_SZ_64M ((0x0 << 10) \| (0x01 << 0))
	25	#define SG_MEMCONF_CH0_SZ_128M ((0x0 << 10) \| (0x02 << 0))
	26	#define SG_MEMCONF_CH0_SZ_256M ((0x0 << 10) \| (0x03 << 0))
	27	#define SG_MEMCONF_CH0_SZ_512M ((0x1 << 10) \| (0x00 << 0))
	28	#define SG_MEMCONF_CH0_SZ_1G ((0x1 << 10) \| (0x01 << 0))
323d1f9d	29	#define SG_MEMCONF_CH0_NUM_MASK (0x1 << 8)
5894ca00 MY	30	#define SG_MEMCONF_CH0_NUM_1 (0x1 << 8)
	31	#define SG_MEMCONF_CH0_NUM_2 (0x0 << 8)
	32
323d1f9d	33	#define SG_MEMCONF_CH1_SZ_MASK ((0x1 << 11) \| (0x03 << 2))
367a0d51 MY	34	#define SG_MEMCONF_CH1_SZ_64M ((0x0 << 11) \| (0x01 << 2))
	35	#define SG_MEMCONF_CH1_SZ_128M ((0x0 << 11) \| (0x02 << 2))
	36	#define SG_MEMCONF_CH1_SZ_256M ((0x0 << 11) \| (0x03 << 2))
	37	#define SG_MEMCONF_CH1_SZ_512M ((0x1 << 11) \| (0x00 << 2))
	38	#define SG_MEMCONF_CH1_SZ_1G ((0x1 << 11) \| (0x01 << 2))
323d1f9d	39	#define SG_MEMCONF_CH1_NUM_MASK (0x1 << 9)
5894ca00 MY	40	#define SG_MEMCONF_CH1_NUM_1 (0x1 << 9)
	41	#define SG_MEMCONF_CH1_NUM_2 (0x0 << 9)
	42
323d1f9d	43	#define SG_MEMCONF_CH2_SZ_MASK ((0x1 << 26) \| (0x03 << 16))
0ba924a4 MY	44	#define SG_MEMCONF_CH2_SZ_64M ((0x0 << 26) \| (0x01 << 16))
	45	#define SG_MEMCONF_CH2_SZ_128M ((0x0 << 26) \| (0x02 << 16))
	46	#define SG_MEMCONF_CH2_SZ_256M ((0x0 << 26) \| (0x03 << 16))
	47	#define SG_MEMCONF_CH2_SZ_512M ((0x1 << 26) \| (0x00 << 16))
9d0c2ceb	48	#define SG_MEMCONF_CH2_SZ_1G ((0x1 << 26) \| (0x01 << 16))
323d1f9d	49	#define SG_MEMCONF_CH2_NUM_MASK (0x1 << 24)
0ba924a4 MY	50	#define SG_MEMCONF_CH2_NUM_1 (0x1 << 24)
0ba924a4 MY	51	#define SG_MEMCONF_CH2_NUM_2 (0x0 << 24)
9d0c2ceb	52	/* PH1-LD6b, ProXstream2, PH1-LD20 only */
019df879	53	#define SG_MEMCONF_CH2_DISABLE (0x1 << 21)
0ba924a4	54
5894ca00 MY	55	#define SG_MEMCONF_SPARSEMEM (0x1 << 4)
5894ca00 MY	56
395e2142	57	#define SG_USBPHYCTRL (SG_CTRL_BASE \| 0x500)
667dbcd0 MY	58	#define SG_ETPHYPSHUT (SG_CTRL_BASE \| 0x554)
	59	#define SG_ETPHYCNT (SG_CTRL_BASE \| 0x550)
	60
5894ca00 MY	61	/* Pin Control */
	62	#define SG_PINCTRL_BASE (SG_CTRL_BASE \| 0x1000)
	63
28f40d4a	64	/* PH1-Pro4, PH1-Pro5 */
5894ca00 MY	65	#define SG_LOADPINCTRL (SG_CTRL_BASE \| 0x1700)
	66
	67	/* Input Enable */
	68	#define SG_IECTRL (SG_CTRL_BASE \| 0x1d00)
	69
	70	/* Pin Monitor */
	71	#define SG_PINMON0 (SG_DBG_BASE \| 0x0100)
81afa9c9	72	#define SG_PINMON2 (SG_DBG_BASE \| 0x0108)
5894ca00 MY	73
	74	#define SG_PINMON0_CLK_MODE_UPLLSRC_MASK (0x3 << 19)
	75	#define SG_PINMON0_CLK_MODE_UPLLSRC_DEFAULT (0x0 << 19)
	76	#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27A (0x2 << 19)
	77	#define SG_PINMON0_CLK_MODE_UPLLSRC_VPLL27B (0x3 << 19)
	78
	79	#define SG_PINMON0_CLK_MODE_AXOSEL_MASK (0x3 << 16)
	80	#define SG_PINMON0_CLK_MODE_AXOSEL_24576KHZ (0x0 << 16)
	81	#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ (0x1 << 16)
	82	#define SG_PINMON0_CLK_MODE_AXOSEL_6144KHZ (0x2 << 16)
	83	#define SG_PINMON0_CLK_MODE_AXOSEL_6250KHZ (0x3 << 16)
	84
	85	#define SG_PINMON0_CLK_MODE_AXOSEL_DEFAULT (0x0 << 16)
	86	#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_U (0x1 << 16)
	87	#define SG_PINMON0_CLK_MODE_AXOSEL_20480KHZ (0x2 << 16)
	88	#define SG_PINMON0_CLK_MODE_AXOSEL_25000KHZ_A (0x3 << 16)
	89
2d5d1c9e MY	90	#ifdef __ASSEMBLY__
2d5d1c9e MY	91
9628afa7 MY	92	.macro sg_set_pinsel, pin, muxval, mux_bits, reg_stride, ra, rd
9628afa7 MY	93	ldr \ra, =(SG_PINCTRL_BASE + \pin * \mux_bits / 32 * \reg_stride)
2d5d1c9e	94	ldr \rd, [\ra]
9628afa7 MY	95	and \rd, \rd, #~(((1 << \mux_bits) - 1) << (\pin * \mux_bits % 32))
9628afa7 MY	96	orr \rd, \rd, #(\muxval << (\pin * \mux_bits % 32))
2d5d1c9e MY	97	str \rd, [\ra]
	98	.endm
	99
	100	#else
	101
5894ca00	102	#include <linux/types.h>
f6e7f07c	103	#include <linux/io.h>
5894ca00	104
9628afa7 MY	105	static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
9628afa7 MY	106	unsigned mux_bits, unsigned reg_stride)
5894ca00	107	{
9628afa7	108	unsigned shift = pin * mux_bits % 32;
11d3ede4	109	unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
9628afa7 MY	110	u32 mask = (1U << mux_bits) - 1;
	111	u32 tmp;
	112
	113	tmp = readl(reg);
	114	tmp &= ~(mask << shift);
	115	tmp \|= (mask & muxval) << shift;
	116	writel(tmp, reg);
5894ca00 MY	117	}
5894ca00 MY	118
c8cc7213 MY	119	static inline void sg_set_iectrl(unsigned pin)
	120	{
	121	unsigned bit = pin % 32;
	122	unsigned long reg = SG_IECTRL + pin / 32 * 4;
	123	u32 tmp;
	124
	125	tmp = readl(reg);
	126	tmp \|= 1 << bit;
	127	writel(tmp, reg);
	128	}
	129
612ccd90 MY	130	static inline void sg_set_iectrl_range(unsigned min, unsigned max)
	131	{
	132	int i;
	133
	134	for (i = min; i <= max; i++)
	135	sg_set_iectrl(i);
	136	}
	137
5894ca00 MY	138	#endif /* __ASSEMBLY__ */
5894ca00 MY	139
e27d6c7d	140	#endif /* UNIPHIER_SG_REGS_H */