[thirdparty/u-boot.git] / arch / arm / mach-zynqmp / include / mach / sys_proto.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * (C) Copyright 2014 - 2015 Xilinx, Inc.
 * Michal Simek <michal.simek@xilinx.com>
 */

#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H

#define ZYNQMP_CSU_SILICON_VER_MASK	0xF
#define KEY_PTR_LEN	32
#define IV_SIZE		12
#define RSA_KEY_SIZE	512
#define MODULUS_LEN	512
#define PRIV_EXPO_LEN	512
#define PUB_EXPO_LEN	4

#define ZYNQMP_SHA3_INIT	1
#define ZYNQMP_SHA3_UPDATE	2
#define ZYNQMP_SHA3_FINAL	4
#define ZYNQMP_SHA3_SIZE	48

#define ZYNQMP_FPGA_BIT_AUTH_DDR	1
#define ZYNQMP_FPGA_BIT_AUTH_OCM	2
#define ZYNQMP_FPGA_BIT_ENC_USR_KEY	3
#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY	4
#define ZYNQMP_FPGA_BIT_NS		5

#define ZYNQMP_FPGA_AUTH_DDR	1

enum {
	IDCODE,
	VERSION,
	IDCODE2,
};

enum {
	ZYNQMP_SILICON_V1,
	ZYNQMP_SILICON_V2,
	ZYNQMP_SILICON_V3,
	ZYNQMP_SILICON_V4,
};

enum {
	TCM_LOCK,
	TCM_SPLIT,
};

int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
unsigned int zynqmp_get_silicon_version(void);

int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
int zynqmp_mmio_read(const u32 address, u32 *value);

void initialize_tcm(bool mode);
void mem_map_fill(void);
#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) || defined(CONFIG_DEFINE_TCM_OCM_MMAP)
void tcm_init(u8 mode);
#endif

#endif /* _ASM_ARCH_SYS_PROTO_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
84c7204b MS	2	/*
	3	* (C) Copyright 2014 - 2015 Xilinx, Inc.
	4	* Michal Simek <michal.simek@xilinx.com>
84c7204b MS	5	*/
	6
	7	#ifndef _ASM_ARCH_SYS_PROTO_H
	8	#define _ASM_ARCH_SYS_PROTO_H
	9
db3123b4	10	#define ZYNQMP_CSU_SILICON_VER_MASK 0xF
c436bf92	11	#define KEY_PTR_LEN 32
8e4e9146	12	#define IV_SIZE 12
650d02ae KR	13	#define RSA_KEY_SIZE 512
	14	#define MODULUS_LEN 512
	15	#define PRIV_EXPO_LEN 512
	16	#define PUB_EXPO_LEN 4
db3123b4	17
0af9de9a KR	18	#define ZYNQMP_SHA3_INIT 1
	19	#define ZYNQMP_SHA3_UPDATE 2
	20	#define ZYNQMP_SHA3_FINAL 4
	21	#define ZYNQMP_SHA3_SIZE 48
	22
a18d09ea SDPP	23	#define ZYNQMP_FPGA_BIT_AUTH_DDR 1
	24	#define ZYNQMP_FPGA_BIT_AUTH_OCM 2
	25	#define ZYNQMP_FPGA_BIT_ENC_USR_KEY 3
	26	#define ZYNQMP_FPGA_BIT_ENC_DEV_KEY 4
19ed4b69 SDPP	27	#define ZYNQMP_FPGA_BIT_NS 5
19ed4b69 SDPP	28
a18d09ea SDPP	29	#define ZYNQMP_FPGA_AUTH_DDR 1
a18d09ea SDPP	30
db3123b4 SDPP	31	enum {
	32	IDCODE,
	33	VERSION,
494fffe7	34	IDCODE2,
db3123b4 SDPP	35	};
	36
	37	enum {
	38	ZYNQMP_SILICON_V1,
	39	ZYNQMP_SILICON_V2,
	40	ZYNQMP_SILICON_V3,
	41	ZYNQMP_SILICON_V4,
	42	};
	43
a076789e SDPP	44	enum {
	45	TCM_LOCK,
	46	TCM_SPLIT,
	47	};
	48
2d2af5d8	49	int zynq_board_read_rom_ethaddr(unsigned char *ethaddr);
84c7204b MS	50	unsigned int zynqmp_get_silicon_version(void);
84c7204b MS	51
e0752bc1 SDPP	52	int zynqmp_mmio_write(const u32 address, const u32 mask, const u32 value);
e0752bc1 SDPP	53	int zynqmp_mmio_read(const u32 address, u32 *value);
e0752bc1	54
a076789e	55	void initialize_tcm(bool mode);
0678941a	56	void mem_map_fill(void);
5860bc16 SDPP	57	#if defined(CONFIG_SYS_MEM_RSVD_FOR_MMU) \|\| defined(CONFIG_DEFINE_TCM_OCM_MMAP)
	58	void tcm_init(u8 mode);
	59	#endif
f52bf5a3	60
84c7204b	61	#endif /* _ASM_ARCH_SYS_PROTO_H */