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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-arm920.S: MMU functions for ARM920 | |
3 | * | |
4 | * Copyright (C) 1999,2000 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
d090ddda | 6 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | * | |
23 | * These are the low level assembler for performing cache and TLB | |
24 | * functions on the arm920. | |
25 | * | |
26 | * CONFIG_CPU_ARM920_CPU_IDLE -> nohlt | |
27 | */ | |
28 | #include <linux/linkage.h> | |
1da177e4 LT |
29 | #include <linux/init.h> |
30 | #include <asm/assembler.h> | |
5ec9407d | 31 | #include <asm/hwcap.h> |
74945c86 | 32 | #include <asm/pgtable-hwdef.h> |
1da177e4 | 33 | #include <asm/pgtable.h> |
1da177e4 LT |
34 | #include <asm/page.h> |
35 | #include <asm/ptrace.h> | |
36 | #include "proc-macros.S" | |
37 | ||
38 | /* | |
39 | * The size of one data cache line. | |
40 | */ | |
41 | #define CACHE_DLINESIZE 32 | |
42 | ||
43 | /* | |
44 | * The number of data cache segments. | |
45 | */ | |
46 | #define CACHE_DSEGMENTS 8 | |
47 | ||
48 | /* | |
49 | * The number of lines in a cache segment. | |
50 | */ | |
51 | #define CACHE_DENTRIES 64 | |
52 | ||
53 | /* | |
54 | * This is the size at which it becomes more efficient to | |
55 | * clean the whole cache, rather than using the individual | |
25985edc | 56 | * cache line maintenance instructions. |
1da177e4 LT |
57 | */ |
58 | #define CACHE_DLIMIT 65536 | |
59 | ||
60 | ||
61 | .text | |
62 | /* | |
63 | * cpu_arm920_proc_init() | |
64 | */ | |
65 | ENTRY(cpu_arm920_proc_init) | |
66 | mov pc, lr | |
67 | ||
68 | /* | |
69 | * cpu_arm920_proc_fin() | |
70 | */ | |
71 | ENTRY(cpu_arm920_proc_fin) | |
1da177e4 LT |
72 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
73 | bic r0, r0, #0x1000 @ ...i............ | |
74 | bic r0, r0, #0x000e @ ............wca. | |
75 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 76 | mov pc, lr |
1da177e4 LT |
77 | |
78 | /* | |
79 | * cpu_arm920_reset(loc) | |
80 | * | |
81 | * Perform a soft reset of the system. Put the CPU into the | |
82 | * same state as it would be if it had been reset, and branch | |
83 | * to what would be the reset vector. | |
84 | * | |
85 | * loc: location to jump to for soft reset | |
86 | */ | |
87 | .align 5 | |
88 | ENTRY(cpu_arm920_reset) | |
89 | mov ip, #0 | |
90 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
91 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
d090ddda | 92 | #ifdef CONFIG_MMU |
1da177e4 | 93 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
d090ddda | 94 | #endif |
1da177e4 LT |
95 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
96 | bic ip, ip, #0x000f @ ............wcam | |
97 | bic ip, ip, #0x1100 @ ...i...s........ | |
98 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
99 | mov pc, r0 | |
100 | ||
101 | /* | |
102 | * cpu_arm920_do_idle() | |
103 | */ | |
104 | .align 5 | |
105 | ENTRY(cpu_arm920_do_idle) | |
106 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt | |
107 | mov pc, lr | |
108 | ||
109 | ||
110 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
111 | ||
c8c90860 MW |
112 | /* |
113 | * flush_icache_all() | |
114 | * | |
115 | * Unconditionally clean and invalidate the entire icache. | |
116 | */ | |
117 | ENTRY(arm920_flush_icache_all) | |
118 | mov r0, #0 | |
119 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
120 | mov pc, lr | |
121 | ENDPROC(arm920_flush_icache_all) | |
122 | ||
1da177e4 LT |
123 | /* |
124 | * flush_user_cache_all() | |
125 | * | |
126 | * Invalidate all cache entries in a particular address | |
127 | * space. | |
128 | */ | |
129 | ENTRY(arm920_flush_user_cache_all) | |
130 | /* FALLTHROUGH */ | |
131 | ||
132 | /* | |
133 | * flush_kern_cache_all() | |
134 | * | |
135 | * Clean and invalidate the entire cache. | |
136 | */ | |
137 | ENTRY(arm920_flush_kern_cache_all) | |
138 | mov r2, #VM_EXEC | |
139 | mov ip, #0 | |
140 | __flush_whole_cache: | |
141 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments | |
142 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries | |
143 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index | |
144 | subs r3, r3, #1 << 26 | |
145 | bcs 2b @ entries 63 to 0 | |
146 | subs r1, r1, #1 << 5 | |
147 | bcs 1b @ segments 7 to 0 | |
148 | tst r2, #VM_EXEC | |
149 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
150 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
151 | mov pc, lr | |
152 | ||
153 | /* | |
154 | * flush_user_cache_range(start, end, flags) | |
155 | * | |
156 | * Invalidate a range of cache entries in the specified | |
157 | * address space. | |
158 | * | |
159 | * - start - start address (inclusive) | |
160 | * - end - end address (exclusive) | |
161 | * - flags - vm_flags for address space | |
162 | */ | |
163 | ENTRY(arm920_flush_user_cache_range) | |
164 | mov ip, #0 | |
165 | sub r3, r1, r0 @ calculate total size | |
166 | cmp r3, #CACHE_DLIMIT | |
167 | bhs __flush_whole_cache | |
168 | ||
169 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
170 | tst r2, #VM_EXEC | |
171 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
172 | add r0, r0, #CACHE_DLINESIZE | |
173 | cmp r0, r1 | |
174 | blo 1b | |
175 | tst r2, #VM_EXEC | |
176 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
177 | mov pc, lr | |
178 | ||
179 | /* | |
180 | * coherent_kern_range(start, end) | |
181 | * | |
182 | * Ensure coherency between the Icache and the Dcache in the | |
183 | * region described by start, end. If you have non-snooping | |
184 | * Harvard caches, you need to implement this function. | |
185 | * | |
186 | * - start - virtual start address | |
187 | * - end - virtual end address | |
188 | */ | |
189 | ENTRY(arm920_coherent_kern_range) | |
190 | /* FALLTHROUGH */ | |
191 | ||
192 | /* | |
193 | * coherent_user_range(start, end) | |
194 | * | |
195 | * Ensure coherency between the Icache and the Dcache in the | |
196 | * region described by start, end. If you have non-snooping | |
197 | * Harvard caches, you need to implement this function. | |
198 | * | |
199 | * - start - virtual start address | |
200 | * - end - virtual end address | |
201 | */ | |
202 | ENTRY(arm920_coherent_user_range) | |
203 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
204 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
205 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
206 | add r0, r0, #CACHE_DLINESIZE | |
207 | cmp r0, r1 | |
208 | blo 1b | |
209 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
210 | mov pc, lr | |
211 | ||
212 | /* | |
2c9b9c84 | 213 | * flush_kern_dcache_area(void *addr, size_t size) |
1da177e4 LT |
214 | * |
215 | * Ensure no D cache aliasing occurs, either with itself or | |
216 | * the I cache | |
217 | * | |
2c9b9c84 RK |
218 | * - addr - kernel address |
219 | * - size - region size | |
1da177e4 | 220 | */ |
2c9b9c84 RK |
221 | ENTRY(arm920_flush_kern_dcache_area) |
222 | add r1, r0, r1 | |
1da177e4 LT |
223 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
224 | add r0, r0, #CACHE_DLINESIZE | |
225 | cmp r0, r1 | |
226 | blo 1b | |
227 | mov r0, #0 | |
228 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
229 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
230 | mov pc, lr | |
231 | ||
232 | /* | |
233 | * dma_inv_range(start, end) | |
234 | * | |
235 | * Invalidate (discard) the specified virtual address range. | |
236 | * May not write back any entries. If 'start' or 'end' | |
237 | * are not cache line aligned, those lines must be written | |
238 | * back. | |
239 | * | |
240 | * - start - virtual start address | |
241 | * - end - virtual end address | |
242 | * | |
243 | * (same as v4wb) | |
244 | */ | |
702b94bf | 245 | arm920_dma_inv_range: |
1da177e4 LT |
246 | tst r0, #CACHE_DLINESIZE - 1 |
247 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
248 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | |
249 | tst r1, #CACHE_DLINESIZE - 1 | |
250 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | |
251 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
252 | add r0, r0, #CACHE_DLINESIZE | |
253 | cmp r0, r1 | |
254 | blo 1b | |
255 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
256 | mov pc, lr | |
257 | ||
258 | /* | |
259 | * dma_clean_range(start, end) | |
260 | * | |
261 | * Clean the specified virtual address range. | |
262 | * | |
263 | * - start - virtual start address | |
264 | * - end - virtual end address | |
265 | * | |
266 | * (same as v4wb) | |
267 | */ | |
702b94bf | 268 | arm920_dma_clean_range: |
1da177e4 LT |
269 | bic r0, r0, #CACHE_DLINESIZE - 1 |
270 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
271 | add r0, r0, #CACHE_DLINESIZE | |
272 | cmp r0, r1 | |
273 | blo 1b | |
274 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
275 | mov pc, lr | |
276 | ||
277 | /* | |
278 | * dma_flush_range(start, end) | |
279 | * | |
280 | * Clean and invalidate the specified virtual address range. | |
281 | * | |
282 | * - start - virtual start address | |
283 | * - end - virtual end address | |
284 | */ | |
285 | ENTRY(arm920_dma_flush_range) | |
286 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
287 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
288 | add r0, r0, #CACHE_DLINESIZE | |
289 | cmp r0, r1 | |
290 | blo 1b | |
291 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
292 | mov pc, lr | |
293 | ||
a9c9147e RK |
294 | /* |
295 | * dma_map_area(start, size, dir) | |
296 | * - start - kernel virtual start address | |
297 | * - size - size of region | |
298 | * - dir - DMA direction | |
299 | */ | |
300 | ENTRY(arm920_dma_map_area) | |
301 | add r1, r1, r0 | |
302 | cmp r2, #DMA_TO_DEVICE | |
303 | beq arm920_dma_clean_range | |
304 | bcs arm920_dma_inv_range | |
305 | b arm920_dma_flush_range | |
306 | ENDPROC(arm920_dma_map_area) | |
307 | ||
308 | /* | |
309 | * dma_unmap_area(start, size, dir) | |
310 | * - start - kernel virtual start address | |
311 | * - size - size of region | |
312 | * - dir - DMA direction | |
313 | */ | |
314 | ENTRY(arm920_dma_unmap_area) | |
315 | mov pc, lr | |
316 | ENDPROC(arm920_dma_unmap_area) | |
317 | ||
1da177e4 | 318 | ENTRY(arm920_cache_fns) |
c8c90860 | 319 | .long arm920_flush_icache_all |
1da177e4 LT |
320 | .long arm920_flush_kern_cache_all |
321 | .long arm920_flush_user_cache_all | |
322 | .long arm920_flush_user_cache_range | |
323 | .long arm920_coherent_kern_range | |
324 | .long arm920_coherent_user_range | |
2c9b9c84 | 325 | .long arm920_flush_kern_dcache_area |
a9c9147e RK |
326 | .long arm920_dma_map_area |
327 | .long arm920_dma_unmap_area | |
1da177e4 LT |
328 | .long arm920_dma_flush_range |
329 | ||
330 | #endif | |
331 | ||
332 | ||
333 | ENTRY(cpu_arm920_dcache_clean_area) | |
334 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
335 | add r0, r0, #CACHE_DLINESIZE | |
336 | subs r1, r1, #CACHE_DLINESIZE | |
337 | bhi 1b | |
338 | mov pc, lr | |
339 | ||
340 | /* =============================== PageTable ============================== */ | |
341 | ||
342 | /* | |
343 | * cpu_arm920_switch_mm(pgd) | |
344 | * | |
345 | * Set the translation base pointer to be as described by pgd. | |
346 | * | |
347 | * pgd: new page tables | |
348 | */ | |
349 | .align 5 | |
350 | ENTRY(cpu_arm920_switch_mm) | |
d090ddda | 351 | #ifdef CONFIG_MMU |
1da177e4 LT |
352 | mov ip, #0 |
353 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
354 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
355 | #else | |
356 | @ && 'Clean & Invalidate whole DCache' | |
357 | @ && Re-written to use Index Ops. | |
358 | @ && Uses registers r1, r3 and ip | |
359 | ||
360 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 8 segments | |
361 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries | |
362 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
363 | subs r3, r3, #1 << 26 | |
364 | bcs 2b @ entries 63 to 0 | |
365 | subs r1, r1, #1 << 5 | |
366 | bcs 1b @ segments 7 to 0 | |
367 | #endif | |
368 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
369 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
370 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | |
371 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
d090ddda | 372 | #endif |
1da177e4 LT |
373 | mov pc, lr |
374 | ||
375 | /* | |
ad1ae2fe | 376 | * cpu_arm920_set_pte(ptep, pte, ext) |
1da177e4 LT |
377 | * |
378 | * Set a PTE and flush it out | |
379 | */ | |
380 | .align 5 | |
ad1ae2fe | 381 | ENTRY(cpu_arm920_set_pte_ext) |
d090ddda | 382 | #ifdef CONFIG_MMU |
da091653 | 383 | armv3_set_pte_ext |
1da177e4 LT |
384 | mov r0, r0 |
385 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
386 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
da091653 | 387 | #endif |
1da177e4 LT |
388 | mov pc, lr |
389 | ||
f6b0fa02 RK |
390 | /* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ |
391 | .globl cpu_arm920_suspend_size | |
392 | .equ cpu_arm920_suspend_size, 4 * 3 | |
393 | #ifdef CONFIG_PM | |
394 | ENTRY(cpu_arm920_do_suspend) | |
395 | stmfd sp!, {r4 - r7, lr} | |
396 | mrc p15, 0, r4, c13, c0, 0 @ PID | |
397 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID | |
398 | mrc p15, 0, r6, c2, c0, 0 @ TTB address | |
399 | mrc p15, 0, r7, c1, c0, 0 @ Control register | |
400 | stmia r0, {r4 - r7} | |
401 | ldmfd sp!, {r4 - r7, pc} | |
402 | ENDPROC(cpu_arm920_do_suspend) | |
403 | ||
404 | ENTRY(cpu_arm920_do_resume) | |
405 | mov ip, #0 | |
406 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs | |
407 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches | |
408 | ldmia r0, {r4 - r7} | |
409 | mcr p15, 0, r4, c13, c0, 0 @ PID | |
410 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID | |
411 | mcr p15, 0, r6, c2, c0, 0 @ TTB address | |
412 | mov r0, r7 @ control register | |
413 | mov r2, r6, lsr #14 @ get TTB0 base | |
414 | mov r2, r2, lsl #14 | |
415 | ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \ | |
416 | PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE | |
417 | b cpu_resume_mmu | |
418 | ENDPROC(cpu_arm920_do_resume) | |
419 | #else | |
420 | #define cpu_arm920_do_suspend 0 | |
421 | #define cpu_arm920_do_resume 0 | |
422 | #endif | |
423 | ||
5085f3ff | 424 | __CPUINIT |
1da177e4 LT |
425 | |
426 | .type __arm920_setup, #function | |
427 | __arm920_setup: | |
428 | mov r0, #0 | |
429 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | |
430 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | |
d090ddda | 431 | #ifdef CONFIG_MMU |
1da177e4 | 432 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
d090ddda | 433 | #endif |
22b19086 RK |
434 | adr r5, arm920_crval |
435 | ldmia r5, {r5, r6} | |
1da177e4 | 436 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
1da177e4 | 437 | bic r0, r0, r5 |
22b19086 | 438 | orr r0, r0, r6 |
1da177e4 LT |
439 | mov pc, lr |
440 | .size __arm920_setup, . - __arm920_setup | |
441 | ||
442 | /* | |
443 | * R | |
444 | * .RVI ZFRS BLDP WCAM | |
445 | * ..11 0001 ..11 0101 | |
446 | * | |
447 | */ | |
22b19086 RK |
448 | .type arm920_crval, #object |
449 | arm920_crval: | |
450 | crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130 | |
1da177e4 LT |
451 | |
452 | __INITDATA | |
453 | ||
454 | /* | |
455 | * Purpose : Function pointers used to access above functions - all calls | |
456 | * come through these | |
457 | */ | |
458 | .type arm920_processor_functions, #object | |
459 | arm920_processor_functions: | |
460 | .word v4t_early_abort | |
4fb28474 | 461 | .word legacy_pabort |
1da177e4 LT |
462 | .word cpu_arm920_proc_init |
463 | .word cpu_arm920_proc_fin | |
464 | .word cpu_arm920_reset | |
465 | .word cpu_arm920_do_idle | |
466 | .word cpu_arm920_dcache_clean_area | |
467 | .word cpu_arm920_switch_mm | |
ad1ae2fe | 468 | .word cpu_arm920_set_pte_ext |
f6b0fa02 RK |
469 | .word cpu_arm920_suspend_size |
470 | .word cpu_arm920_do_suspend | |
471 | .word cpu_arm920_do_resume | |
1da177e4 LT |
472 | .size arm920_processor_functions, . - arm920_processor_functions |
473 | ||
474 | .section ".rodata" | |
475 | ||
476 | .type cpu_arch_name, #object | |
477 | cpu_arch_name: | |
478 | .asciz "armv4t" | |
479 | .size cpu_arch_name, . - cpu_arch_name | |
480 | ||
481 | .type cpu_elf_name, #object | |
482 | cpu_elf_name: | |
483 | .asciz "v4" | |
484 | .size cpu_elf_name, . - cpu_elf_name | |
485 | ||
486 | .type cpu_arm920_name, #object | |
487 | cpu_arm920_name: | |
264edb35 | 488 | .asciz "ARM920T" |
1da177e4 LT |
489 | .size cpu_arm920_name, . - cpu_arm920_name |
490 | ||
491 | .align | |
492 | ||
02b7dd12 | 493 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
494 | |
495 | .type __arm920_proc_info,#object | |
496 | __arm920_proc_info: | |
497 | .long 0x41009200 | |
498 | .long 0xff00fff0 | |
499 | .long PMD_TYPE_SECT | \ | |
500 | PMD_SECT_BUFFERABLE | \ | |
501 | PMD_SECT_CACHEABLE | \ | |
502 | PMD_BIT4 | \ | |
503 | PMD_SECT_AP_WRITE | \ | |
504 | PMD_SECT_AP_READ | |
8799ee9f RK |
505 | .long PMD_TYPE_SECT | \ |
506 | PMD_BIT4 | \ | |
507 | PMD_SECT_AP_WRITE | \ | |
508 | PMD_SECT_AP_READ | |
1da177e4 LT |
509 | b __arm920_setup |
510 | .long cpu_arch_name | |
511 | .long cpu_elf_name | |
512 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | |
513 | .long cpu_arm920_name | |
514 | .long arm920_processor_functions | |
515 | .long v4wbi_tlb_fns | |
516 | .long v4wb_user_fns | |
517 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
518 | .long arm920_cache_fns | |
519 | #else | |
520 | .long v4wt_cache_fns | |
521 | #endif | |
522 | .size __arm920_proc_info, . - __arm920_proc_info |