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omap: Cleanup the coding style in id.c
[people/ms/linux.git] / arch / arm / plat-omap / gpio.c
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5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
5e1c5ff4
TL		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
5e1c5ff4
TL		 17#include <linux/init.h>
18#include <linux/module.h>
5e1c5ff4 19#include <linux/interrupt.h>
92105bb7
TL		 20#include <linux/sysdev.h>
21#include <linux/err.h>
f8ce2547 22#include <linux/clk.h>
fced80c7 23#include <linux/io.h>
5e1c5ff4 24
a09e64fb 25#include <mach/hardware.h>
5e1c5ff4 26#include <asm/irq.h>
a09e64fb
RK		 27#include <mach/irqs.h>
28#include <mach/gpio.h>
5e1c5ff4
TL		 29#include <asm/mach/irq.h>
30
5e1c5ff4
TL		 31/*
32 * OMAP1510 GPIO registers
33 */
9f7065da 34#define OMAP1510_GPIO_BASE 0xfffce000
5e1c5ff4
TL		 35#define OMAP1510_GPIO_DATA_INPUT 0x00
36#define OMAP1510_GPIO_DATA_OUTPUT 0x04
37#define OMAP1510_GPIO_DIR_CONTROL 0x08
38#define OMAP1510_GPIO_INT_CONTROL 0x0c
39#define OMAP1510_GPIO_INT_MASK 0x10
40#define OMAP1510_GPIO_INT_STATUS 0x14
41#define OMAP1510_GPIO_PIN_CONTROL 0x18
42
43#define OMAP1510_IH_GPIO_BASE 64
44
45/*
46 * OMAP1610 specific GPIO registers
47 */
9f7065da
TL		 48#define OMAP1610_GPIO1_BASE 0xfffbe400
49#define OMAP1610_GPIO2_BASE 0xfffbec00
50#define OMAP1610_GPIO3_BASE 0xfffbb400
51#define OMAP1610_GPIO4_BASE 0xfffbbc00
5e1c5ff4
TL		 52#define OMAP1610_GPIO_REVISION 0x0000
53#define OMAP1610_GPIO_SYSCONFIG 0x0010
54#define OMAP1610_GPIO_SYSSTATUS 0x0014
55#define OMAP1610_GPIO_IRQSTATUS1 0x0018
56#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 57#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 58#define OMAP1610_GPIO_DATAIN 0x002c
59#define OMAP1610_GPIO_DATAOUT 0x0030
60#define OMAP1610_GPIO_DIRECTION 0x0034
61#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
62#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
63#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 64#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
66#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 67#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 68#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
69
70/*
7c006926 71 * OMAP7XX specific GPIO registers
5e1c5ff4 72 */
9f7065da
TL		 73#define OMAP7XX_GPIO1_BASE 0xfffbc000
74#define OMAP7XX_GPIO2_BASE 0xfffbc800
75#define OMAP7XX_GPIO3_BASE 0xfffbd000
76#define OMAP7XX_GPIO4_BASE 0xfffbd800
77#define OMAP7XX_GPIO5_BASE 0xfffbe000
78#define OMAP7XX_GPIO6_BASE 0xfffbe800
7c006926
AB		 79#define OMAP7XX_GPIO_DATA_INPUT 0x00
80#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
81#define OMAP7XX_GPIO_DIR_CONTROL 0x08
82#define OMAP7XX_GPIO_INT_CONTROL 0x0c
83#define OMAP7XX_GPIO_INT_MASK 0x10
84#define OMAP7XX_GPIO_INT_STATUS 0x14
5e1c5ff4 85
9f7065da 86#define OMAP1_MPUIO_VBASE OMAP1_MPUIO_BASE
94113260 87
92105bb7
TL		 88/*
89 * omap24xx specific GPIO registers
90 */
9f7065da
TL		 91#define OMAP242X_GPIO1_BASE 0x48018000
92#define OMAP242X_GPIO2_BASE 0x4801a000
93#define OMAP242X_GPIO3_BASE 0x4801c000
94#define OMAP242X_GPIO4_BASE 0x4801e000
56a25641 95
9f7065da
TL		 96#define OMAP243X_GPIO1_BASE 0x4900C000
97#define OMAP243X_GPIO2_BASE 0x4900E000
98#define OMAP243X_GPIO3_BASE 0x49010000
99#define OMAP243X_GPIO4_BASE 0x49012000
100#define OMAP243X_GPIO5_BASE 0x480B6000
56a25641 101
92105bb7
TL		 102#define OMAP24XX_GPIO_REVISION 0x0000
103#define OMAP24XX_GPIO_SYSCONFIG 0x0010
104#define OMAP24XX_GPIO_SYSSTATUS 0x0014
105#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 106#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
107#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 108#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 109#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 110#define OMAP24XX_GPIO_CTRL 0x0030
111#define OMAP24XX_GPIO_OE 0x0034
112#define OMAP24XX_GPIO_DATAIN 0x0038
113#define OMAP24XX_GPIO_DATAOUT 0x003c
114#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
115#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
116#define OMAP24XX_GPIO_RISINGDETECT 0x0048
117#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 118#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
119#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 120#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
121#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
122#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
123#define OMAP24XX_GPIO_SETWKUENA 0x0084
124#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
125#define OMAP24XX_GPIO_SETDATAOUT 0x0094
126
78a1a6d3
SR		 127#define OMAP4_GPIO_REVISION 0x0000
128#define OMAP4_GPIO_SYSCONFIG 0x0010
129#define OMAP4_GPIO_EOI 0x0020
130#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
131#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
132#define OMAP4_GPIO_IRQSTATUS0 0x002c
133#define OMAP4_GPIO_IRQSTATUS1 0x0030
134#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
135#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
136#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
137#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
138#define OMAP4_GPIO_IRQWAKEN0 0x0044
139#define OMAP4_GPIO_IRQWAKEN1 0x0048
140#define OMAP4_GPIO_SYSSTATUS 0x0104
141#define OMAP4_GPIO_CTRL 0x0130
142#define OMAP4_GPIO_OE 0x0134
143#define OMAP4_GPIO_DATAIN 0x0138
144#define OMAP4_GPIO_DATAOUT 0x013c
145#define OMAP4_GPIO_LEVELDETECT0 0x0140
146#define OMAP4_GPIO_LEVELDETECT1 0x0144
147#define OMAP4_GPIO_RISINGDETECT 0x0148
148#define OMAP4_GPIO_FALLINGDETECT 0x014c
149#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
150#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
151#define OMAP4_GPIO_CLEARDATAOUT 0x0190
152#define OMAP4_GPIO_SETDATAOUT 0x0194
5492fb1a
SMK		 153/*
154 * omap34xx specific GPIO registers
155 */
156
9f7065da
TL		 157#define OMAP34XX_GPIO1_BASE 0x48310000
158#define OMAP34XX_GPIO2_BASE 0x49050000
159#define OMAP34XX_GPIO3_BASE 0x49052000
160#define OMAP34XX_GPIO4_BASE 0x49054000
161#define OMAP34XX_GPIO5_BASE 0x49056000
162#define OMAP34XX_GPIO6_BASE 0x49058000
5492fb1a 163
44169075
SS		 164/*
165 * OMAP44XX specific GPIO registers
166 */
9f7065da
TL		 167#define OMAP44XX_GPIO1_BASE 0x4a310000
168#define OMAP44XX_GPIO2_BASE 0x48055000
169#define OMAP44XX_GPIO3_BASE 0x48057000
170#define OMAP44XX_GPIO4_BASE 0x48059000
171#define OMAP44XX_GPIO5_BASE 0x4805B000
172#define OMAP44XX_GPIO6_BASE 0x4805D000
5492fb1a 173
5e1c5ff4 174struct gpio_bank {
9f7065da 175 unsigned long pbase;
92105bb7 176 void __iomem *base;
5e1c5ff4
TL		 177 u16 irq;
178 u16 virtual_irq_start;
92105bb7 179 int method;
44169075
SS		 180#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
181 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 182 u32 suspend_wakeup;
183 u32 saved_wakeup;
3ac4fa99 184#endif
44169075
SS		 185#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
186 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 187 u32 non_wakeup_gpios;
188 u32 enabled_non_wakeup_gpios;
189
190 u32 saved_datain;
191 u32 saved_fallingdetect;
192 u32 saved_risingdetect;
193#endif
b144ff6f 194 u32 level_mask;
5e1c5ff4 195 spinlock_t lock;
52e31344 196 struct gpio_chip chip;
89db9482 197 struct clk *dbck;
5e1c5ff4
TL		 198};
199
200#define METHOD_MPUIO 0
201#define METHOD_GPIO_1510 1
202#define METHOD_GPIO_1610 2
7c006926 203#define METHOD_GPIO_7XX 3
56739a69 204#define METHOD_GPIO_24XX 5
5e1c5ff4 205
92105bb7 206#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 207static struct gpio_bank gpio_bank_1610[5] = {
9f7065da
TL		 208 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
209 METHOD_MPUIO },
210 { OMAP1610_GPIO1_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
211 METHOD_GPIO_1610 },
212 { OMAP1610_GPIO2_BASE, NULL, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16,
213 METHOD_GPIO_1610 },
214 { OMAP1610_GPIO3_BASE, NULL, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32,
215 METHOD_GPIO_1610 },
216 { OMAP1610_GPIO4_BASE, NULL, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48,
217 METHOD_GPIO_1610 },
5e1c5ff4
TL		 218};
219#endif
220
1a8bfa1e 221#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 222static struct gpio_bank gpio_bank_1510[2] = {
9f7065da
TL		 223 { OMAP1_MPUIO_VBASE, NULL, INT_MPUIO, IH_MPUIO_BASE,
224 METHOD_MPUIO },
225 { OMAP1510_GPIO_BASE, NULL, INT_GPIO_BANK1, IH_GPIO_BASE,
226 METHOD_GPIO_1510 }
5e1c5ff4
TL		 227};
228#endif
229
b718aa81 230#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926 231static struct gpio_bank gpio_bank_7xx[7] = {
9f7065da
TL		 232 { OMAP1_MPUIO_VBASE, NULL, INT_7XX_MPUIO, IH_MPUIO_BASE,
233 METHOD_MPUIO },
234 { OMAP7XX_GPIO1_BASE, NULL, INT_7XX_GPIO_BANK1, IH_GPIO_BASE,
235 METHOD_GPIO_7XX },
236 { OMAP7XX_GPIO2_BASE, NULL, INT_7XX_GPIO_BANK2, IH_GPIO_BASE + 32,
237 METHOD_GPIO_7XX },
238 { OMAP7XX_GPIO3_BASE, NULL, INT_7XX_GPIO_BANK3, IH_GPIO_BASE + 64,
239 METHOD_GPIO_7XX },
240 { OMAP7XX_GPIO4_BASE, NULL, INT_7XX_GPIO_BANK4, IH_GPIO_BASE + 96,
241 METHOD_GPIO_7XX },
242 { OMAP7XX_GPIO5_BASE, NULL, INT_7XX_GPIO_BANK5, IH_GPIO_BASE + 128,
243 METHOD_GPIO_7XX },
244 { OMAP7XX_GPIO6_BASE, NULL, INT_7XX_GPIO_BANK6, IH_GPIO_BASE + 160,
245 METHOD_GPIO_7XX },
5e1c5ff4
TL		 246};
247#endif
248
92105bb7 249#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 250
251static struct gpio_bank gpio_bank_242x[4] = {
9f7065da
TL		 252 { OMAP242X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
253 METHOD_GPIO_24XX },
254 { OMAP242X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
255 METHOD_GPIO_24XX },
256 { OMAP242X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
257 METHOD_GPIO_24XX },
258 { OMAP242X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
259 METHOD_GPIO_24XX },
92105bb7 260};
56a25641
SMK		 261
262static struct gpio_bank gpio_bank_243x[5] = {
9f7065da
TL		 263 { OMAP243X_GPIO1_BASE, NULL, INT_24XX_GPIO_BANK1, IH_GPIO_BASE,
264 METHOD_GPIO_24XX },
265 { OMAP243X_GPIO2_BASE, NULL, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32,
266 METHOD_GPIO_24XX },
267 { OMAP243X_GPIO3_BASE, NULL, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64,
268 METHOD_GPIO_24XX },
269 { OMAP243X_GPIO4_BASE, NULL, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96,
270 METHOD_GPIO_24XX },
271 { OMAP243X_GPIO5_BASE, NULL, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128,
272 METHOD_GPIO_24XX },
56a25641
SMK		 273};
274
92105bb7
TL		 275#endif
276
5492fb1a
SMK		 277#ifdef CONFIG_ARCH_OMAP34XX
278static struct gpio_bank gpio_bank_34xx[6] = {
9f7065da
TL		 279 { OMAP34XX_GPIO1_BASE, NULL, INT_34XX_GPIO_BANK1, IH_GPIO_BASE,
280 METHOD_GPIO_24XX },
281 { OMAP34XX_GPIO2_BASE, NULL, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32,
282 METHOD_GPIO_24XX },
283 { OMAP34XX_GPIO3_BASE, NULL, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64,
284 METHOD_GPIO_24XX },
285 { OMAP34XX_GPIO4_BASE, NULL, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96,
286 METHOD_GPIO_24XX },
287 { OMAP34XX_GPIO5_BASE, NULL, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128,
288 METHOD_GPIO_24XX },
289 { OMAP34XX_GPIO6_BASE, NULL, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160,
290 METHOD_GPIO_24XX },
5492fb1a
SMK		 291};
292
40c670f0
RN		 293struct omap3_gpio_regs {
294 u32 sysconfig;
295 u32 irqenable1;
296 u32 irqenable2;
297 u32 wake_en;
298 u32 ctrl;
299 u32 oe;
300 u32 leveldetect0;
301 u32 leveldetect1;
302 u32 risingdetect;
303 u32 fallingdetect;
304 u32 dataout;
305 u32 setwkuena;
306 u32 setdataout;
5492fb1a
SMK		 307};
308
40c670f0 309static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 310#endif
311
44169075
SS		 312#ifdef CONFIG_ARCH_OMAP4
313static struct gpio_bank gpio_bank_44xx[6] = {
9f7065da 314 { OMAP44XX_GPIO1_BASE, NULL, INT_44XX_GPIO_BANK1, IH_GPIO_BASE,
44169075 315 METHOD_GPIO_24XX },
9f7065da 316 { OMAP44XX_GPIO2_BASE, NULL, INT_44XX_GPIO_BANK2, IH_GPIO_BASE + 32,
44169075 317 METHOD_GPIO_24XX },
9f7065da 318 { OMAP44XX_GPIO3_BASE, NULL, INT_44XX_GPIO_BANK3, IH_GPIO_BASE + 64,
44169075 319 METHOD_GPIO_24XX },
9f7065da 320 { OMAP44XX_GPIO4_BASE, NULL, INT_44XX_GPIO_BANK4, IH_GPIO_BASE + 96,
44169075 321 METHOD_GPIO_24XX },
9f7065da 322 { OMAP44XX_GPIO5_BASE, NULL, INT_44XX_GPIO_BANK5, IH_GPIO_BASE + 128,
44169075 323 METHOD_GPIO_24XX },
9f7065da 324 { OMAP44XX_GPIO6_BASE, NULL, INT_44XX_GPIO_BANK6, IH_GPIO_BASE + 160,
44169075
SS		 325 METHOD_GPIO_24XX },
326};
327
328#endif
329
5e1c5ff4
TL		 330static struct gpio_bank *gpio_bank;
331static int gpio_bank_count;
332
333static inline struct gpio_bank *get_gpio_bank(int gpio)
334{
6e60e79a 335 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 336 if (OMAP_GPIO_IS_MPUIO(gpio))
337 return &gpio_bank[0];
338 return &gpio_bank[1];
339 }
5e1c5ff4
TL		 340 if (cpu_is_omap16xx()) {
341 if (OMAP_GPIO_IS_MPUIO(gpio))
342 return &gpio_bank[0];
343 return &gpio_bank[1 + (gpio >> 4)];
344 }
56739a69 345 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 346 if (OMAP_GPIO_IS_MPUIO(gpio))
347 return &gpio_bank[0];
348 return &gpio_bank[1 + (gpio >> 5)];
349 }
92105bb7
TL		 350 if (cpu_is_omap24xx())
351 return &gpio_bank[gpio >> 5];
44169075 352 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 353 return &gpio_bank[gpio >> 5];
e031ab23
DB		 354 BUG();
355 return NULL;
5e1c5ff4
TL		 356}
357
358static inline int get_gpio_index(int gpio)
359{
56739a69 360 if (cpu_is_omap7xx())
5e1c5ff4 361 return gpio & 0x1f;
92105bb7
TL		 362 if (cpu_is_omap24xx())
363 return gpio & 0x1f;
44169075 364 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 365 return gpio & 0x1f;
92105bb7 366 return gpio & 0x0f;
5e1c5ff4
TL		 367}
368
369static inline int gpio_valid(int gpio)
370{
371 if (gpio < 0)
372 return -1;
d11ac979 373 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 374 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 375 return -1;
376 return 0;
377 }
6e60e79a 378 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 379 return 0;
5e1c5ff4
TL		 380 if ((cpu_is_omap16xx()) && gpio < 64)
381 return 0;
56739a69 382 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 383 return 0;
92105bb7
TL		 384 if (cpu_is_omap24xx() && gpio < 128)
385 return 0;
44169075 386 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 387 return 0;
5e1c5ff4
TL		 388 return -1;
389}
390
391static int check_gpio(int gpio)
392{
d32b20fc 393 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 394 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
395 dump_stack();
396 return -1;
397 }
398 return 0;
399}
400
401static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
402{
92105bb7 403 void __iomem *reg = bank->base;
5e1c5ff4
TL		 404 u32 l;
405
406 switch (bank->method) {
e5c56ed3 407#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 408 case METHOD_MPUIO:
409 reg += OMAP_MPUIO_IO_CNTL;
410 break;
e5c56ed3
DB		 411#endif
412#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 413 case METHOD_GPIO_1510:
414 reg += OMAP1510_GPIO_DIR_CONTROL;
415 break;
e5c56ed3
DB		 416#endif
417#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 418 case METHOD_GPIO_1610:
419 reg += OMAP1610_GPIO_DIRECTION;
420 break;
e5c56ed3 421#endif
b718aa81 422#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 423 case METHOD_GPIO_7XX:
424 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 425 break;
426#endif
78a1a6d3 427#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 428 case METHOD_GPIO_24XX:
429 reg += OMAP24XX_GPIO_OE;
430 break;
78a1a6d3
SR		 431#endif
432#if defined(CONFIG_ARCH_OMAP4)
433 case METHOD_GPIO_24XX:
434 reg += OMAP4_GPIO_OE;
435 break;
e5c56ed3
DB		 436#endif
437 default:
438 WARN_ON(1);
439 return;
5e1c5ff4
TL		 440 }
441 l = __raw_readl(reg);
442 if (is_input)
443 l |= 1 << gpio;
444 else
445 l &= ~(1 << gpio);
446 __raw_writel(l, reg);
447}
448
5e1c5ff4
TL		 449static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
450{
92105bb7 451 void __iomem *reg = bank->base;
5e1c5ff4
TL		 452 u32 l = 0;
453
454 switch (bank->method) {
e5c56ed3 455#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 456 case METHOD_MPUIO:
457 reg += OMAP_MPUIO_OUTPUT;
458 l = __raw_readl(reg);
459 if (enable)
460 l |= 1 << gpio;
461 else
462 l &= ~(1 << gpio);
463 break;
e5c56ed3
DB		 464#endif
465#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 466 case METHOD_GPIO_1510:
467 reg += OMAP1510_GPIO_DATA_OUTPUT;
468 l = __raw_readl(reg);
469 if (enable)
470 l |= 1 << gpio;
471 else
472 l &= ~(1 << gpio);
473 break;
e5c56ed3
DB		 474#endif
475#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 476 case METHOD_GPIO_1610:
477 if (enable)
478 reg += OMAP1610_GPIO_SET_DATAOUT;
479 else
480 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
481 l = 1 << gpio;
482 break;
e5c56ed3 483#endif
b718aa81 484#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 485 case METHOD_GPIO_7XX:
486 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 487 l = __raw_readl(reg);
488 if (enable)
489 l |= 1 << gpio;
490 else
491 l &= ~(1 << gpio);
492 break;
493#endif
78a1a6d3 494#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 495 case METHOD_GPIO_24XX:
496 if (enable)
497 reg += OMAP24XX_GPIO_SETDATAOUT;
498 else
499 reg += OMAP24XX_GPIO_CLEARDATAOUT;
500 l = 1 << gpio;
501 break;
78a1a6d3
SR		 502#endif
503#ifdef CONFIG_ARCH_OMAP4
504 case METHOD_GPIO_24XX:
505 if (enable)
506 reg += OMAP4_GPIO_SETDATAOUT;
507 else
508 reg += OMAP4_GPIO_CLEARDATAOUT;
509 l = 1 << gpio;
510 break;
e5c56ed3 511#endif
5e1c5ff4 512 default:
e5c56ed3 513 WARN_ON(1);
5e1c5ff4
TL		 514 return;
515 }
516 __raw_writel(l, reg);
517}
518
b37c45b8 519static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 520{
92105bb7 521 void __iomem *reg;
5e1c5ff4
TL		 522
523 if (check_gpio(gpio) < 0)
e5c56ed3 524 return -EINVAL;
5e1c5ff4
TL		 525 reg = bank->base;
526 switch (bank->method) {
e5c56ed3 527#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 528 case METHOD_MPUIO:
529 reg += OMAP_MPUIO_INPUT_LATCH;
530 break;
e5c56ed3
DB		 531#endif
532#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 533 case METHOD_GPIO_1510:
534 reg += OMAP1510_GPIO_DATA_INPUT;
535 break;
e5c56ed3
DB		 536#endif
537#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 538 case METHOD_GPIO_1610:
539 reg += OMAP1610_GPIO_DATAIN;
540 break;
e5c56ed3 541#endif
b718aa81 542#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 543 case METHOD_GPIO_7XX:
544 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 545 break;
546#endif
78a1a6d3 547#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 548 case METHOD_GPIO_24XX:
549 reg += OMAP24XX_GPIO_DATAIN;
550 break;
78a1a6d3
SR		 551#endif
552#ifdef CONFIG_ARCH_OMAP4
553 case METHOD_GPIO_24XX:
554 reg += OMAP4_GPIO_DATAIN;
555 break;
e5c56ed3 556#endif
5e1c5ff4 557 default:
e5c56ed3 558 return -EINVAL;
5e1c5ff4 559 }
92105bb7
TL		 560 return (__raw_readl(reg)
561 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 562}
563
b37c45b8
RQ		 564static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
565{
566 void __iomem *reg;
567
568 if (check_gpio(gpio) < 0)
569 return -EINVAL;
570 reg = bank->base;
571
572 switch (bank->method) {
573#ifdef CONFIG_ARCH_OMAP1
574 case METHOD_MPUIO:
575 reg += OMAP_MPUIO_OUTPUT;
576 break;
577#endif
578#ifdef CONFIG_ARCH_OMAP15XX
579 case METHOD_GPIO_1510:
580 reg += OMAP1510_GPIO_DATA_OUTPUT;
581 break;
582#endif
583#ifdef CONFIG_ARCH_OMAP16XX
584 case METHOD_GPIO_1610:
585 reg += OMAP1610_GPIO_DATAOUT;
586 break;
587#endif
b718aa81 588#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 589 case METHOD_GPIO_7XX:
590 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 591 break;
592#endif
593#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
594 defined(CONFIG_ARCH_OMAP4)
595 case METHOD_GPIO_24XX:
596 reg += OMAP24XX_GPIO_DATAOUT;
597 break;
598#endif
599 default:
600 return -EINVAL;
601 }
602
603 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
604}
605
92105bb7
TL		 606#define MOD_REG_BIT(reg, bit_mask, set) \
607do { \
608 int l = __raw_readl(base + reg); \
609 if (set) l |= bit_mask; \
610 else l &= ~bit_mask; \
611 __raw_writel(l, base + reg); \
612} while(0)
613
5eb3bb9c
KH		 614void omap_set_gpio_debounce(int gpio, int enable)
615{
616 struct gpio_bank *bank;
617 void __iomem *reg;
e031ab23 618 unsigned long flags;
5eb3bb9c
KH		 619 u32 val, l = 1 << get_gpio_index(gpio);
620
621 if (cpu_class_is_omap1())
622 return;
623
624 bank = get_gpio_bank(gpio);
625 reg = bank->base;
78a1a6d3
SR		 626#ifdef CONFIG_ARCH_OMAP4
627 reg += OMAP4_GPIO_DEBOUNCENABLE;
628#else
5eb3bb9c 629 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
78a1a6d3 630#endif
e031ab23
DB		 631
632 spin_lock_irqsave(&bank->lock, flags);
5eb3bb9c
KH		 633 val = __raw_readl(reg);
634
89db9482 635 if (enable && !(val & l))
5eb3bb9c 636 val |= l;
e031ab23 637 else if (!enable && (val & l))
5eb3bb9c 638 val &= ~l;
89db9482 639 else
e031ab23 640 goto done;
89db9482 641
44169075 642 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
e031ab23
DB		 643 if (enable)
644 clk_enable(bank->dbck);
645 else
646 clk_disable(bank->dbck);
647 }
5eb3bb9c
KH		 648
649 __raw_writel(val, reg);
e031ab23
DB		 650done:
651 spin_unlock_irqrestore(&bank->lock, flags);
5eb3bb9c
KH		 652}
653EXPORT_SYMBOL(omap_set_gpio_debounce);
654
655void omap_set_gpio_debounce_time(int gpio, int enc_time)
656{
657 struct gpio_bank *bank;
658 void __iomem *reg;
659
660 if (cpu_class_is_omap1())
661 return;
662
663 bank = get_gpio_bank(gpio);
664 reg = bank->base;
665
666 enc_time &= 0xff;
78a1a6d3
SR		 667#ifdef CONFIG_ARCH_OMAP4
668 reg += OMAP4_GPIO_DEBOUNCINGTIME;
669#else
5eb3bb9c 670 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
78a1a6d3 671#endif
5eb3bb9c
KH		 672 __raw_writel(enc_time, reg);
673}
674EXPORT_SYMBOL(omap_set_gpio_debounce_time);
675
44169075
SS		 676#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
677 defined(CONFIG_ARCH_OMAP4)
5eb3bb9c
KH		 678static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
679 int trigger)
5e1c5ff4 680{
3ac4fa99 681 void __iomem *base = bank->base;
92105bb7 682 u32 gpio_bit = 1 << gpio;
78a1a6d3 683 u32 val;
92105bb7 684
78a1a6d3
SR		 685 if (cpu_is_omap44xx()) {
686 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
687 trigger & IRQ_TYPE_LEVEL_LOW);
688 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
689 trigger & IRQ_TYPE_LEVEL_HIGH);
690 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
691 trigger & IRQ_TYPE_EDGE_RISING);
692 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
693 trigger & IRQ_TYPE_EDGE_FALLING);
694 } else {
695 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
696 trigger & IRQ_TYPE_LEVEL_LOW);
697 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
698 trigger & IRQ_TYPE_LEVEL_HIGH);
699 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
700 trigger & IRQ_TYPE_EDGE_RISING);
701 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
702 trigger & IRQ_TYPE_EDGE_FALLING);
703 }
3ac4fa99 704 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3
SR		 705 if (cpu_is_omap44xx()) {
706 if (trigger != 0)
707 __raw_writel(1 << gpio, bank->base+
708 OMAP4_GPIO_IRQWAKEN0);
709 else {
710 val = __raw_readl(bank->base +
711 OMAP4_GPIO_IRQWAKEN0);
712 __raw_writel(val & (~(1 << gpio)), bank->base +
713 OMAP4_GPIO_IRQWAKEN0);
714 }
715 } else {
716 if (trigger != 0)
717 __raw_writel(1 << gpio, bank->base
5eb3bb9c 718 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 719 else
720 __raw_writel(1 << gpio, bank->base
5eb3bb9c 721 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 722 }
3ac4fa99
JY		 723 } else {
724 if (trigger != 0)
725 bank->enabled_non_wakeup_gpios |= gpio_bit;
726 else
727 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
728 }
5eb3bb9c 729
78a1a6d3
SR		 730 if (cpu_is_omap44xx()) {
731 bank->level_mask =
732 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
733 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
734 } else {
735 bank->level_mask =
736 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
737 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
738 }
92105bb7 739}
3ac4fa99 740#endif
92105bb7
TL		 741
742static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
743{
744 void __iomem *reg = bank->base;
745 u32 l = 0;
5e1c5ff4
TL		 746
747 switch (bank->method) {
e5c56ed3 748#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 749 case METHOD_MPUIO:
750 reg += OMAP_MPUIO_GPIO_INT_EDGE;
751 l = __raw_readl(reg);
6cab4860 752 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 753 l |= 1 << gpio;
6cab4860 754 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 755 l &= ~(1 << gpio);
92105bb7
TL		 756 else
757 goto bad;
5e1c5ff4 758 break;
e5c56ed3
DB		 759#endif
760#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 761 case METHOD_GPIO_1510:
762 reg += OMAP1510_GPIO_INT_CONTROL;
763 l = __raw_readl(reg);
6cab4860 764 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 765 l |= 1 << gpio;
6cab4860 766 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 767 l &= ~(1 << gpio);
92105bb7
TL		 768 else
769 goto bad;
5e1c5ff4 770 break;
e5c56ed3 771#endif
3ac4fa99 772#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 773 case METHOD_GPIO_1610:
5e1c5ff4
TL		 774 if (gpio & 0x08)
775 reg += OMAP1610_GPIO_EDGE_CTRL2;
776 else
777 reg += OMAP1610_GPIO_EDGE_CTRL1;
778 gpio &= 0x07;
779 l = __raw_readl(reg);
780 l &= ~(3 << (gpio << 1));
6cab4860 781 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 782 l |= 2 << (gpio << 1);
6cab4860 783 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 784 l |= 1 << (gpio << 1);
3ac4fa99
JY		 785 if (trigger)
786 /* Enable wake-up during idle for dynamic tick */
787 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
788 else
789 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 790 break;
3ac4fa99 791#endif
b718aa81 792#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 793 case METHOD_GPIO_7XX:
794 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69
ZM		 795 l = __raw_readl(reg);
796 if (trigger & IRQ_TYPE_EDGE_RISING)
797 l |= 1 << gpio;
798 else if (trigger & IRQ_TYPE_EDGE_FALLING)
799 l &= ~(1 << gpio);
800 else
801 goto bad;
802 break;
803#endif
44169075
SS		 804#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
805 defined(CONFIG_ARCH_OMAP4)
92105bb7 806 case METHOD_GPIO_24XX:
3ac4fa99 807 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 808 break;
3ac4fa99 809#endif
5e1c5ff4 810 default:
92105bb7 811 goto bad;
5e1c5ff4 812 }
92105bb7
TL		 813 __raw_writel(l, reg);
814 return 0;
815bad:
816 return -EINVAL;
5e1c5ff4
TL		 817}
818
92105bb7 819static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 820{
821 struct gpio_bank *bank;
92105bb7
TL		 822 unsigned gpio;
823 int retval;
a6472533 824 unsigned long flags;
92105bb7 825
5492fb1a 826 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 827 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
828 else
829 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 830
831 if (check_gpio(gpio) < 0)
92105bb7
TL		 832 return -EINVAL;
833
e5c56ed3 834 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 835 return -EINVAL;
e5c56ed3
DB		 836
837 /* OMAP1 allows only only edge triggering */
5492fb1a 838 if (!cpu_class_is_omap2()
e5c56ed3 839 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 840 return -EINVAL;
841
58781016 842 bank = get_irq_chip_data(irq);
a6472533 843 spin_lock_irqsave(&bank->lock, flags);
92105bb7 844 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 845 if (retval == 0) {
846 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
847 irq_desc[irq].status |= type;
848 }
a6472533 849 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 850
851 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
852 __set_irq_handler_unlocked(irq, handle_level_irq);
853 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
854 __set_irq_handler_unlocked(irq, handle_edge_irq);
855
92105bb7 856 return retval;
5e1c5ff4
TL		 857}
858
859static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
860{
92105bb7 861 void __iomem *reg = bank->base;
5e1c5ff4
TL		 862
863 switch (bank->method) {
e5c56ed3 864#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 865 case METHOD_MPUIO:
866 /* MPUIO irqstatus is reset by reading the status register,
867 * so do nothing here */
868 return;
e5c56ed3
DB		 869#endif
870#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 871 case METHOD_GPIO_1510:
872 reg += OMAP1510_GPIO_INT_STATUS;
873 break;
e5c56ed3
DB		 874#endif
875#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 876 case METHOD_GPIO_1610:
877 reg += OMAP1610_GPIO_IRQSTATUS1;
878 break;
e5c56ed3 879#endif
b718aa81 880#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 881 case METHOD_GPIO_7XX:
882 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 883 break;
884#endif
78a1a6d3 885#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 886 case METHOD_GPIO_24XX:
887 reg += OMAP24XX_GPIO_IRQSTATUS1;
888 break;
78a1a6d3
SR		 889#endif
890#if defined(CONFIG_ARCH_OMAP4)
891 case METHOD_GPIO_24XX:
892 reg += OMAP4_GPIO_IRQSTATUS0;
893 break;
e5c56ed3 894#endif
5e1c5ff4 895 default:
e5c56ed3 896 WARN_ON(1);
5e1c5ff4
TL		 897 return;
898 }
899 __raw_writel(gpio_mask, reg);
bee7930f
HD		 900
901 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a 902#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
bedfd154 903 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
78a1a6d3
SR		 904#endif
905#if defined(CONFIG_ARCH_OMAP4)
906 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
907#endif
908 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 909 __raw_writel(gpio_mask, reg);
910
911 /* Flush posted write for the irq status to avoid spurious interrupts */
912 __raw_readl(reg);
78a1a6d3 913 }
5e1c5ff4
TL		 914}
915
916static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
917{
918 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
919}
920
ea6dedd7
ID		 921static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
922{
923 void __iomem *reg = bank->base;
99c47707
ID		 924 int inv = 0;
925 u32 l;
926 u32 mask;
ea6dedd7
ID		 927
928 switch (bank->method) {
e5c56ed3 929#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 930 case METHOD_MPUIO:
931 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 932 mask = 0xffff;
933 inv = 1;
ea6dedd7 934 break;
e5c56ed3
DB		 935#endif
936#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 937 case METHOD_GPIO_1510:
938 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 939 mask = 0xffff;
940 inv = 1;
ea6dedd7 941 break;
e5c56ed3
DB		 942#endif
943#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 944 case METHOD_GPIO_1610:
945 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 946 mask = 0xffff;
ea6dedd7 947 break;
e5c56ed3 948#endif
b718aa81 949#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 950 case METHOD_GPIO_7XX:
951 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 952 mask = 0xffffffff;
953 inv = 1;
954 break;
955#endif
78a1a6d3 956#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 957 case METHOD_GPIO_24XX:
958 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 959 mask = 0xffffffff;
ea6dedd7 960 break;
78a1a6d3
SR		 961#endif
962#if defined(CONFIG_ARCH_OMAP4)
963 case METHOD_GPIO_24XX:
964 reg += OMAP4_GPIO_IRQSTATUSSET0;
965 mask = 0xffffffff;
966 break;
e5c56ed3 967#endif
ea6dedd7 968 default:
e5c56ed3 969 WARN_ON(1);
ea6dedd7
ID		 970 return 0;
971 }
972
99c47707
ID		 973 l = __raw_readl(reg);
974 if (inv)
975 l = ~l;
976 l &= mask;
977 return l;
ea6dedd7
ID		 978}
979
5e1c5ff4
TL		 980static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
981{
92105bb7 982 void __iomem *reg = bank->base;
5e1c5ff4
TL		 983 u32 l;
984
985 switch (bank->method) {
e5c56ed3 986#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 987 case METHOD_MPUIO:
988 reg += OMAP_MPUIO_GPIO_MASKIT;
989 l = __raw_readl(reg);
990 if (enable)
991 l &= ~(gpio_mask);
992 else
993 l |= gpio_mask;
994 break;
e5c56ed3
DB		 995#endif
996#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 997 case METHOD_GPIO_1510:
998 reg += OMAP1510_GPIO_INT_MASK;
999 l = __raw_readl(reg);
1000 if (enable)
1001 l &= ~(gpio_mask);
1002 else
1003 l |= gpio_mask;
1004 break;
e5c56ed3
DB		 1005#endif
1006#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 1007 case METHOD_GPIO_1610:
1008 if (enable)
1009 reg += OMAP1610_GPIO_SET_IRQENABLE1;
1010 else
1011 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
1012 l = gpio_mask;
1013 break;
e5c56ed3 1014#endif
b718aa81 1015#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1016 case METHOD_GPIO_7XX:
1017 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 1018 l = __raw_readl(reg);
1019 if (enable)
1020 l &= ~(gpio_mask);
1021 else
1022 l |= gpio_mask;
1023 break;
1024#endif
78a1a6d3 1025#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1026 case METHOD_GPIO_24XX:
1027 if (enable)
1028 reg += OMAP24XX_GPIO_SETIRQENABLE1;
1029 else
1030 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
1031 l = gpio_mask;
1032 break;
78a1a6d3
SR		 1033#endif
1034#ifdef CONFIG_ARCH_OMAP4
1035 case METHOD_GPIO_24XX:
1036 if (enable)
1037 reg += OMAP4_GPIO_IRQSTATUSSET0;
1038 else
1039 reg += OMAP4_GPIO_IRQSTATUSCLR0;
1040 l = gpio_mask;
1041 break;
e5c56ed3 1042#endif
5e1c5ff4 1043 default:
e5c56ed3 1044 WARN_ON(1);
5e1c5ff4
TL		 1045 return;
1046 }
1047 __raw_writel(l, reg);
1048}
1049
1050static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
1051{
1052 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
1053}
1054
92105bb7
TL		 1055/*
1056 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
1057 * 1510 does not seem to have a wake-up register. If JTAG is connected
1058 * to the target, system will wake up always on GPIO events. While
1059 * system is running all registered GPIO interrupts need to have wake-up
1060 * enabled. When system is suspended, only selected GPIO interrupts need
1061 * to have wake-up enabled.
1062 */
1063static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
1064{
a6472533
DB		 1065 unsigned long flags;
1066
92105bb7 1067 switch (bank->method) {
3ac4fa99 1068#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 1069 case METHOD_MPUIO:
92105bb7 1070 case METHOD_GPIO_1610:
a6472533 1071 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1072 if (enable)
92105bb7 1073 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1074 else
92105bb7 1075 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1076 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1077 return 0;
3ac4fa99 1078#endif
44169075
SS		 1079#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1080 defined(CONFIG_ARCH_OMAP4)
3ac4fa99 1081 case METHOD_GPIO_24XX:
11a78b79
DB		 1082 if (bank->non_wakeup_gpios & (1 << gpio)) {
1083 printk(KERN_ERR "Unable to modify wakeup on "
1084 "non-wakeup GPIO%d\n",
1085 (bank - gpio_bank) * 32 + gpio);
1086 return -EINVAL;
1087 }
a6472533 1088 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 1089 if (enable)
3ac4fa99 1090 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 1091 else
3ac4fa99 1092 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1093 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 1094 return 0;
1095#endif
92105bb7
TL		 1096 default:
1097 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1098 bank->method);
1099 return -EINVAL;
1100 }
1101}
1102
4196dd6b
TL		 1103static void _reset_gpio(struct gpio_bank *bank, int gpio)
1104{
1105 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1106 _set_gpio_irqenable(bank, gpio, 0);
1107 _clear_gpio_irqstatus(bank, gpio);
6cab4860 1108 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 1109}
1110
92105bb7
TL		 1111/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
1112static int gpio_wake_enable(unsigned int irq, unsigned int enable)
1113{
1114 unsigned int gpio = irq - IH_GPIO_BASE;
1115 struct gpio_bank *bank;
1116 int retval;
1117
1118 if (check_gpio(gpio) < 0)
1119 return -ENODEV;
58781016 1120 bank = get_irq_chip_data(irq);
92105bb7 1121 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 1122
1123 return retval;
1124}
1125
3ff164e1 1126static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1127{
3ff164e1 1128 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1129 unsigned long flags;
52e31344 1130
a6472533 1131 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1132
4196dd6b
TL		 1133 /* Set trigger to none. You need to enable the desired trigger with
1134 * request_irq() or set_irq_type().
1135 */
3ff164e1 1136 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 1137
1a8bfa1e 1138#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 1139 if (bank->method == METHOD_GPIO_1510) {
92105bb7 1140 void __iomem *reg;
5e1c5ff4 1141
92105bb7 1142 /* Claim the pin for MPU */
5e1c5ff4 1143 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 1144 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1145 }
1146#endif
a6472533 1147 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1148
1149 return 0;
1150}
1151
3ff164e1 1152static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1153{
3ff164e1 1154 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1155 unsigned long flags;
5e1c5ff4 1156
a6472533 1157 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1158#ifdef CONFIG_ARCH_OMAP16XX
1159 if (bank->method == METHOD_GPIO_1610) {
1160 /* Disable wake-up during idle for dynamic tick */
1161 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1162 __raw_writel(1 << offset, reg);
92105bb7
TL		 1163 }
1164#endif
44169075
SS		 1165#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1166 defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 1167 if (bank->method == METHOD_GPIO_24XX) {
1168 /* Disable wake-up during idle for dynamic tick */
1169 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1170 __raw_writel(1 << offset, reg);
92105bb7
TL		 1171 }
1172#endif
3ff164e1 1173 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1174 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1175}
1176
1177/*
1178 * We need to unmask the GPIO bank interrupt as soon as possible to
1179 * avoid missing GPIO interrupts for other lines in the bank.
1180 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1181 * in the bank to avoid missing nested interrupts for a GPIO line.
1182 * If we wait to unmask individual GPIO lines in the bank after the
1183 * line's interrupt handler has been run, we may miss some nested
1184 * interrupts.
1185 */
10dd5ce2 1186static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1187{
92105bb7 1188 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 1189 u32 isr;
1190 unsigned int gpio_irq;
1191 struct gpio_bank *bank;
ea6dedd7
ID		 1192 u32 retrigger = 0;
1193 int unmasked = 0;
5e1c5ff4
TL		 1194
1195 desc->chip->ack(irq);
1196
418ca1f0 1197 bank = get_irq_data(irq);
e5c56ed3 1198#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1199 if (bank->method == METHOD_MPUIO)
1200 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1201#endif
1a8bfa1e 1202#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1203 if (bank->method == METHOD_GPIO_1510)
1204 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1205#endif
1206#if defined(CONFIG_ARCH_OMAP16XX)
1207 if (bank->method == METHOD_GPIO_1610)
1208 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1209#endif
b718aa81 1210#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1211 if (bank->method == METHOD_GPIO_7XX)
1212 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1213#endif
78a1a6d3 1214#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1215 if (bank->method == METHOD_GPIO_24XX)
1216 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1217#endif
1218#if defined(CONFIG_ARCH_OMAP4)
1219 if (bank->method == METHOD_GPIO_24XX)
1220 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1221#endif
92105bb7 1222 while(1) {
6e60e79a 1223 u32 isr_saved, level_mask = 0;
ea6dedd7 1224 u32 enabled;
6e60e79a 1225
ea6dedd7
ID		 1226 enabled = _get_gpio_irqbank_mask(bank);
1227 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1228
1229 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1230 isr &= 0x0000ffff;
1231
5492fb1a 1232 if (cpu_class_is_omap2()) {
b144ff6f 1233 level_mask = bank->level_mask & enabled;
ea6dedd7 1234 }
6e60e79a
TL		 1235
1236 /* clear edge sensitive interrupts before handler(s) are
1237 called so that we don't miss any interrupt occurred while
1238 executing them */
1239 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1240 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1241 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1242
1243 /* if there is only edge sensitive GPIO pin interrupts
1244 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1245 if (!level_mask && !unmasked) {
1246 unmasked = 1;
6e60e79a 1247 desc->chip->unmask(irq);
ea6dedd7 1248 }
92105bb7 1249
ea6dedd7
ID		 1250 isr |= retrigger;
1251 retrigger = 0;
92105bb7
TL		 1252 if (!isr)
1253 break;
1254
1255 gpio_irq = bank->virtual_irq_start;
1256 for (; isr != 0; isr >>= 1, gpio_irq++) {
92105bb7
TL		 1257 if (!(isr & 1))
1258 continue;
29454dde 1259
d8aa0251 1260 generic_handle_irq(gpio_irq);
92105bb7 1261 }
1a8bfa1e 1262 }
ea6dedd7
ID		 1263 /* if bank has any level sensitive GPIO pin interrupt
1264 configured, we must unmask the bank interrupt only after
1265 handler(s) are executed in order to avoid spurious bank
1266 interrupt */
1267 if (!unmasked)
1268 desc->chip->unmask(irq);
1269
5e1c5ff4
TL		 1270}
1271
4196dd6b
TL		 1272static void gpio_irq_shutdown(unsigned int irq)
1273{
1274 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1275 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1276
1277 _reset_gpio(bank, gpio);
1278}
1279
5e1c5ff4
TL		 1280static void gpio_ack_irq(unsigned int irq)
1281{
1282 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1283 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1284
1285 _clear_gpio_irqstatus(bank, gpio);
1286}
1287
1288static void gpio_mask_irq(unsigned int irq)
1289{
1290 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1291 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1292
1293 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1294 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
5e1c5ff4
TL		 1295}
1296
1297static void gpio_unmask_irq(unsigned int irq)
1298{
1299 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1300 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f 1301 unsigned int irq_mask = 1 << get_gpio_index(gpio);
55b6019a
KH		 1302 struct irq_desc *desc = irq_to_desc(irq);
1303 u32 trigger = desc->status & IRQ_TYPE_SENSE_MASK;
1304
1305 if (trigger)
1306 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1307
1308 /* For level-triggered GPIOs, the clearing must be done after
1309 * the HW source is cleared, thus after the handler has run */
1310 if (bank->level_mask & irq_mask) {
1311 _set_gpio_irqenable(bank, gpio, 0);
1312 _clear_gpio_irqstatus(bank, gpio);
1313 }
5e1c5ff4 1314
4de8c75b 1315 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1316}
1317
e5c56ed3
DB		 1318static struct irq_chip gpio_irq_chip = {
1319 .name = "GPIO",
1320 .shutdown = gpio_irq_shutdown,
1321 .ack = gpio_ack_irq,
1322 .mask = gpio_mask_irq,
1323 .unmask = gpio_unmask_irq,
1324 .set_type = gpio_irq_type,
1325 .set_wake = gpio_wake_enable,
1326};
1327
1328/*---------------------------------------------------------------------*/
1329
1330#ifdef CONFIG_ARCH_OMAP1
1331
1332/* MPUIO uses the always-on 32k clock */
1333
5e1c5ff4
TL		 1334static void mpuio_ack_irq(unsigned int irq)
1335{
1336 /* The ISR is reset automatically, so do nothing here. */
1337}
1338
1339static void mpuio_mask_irq(unsigned int irq)
1340{
1341 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1342 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1343
1344 _set_gpio_irqenable(bank, gpio, 0);
1345}
1346
1347static void mpuio_unmask_irq(unsigned int irq)
1348{
1349 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1350 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1351
1352 _set_gpio_irqenable(bank, gpio, 1);
1353}
1354
e5c56ed3
DB		 1355static struct irq_chip mpuio_irq_chip = {
1356 .name = "MPUIO",
1357 .ack = mpuio_ack_irq,
1358 .mask = mpuio_mask_irq,
1359 .unmask = mpuio_unmask_irq,
92105bb7 1360 .set_type = gpio_irq_type,
11a78b79
DB		 1361#ifdef CONFIG_ARCH_OMAP16XX
1362 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1363 .set_wake = gpio_wake_enable,
1364#endif
5e1c5ff4
TL		 1365};
1366
e5c56ed3
DB		 1367
1368#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1369
11a78b79
DB		 1370
1371#ifdef CONFIG_ARCH_OMAP16XX
1372
1373#include <linux/platform_device.h>
1374
79ee031f 1375static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1376{
79ee031f 1377 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1378 struct gpio_bank *bank = platform_get_drvdata(pdev);
1379 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1380 unsigned long flags;
11a78b79 1381
a6472533 1382 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1383 bank->saved_wakeup = __raw_readl(mask_reg);
1384 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1385 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1386
1387 return 0;
1388}
1389
79ee031f 1390static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1391{
79ee031f 1392 struct platform_device *pdev = to_platform_device(dev);
11a78b79
DB		 1393 struct gpio_bank *bank = platform_get_drvdata(pdev);
1394 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1395 unsigned long flags;
11a78b79 1396
a6472533 1397 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1398 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1399 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1400
1401 return 0;
1402}
1403
79ee031f
MD		 1404static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
1405 .suspend_noirq = omap_mpuio_suspend_noirq,
1406 .resume_noirq = omap_mpuio_resume_noirq,
1407};
1408
11a78b79
DB		 1409/* use platform_driver for this, now that there's no longer any
1410 * point to sys_device (other than not disturbing old code).
1411 */
1412static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1413 .driver = {
1414 .name = "mpuio",
79ee031f 1415 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1416 },
1417};
1418
1419static struct platform_device omap_mpuio_device = {
1420 .name = "mpuio",
1421 .id = -1,
1422 .dev = {
1423 .driver = &omap_mpuio_driver.driver,
1424 }
1425 /* could list the /proc/iomem resources */
1426};
1427
1428static inline void mpuio_init(void)
1429{
fcf126d8
DB		 1430 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1431
11a78b79
DB		 1432 if (platform_driver_register(&omap_mpuio_driver) == 0)
1433 (void) platform_device_register(&omap_mpuio_device);
1434}
1435
1436#else
1437static inline void mpuio_init(void) {}
1438#endif /* 16xx */
1439
e5c56ed3
DB		 1440#else
1441
1442extern struct irq_chip mpuio_irq_chip;
1443
1444#define bank_is_mpuio(bank) 0
11a78b79 1445static inline void mpuio_init(void) {}
e5c56ed3
DB		 1446
1447#endif
1448
1449/*---------------------------------------------------------------------*/
5e1c5ff4 1450
52e31344
DB		 1451/* REVISIT these are stupid implementations! replace by ones that
1452 * don't switch on METHOD_* and which mostly avoid spinlocks
1453 */
1454
1455static int gpio_input(struct gpio_chip *chip, unsigned offset)
1456{
1457 struct gpio_bank *bank;
1458 unsigned long flags;
1459
1460 bank = container_of(chip, struct gpio_bank, chip);
1461 spin_lock_irqsave(&bank->lock, flags);
1462 _set_gpio_direction(bank, offset, 1);
1463 spin_unlock_irqrestore(&bank->lock, flags);
1464 return 0;
1465}
1466
b37c45b8
RQ		 1467static int gpio_is_input(struct gpio_bank *bank, int mask)
1468{
1469 void __iomem *reg = bank->base;
1470
1471 switch (bank->method) {
1472 case METHOD_MPUIO:
1473 reg += OMAP_MPUIO_IO_CNTL;
1474 break;
1475 case METHOD_GPIO_1510:
1476 reg += OMAP1510_GPIO_DIR_CONTROL;
1477 break;
1478 case METHOD_GPIO_1610:
1479 reg += OMAP1610_GPIO_DIRECTION;
1480 break;
7c006926
AB		 1481 case METHOD_GPIO_7XX:
1482 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1483 break;
1484 case METHOD_GPIO_24XX:
1485 reg += OMAP24XX_GPIO_OE;
1486 break;
1487 }
1488 return __raw_readl(reg) & mask;
1489}
1490
52e31344
DB		 1491static int gpio_get(struct gpio_chip *chip, unsigned offset)
1492{
b37c45b8
RQ		 1493 struct gpio_bank *bank;
1494 void __iomem *reg;
1495 int gpio;
1496 u32 mask;
1497
1498 gpio = chip->base + offset;
1499 bank = get_gpio_bank(gpio);
1500 reg = bank->base;
1501 mask = 1 << get_gpio_index(gpio);
1502
1503 if (gpio_is_input(bank, mask))
1504 return _get_gpio_datain(bank, gpio);
1505 else
1506 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1507}
1508
1509static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1510{
1511 struct gpio_bank *bank;
1512 unsigned long flags;
1513
1514 bank = container_of(chip, struct gpio_bank, chip);
1515 spin_lock_irqsave(&bank->lock, flags);
1516 _set_gpio_dataout(bank, offset, value);
1517 _set_gpio_direction(bank, offset, 0);
1518 spin_unlock_irqrestore(&bank->lock, flags);
1519 return 0;
1520}
1521
1522static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1523{
1524 struct gpio_bank *bank;
1525 unsigned long flags;
1526
1527 bank = container_of(chip, struct gpio_bank, chip);
1528 spin_lock_irqsave(&bank->lock, flags);
1529 _set_gpio_dataout(bank, offset, value);
1530 spin_unlock_irqrestore(&bank->lock, flags);
1531}
1532
a007b709
DB		 1533static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1534{
1535 struct gpio_bank *bank;
1536
1537 bank = container_of(chip, struct gpio_bank, chip);
1538 return bank->virtual_irq_start + offset;
1539}
1540
52e31344
DB		 1541/*---------------------------------------------------------------------*/
1542
1a8bfa1e 1543static int initialized;
44169075 1544#if !(defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4))
1a8bfa1e 1545static struct clk * gpio_ick;
5492fb1a
SMK		 1546#endif
1547
1548#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1549static struct clk * gpio_fck;
5492fb1a 1550#endif
5e1c5ff4 1551
5492fb1a 1552#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1553static struct clk * gpio5_ick;
1554static struct clk * gpio5_fck;
1555#endif
1556
44169075 1557#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
5492fb1a
SMK		 1558static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1559#endif
1560
9f7065da
TL		 1561static void __init omap_gpio_show_rev(void)
1562{
1563 u32 rev;
1564
1565 if (cpu_is_omap16xx())
1566 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1567 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
1568 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1569 else if (cpu_is_omap44xx())
1570 rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
1571 else
1572 return;
1573
1574 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1575 (rev >> 4) & 0x0f, rev & 0x0f);
1576}
1577
8ba55c5c
DB		 1578/* This lock class tells lockdep that GPIO irqs are in a different
1579 * category than their parents, so it won't report false recursion.
1580 */
1581static struct lock_class_key gpio_lock_class;
1582
5e1c5ff4
TL		 1583static int __init _omap_gpio_init(void)
1584{
1585 int i;
52e31344 1586 int gpio = 0;
5e1c5ff4 1587 struct gpio_bank *bank;
9f7065da 1588 int bank_size = SZ_8K; /* Module 4KB + L4 4KB except on omap1 */
5492fb1a 1589 char clk_name[11];
5e1c5ff4
TL		 1590
1591 initialized = 1;
1592
5492fb1a 1593#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1594 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1595 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1596 if (IS_ERR(gpio_ick))
92105bb7
TL		 1597 printk("Could not get arm_gpio_ck\n");
1598 else
30ff720b 1599 clk_enable(gpio_ick);
1a8bfa1e 1600 }
5492fb1a
SMK		 1601#endif
1602#if defined(CONFIG_ARCH_OMAP2)
1603 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1604 gpio_ick = clk_get(NULL, "gpios_ick");
1605 if (IS_ERR(gpio_ick))
1606 printk("Could not get gpios_ick\n");
1607 else
30ff720b 1608 clk_enable(gpio_ick);
1a8bfa1e 1609 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1610 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1611 printk("Could not get gpios_fck\n");
1612 else
30ff720b 1613 clk_enable(gpio_fck);
56a25641
SMK		 1614
1615 /*
5492fb1a 1616 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1617 */
5492fb1a 1618#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1619 if (cpu_is_omap2430()) {
1620 gpio5_ick = clk_get(NULL, "gpio5_ick");
1621 if (IS_ERR(gpio5_ick))
1622 printk("Could not get gpio5_ick\n");
1623 else
1624 clk_enable(gpio5_ick);
1625 gpio5_fck = clk_get(NULL, "gpio5_fck");
1626 if (IS_ERR(gpio5_fck))
1627 printk("Could not get gpio5_fck\n");
1628 else
1629 clk_enable(gpio5_fck);
1630 }
1631#endif
5492fb1a
SMK		 1632 }
1633#endif
1634
44169075
SS		 1635#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
1636 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
5492fb1a
SMK		 1637 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1638 sprintf(clk_name, "gpio%d_ick", i + 1);
1639 gpio_iclks[i] = clk_get(NULL, clk_name);
1640 if (IS_ERR(gpio_iclks[i]))
1641 printk(KERN_ERR "Could not get %s\n", clk_name);
1642 else
1643 clk_enable(gpio_iclks[i]);
5492fb1a
SMK		 1644 }
1645 }
1646#endif
1647
92105bb7 1648
1a8bfa1e 1649#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1650 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1651 gpio_bank_count = 2;
1652 gpio_bank = gpio_bank_1510;
9f7065da 1653 bank_size = SZ_2K;
5e1c5ff4
TL		 1654 }
1655#endif
1656#if defined(CONFIG_ARCH_OMAP16XX)
1657 if (cpu_is_omap16xx()) {
5e1c5ff4
TL		 1658 gpio_bank_count = 5;
1659 gpio_bank = gpio_bank_1610;
9f7065da 1660 bank_size = SZ_2K;
5e1c5ff4
TL		 1661 }
1662#endif
b718aa81
AB		 1663#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
1664 if (cpu_is_omap7xx()) {
56739a69 1665 gpio_bank_count = 7;
7c006926 1666 gpio_bank = gpio_bank_7xx;
9f7065da 1667 bank_size = SZ_2K;
56739a69
ZM		 1668 }
1669#endif
92105bb7 1670#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1671 if (cpu_is_omap242x()) {
92105bb7 1672 gpio_bank_count = 4;
56a25641 1673 gpio_bank = gpio_bank_242x;
56a25641
SMK		 1674 }
1675 if (cpu_is_omap243x()) {
56a25641
SMK		 1676 gpio_bank_count = 5;
1677 gpio_bank = gpio_bank_243x;
92105bb7 1678 }
5492fb1a
SMK		 1679#endif
1680#ifdef CONFIG_ARCH_OMAP34XX
1681 if (cpu_is_omap34xx()) {
5492fb1a
SMK		 1682 gpio_bank_count = OMAP34XX_NR_GPIOS;
1683 gpio_bank = gpio_bank_34xx;
5492fb1a 1684 }
44169075
SS		 1685#endif
1686#ifdef CONFIG_ARCH_OMAP4
1687 if (cpu_is_omap44xx()) {
44169075
SS		 1688 gpio_bank_count = OMAP34XX_NR_GPIOS;
1689 gpio_bank = gpio_bank_44xx;
44169075 1690 }
5e1c5ff4
TL		 1691#endif
1692 for (i = 0; i < gpio_bank_count; i++) {
1693 int j, gpio_count = 16;
1694
1695 bank = &gpio_bank[i];
5e1c5ff4 1696 spin_lock_init(&bank->lock);
9f7065da
TL		 1697
1698 /* Static mapping, never released */
1699 bank->base = ioremap(bank->pbase, bank_size);
1700 if (!bank->base) {
1701 printk(KERN_ERR "Could not ioremap gpio bank%i\n", i);
1702 continue;
1703 }
1704
e5c56ed3 1705 if (bank_is_mpuio(bank))
7c7095aa 1706 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1707 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1708 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1709 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1710 }
d11ac979 1711 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1712 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1713 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1714 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1715 }
7c006926
AB		 1716 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1717 __raw_writel(0xffffffff, bank->base + OMAP7XX_GPIO_INT_MASK);
1718 __raw_writel(0x00000000, bank->base + OMAP7XX_GPIO_INT_STATUS);
5e1c5ff4 1719
7c006926 1720 gpio_count = 32; /* 7xx has 32-bit GPIOs */
5e1c5ff4 1721 }
d11ac979 1722
44169075
SS		 1723#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1724 defined(CONFIG_ARCH_OMAP4)
92105bb7 1725 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1726 static const u32 non_wakeup_gpios[] = {
1727 0xe203ffc0, 0x08700040
1728 };
78a1a6d3
SR		 1729 if (cpu_is_omap44xx()) {
1730 __raw_writel(0xffffffff, bank->base +
1731 OMAP4_GPIO_IRQSTATUSCLR0);
1732 __raw_writew(0x0015, bank->base +
1733 OMAP4_GPIO_SYSCONFIG);
1734 __raw_writel(0x00000000, bank->base +
1735 OMAP4_GPIO_DEBOUNCENABLE);
1736 /* Initialize interface clock ungated, module enabled */
1737 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1738 } else {
92105bb7
TL		 1739 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1740 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf 1741 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
cb5793db 1742 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_DEBOUNCE_EN);
14f1c3bf
JY		 1743
1744 /* Initialize interface clock ungated, module enabled */
1745 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
78a1a6d3 1746 }
3ac4fa99
JY		 1747 if (i < ARRAY_SIZE(non_wakeup_gpios))
1748 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1749 gpio_count = 32;
1750 }
5e1c5ff4 1751#endif
52e31344
DB		 1752 /* REVISIT eventually switch from OMAP-specific gpio structs
1753 * over to the generic ones
1754 */
3ff164e1
JN		 1755 bank->chip.request = omap_gpio_request;
1756 bank->chip.free = omap_gpio_free;
52e31344
DB		 1757 bank->chip.direction_input = gpio_input;
1758 bank->chip.get = gpio_get;
1759 bank->chip.direction_output = gpio_output;
1760 bank->chip.set = gpio_set;
a007b709 1761 bank->chip.to_irq = gpio_2irq;
52e31344
DB		 1762 if (bank_is_mpuio(bank)) {
1763 bank->chip.label = "mpuio";
69114a47 1764#ifdef CONFIG_ARCH_OMAP16XX
d8f388d8
DB		 1765 bank->chip.dev = &omap_mpuio_device.dev;
1766#endif
52e31344
DB		 1767 bank->chip.base = OMAP_MPUIO(0);
1768 } else {
1769 bank->chip.label = "gpio";
1770 bank->chip.base = gpio;
1771 gpio += gpio_count;
1772 }
1773 bank->chip.ngpio = gpio_count;
1774
1775 gpiochip_add(&bank->chip);
1776
5e1c5ff4
TL		 1777 for (j = bank->virtual_irq_start;
1778 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1779 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1780 set_irq_chip_data(j, bank);
e5c56ed3 1781 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1782 set_irq_chip(j, &mpuio_irq_chip);
1783 else
1784 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1785 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1786 set_irq_flags(j, IRQF_VALID);
1787 }
1788 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1789 set_irq_data(bank->irq, bank);
89db9482 1790
44169075 1791 if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
89db9482
JH		 1792 sprintf(clk_name, "gpio%d_dbck", i + 1);
1793 bank->dbck = clk_get(NULL, clk_name);
1794 if (IS_ERR(bank->dbck))
1795 printk(KERN_ERR "Could not get %s\n", clk_name);
1796 }
5e1c5ff4
TL		 1797 }
1798
1799 /* Enable system clock for GPIO module.
1800 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1801 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1802 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1803
14f1c3bf
JY		 1804 /* Enable autoidle for the OCP interface */
1805 if (cpu_is_omap24xx())
1806 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1807 if (cpu_is_omap34xx())
1808 omap_writel(1 << 0, 0x48306814);
d11ac979 1809
9f7065da
TL		 1810 omap_gpio_show_rev();
1811
5e1c5ff4
TL		 1812 return 0;
1813}
1814
44169075
SS		 1815#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1816 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
92105bb7
TL		 1817static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1818{
1819 int i;
1820
5492fb1a 1821 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1822 return 0;
1823
1824 for (i = 0; i < gpio_bank_count; i++) {
1825 struct gpio_bank *bank = &gpio_bank[i];
1826 void __iomem *wake_status;
1827 void __iomem *wake_clear;
1828 void __iomem *wake_set;
a6472533 1829 unsigned long flags;
92105bb7
TL		 1830
1831 switch (bank->method) {
e5c56ed3 1832#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1833 case METHOD_GPIO_1610:
1834 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1835 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1836 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1837 break;
e5c56ed3 1838#endif
78a1a6d3 1839#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1840 case METHOD_GPIO_24XX:
723fdb78 1841 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1842 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1843 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1844 break;
78a1a6d3
SR		 1845#endif
1846#ifdef CONFIG_ARCH_OMAP4
1847 case METHOD_GPIO_24XX:
1848 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1849 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1850 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1851 break;
e5c56ed3 1852#endif
92105bb7
TL		 1853 default:
1854 continue;
1855 }
1856
a6472533 1857 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1858 bank->saved_wakeup = __raw_readl(wake_status);
1859 __raw_writel(0xffffffff, wake_clear);
1860 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1861 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1862 }
1863
1864 return 0;
1865}
1866
1867static int omap_gpio_resume(struct sys_device *dev)
1868{
1869 int i;
1870
723fdb78 1871 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1872 return 0;
1873
1874 for (i = 0; i < gpio_bank_count; i++) {
1875 struct gpio_bank *bank = &gpio_bank[i];
1876 void __iomem *wake_clear;
1877 void __iomem *wake_set;
a6472533 1878 unsigned long flags;
92105bb7
TL		 1879
1880 switch (bank->method) {
e5c56ed3 1881#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1882 case METHOD_GPIO_1610:
1883 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1884 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1885 break;
e5c56ed3 1886#endif
78a1a6d3 1887#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1888 case METHOD_GPIO_24XX:
0d9356cb
TL		 1889 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1890 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1891 break;
78a1a6d3
SR		 1892#endif
1893#ifdef CONFIG_ARCH_OMAP4
1894 case METHOD_GPIO_24XX:
1895 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1896 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1897 break;
e5c56ed3 1898#endif
92105bb7
TL		 1899 default:
1900 continue;
1901 }
1902
a6472533 1903 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1904 __raw_writel(0xffffffff, wake_clear);
1905 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1906 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1907 }
1908
1909 return 0;
1910}
1911
1912static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1913 .name = "gpio",
92105bb7
TL		 1914 .suspend = omap_gpio_suspend,
1915 .resume = omap_gpio_resume,
1916};
1917
1918static struct sys_device omap_gpio_device = {
1919 .id = 0,
1920 .cls = &omap_gpio_sysclass,
1921};
3ac4fa99
JY		 1922
1923#endif
1924
44169075
SS		 1925#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
1926 defined(CONFIG_ARCH_OMAP4)
3ac4fa99
JY		 1927
1928static int workaround_enabled;
1929
1930void omap2_gpio_prepare_for_retention(void)
1931{
1932 int i, c = 0;
1933
1934 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1935 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1936 for (i = 0; i < gpio_bank_count; i++) {
1937 struct gpio_bank *bank = &gpio_bank[i];
1938 u32 l1, l2;
1939
1940 if (!(bank->enabled_non_wakeup_gpios))
1941 continue;
78a1a6d3 1942#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1943 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1944 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1945 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
78a1a6d3
SR		 1946#endif
1947#ifdef CONFIG_ARCH_OMAP4
1948 bank->saved_datain = __raw_readl(bank->base +
1949 OMAP4_GPIO_DATAIN);
1950 l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
1951 l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
5492fb1a 1952#endif
3ac4fa99
JY		 1953 bank->saved_fallingdetect = l1;
1954 bank->saved_risingdetect = l2;
1955 l1 &= ~bank->enabled_non_wakeup_gpios;
1956 l2 &= ~bank->enabled_non_wakeup_gpios;
78a1a6d3 1957#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1958 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1959 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
78a1a6d3
SR		 1960#endif
1961#ifdef CONFIG_ARCH_OMAP4
1962 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1963 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
5492fb1a 1964#endif
3ac4fa99
JY		 1965 c++;
1966 }
1967 if (!c) {
1968 workaround_enabled = 0;
1969 return;
1970 }
1971 workaround_enabled = 1;
1972}
1973
1974void omap2_gpio_resume_after_retention(void)
1975{
1976 int i;
1977
1978 if (!workaround_enabled)
1979 return;
1980 for (i = 0; i < gpio_bank_count; i++) {
1981 struct gpio_bank *bank = &gpio_bank[i];
82dbb9d3 1982 u32 l, gen, gen0, gen1;
3ac4fa99
JY		 1983
1984 if (!(bank->enabled_non_wakeup_gpios))
1985 continue;
78a1a6d3 1986#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1987 __raw_writel(bank->saved_fallingdetect,
1988 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1989 __raw_writel(bank->saved_risingdetect,
1990 bank->base + OMAP24XX_GPIO_RISINGDETECT);
78a1a6d3
SR		 1991 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1992#endif
1993#ifdef CONFIG_ARCH_OMAP4
1994 __raw_writel(bank->saved_fallingdetect,
1995 bank->base + OMAP4_GPIO_FALLINGDETECT);
1996 __raw_writel(bank->saved_risingdetect,
1997 bank->base + OMAP4_GPIO_RISINGDETECT);
1998 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
5492fb1a 1999#endif
3ac4fa99
JY		 2000 /* Check if any of the non-wakeup interrupt GPIOs have changed
2001 * state. If so, generate an IRQ by software. This is
2002 * horribly racy, but it's the best we can do to work around
2003 * this silicon bug. */
3ac4fa99
JY		 2004 l ^= bank->saved_datain;
2005 l &= bank->non_wakeup_gpios;
82dbb9d3
EN		 2006
2007 /*
2008 * No need to generate IRQs for the rising edge for gpio IRQs
2009 * configured with falling edge only; and vice versa.
2010 */
2011 gen0 = l & bank->saved_fallingdetect;
2012 gen0 &= bank->saved_datain;
2013
2014 gen1 = l & bank->saved_risingdetect;
2015 gen1 &= ~(bank->saved_datain);
2016
2017 /* FIXME: Consider GPIO IRQs with level detections properly! */
2018 gen = l & (~(bank->saved_fallingdetect) &
2019 ~(bank->saved_risingdetect));
2020 /* Consider all GPIO IRQs needed to be updated */
2021 gen |= gen0 | gen1;
2022
2023 if (gen) {
3ac4fa99 2024 u32 old0, old1;
78a1a6d3 2025#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 2026 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2027 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
82dbb9d3
EN		 2028 __raw_writel(old0 | gen, bank->base +
2029 OMAP24XX_GPIO_LEVELDETECT0);
2030 __raw_writel(old1 | gen, bank->base +
2031 OMAP24XX_GPIO_LEVELDETECT1);
3ac4fa99
JY		 2032 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2033 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
78a1a6d3
SR		 2034#endif
2035#ifdef CONFIG_ARCH_OMAP4
2036 old0 = __raw_readl(bank->base +
2037 OMAP4_GPIO_LEVELDETECT0);
2038 old1 = __raw_readl(bank->base +
2039 OMAP4_GPIO_LEVELDETECT1);
2040 __raw_writel(old0 | l, bank->base +
2041 OMAP4_GPIO_LEVELDETECT0);
2042 __raw_writel(old1 | l, bank->base +
2043 OMAP4_GPIO_LEVELDETECT1);
2044 __raw_writel(old0, bank->base +
2045 OMAP4_GPIO_LEVELDETECT0);
2046 __raw_writel(old1, bank->base +
2047 OMAP4_GPIO_LEVELDETECT1);
5492fb1a 2048#endif
3ac4fa99
JY		 2049 }
2050 }
2051
2052}
2053
92105bb7
TL		 2054#endif
2055
40c670f0
RN		 2056#ifdef CONFIG_ARCH_OMAP34XX
2057/* save the registers of bank 2-6 */
2058void omap_gpio_save_context(void)
2059{
2060 int i;
2061
2062 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2063 for (i = 1; i < gpio_bank_count; i++) {
2064 struct gpio_bank *bank = &gpio_bank[i];
2065 gpio_context[i].sysconfig =
2066 __raw_readl(bank->base + OMAP24XX_GPIO_SYSCONFIG);
2067 gpio_context[i].irqenable1 =
2068 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2069 gpio_context[i].irqenable2 =
2070 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2071 gpio_context[i].wake_en =
2072 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2073 gpio_context[i].ctrl =
2074 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2075 gpio_context[i].oe =
2076 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2077 gpio_context[i].leveldetect0 =
2078 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2079 gpio_context[i].leveldetect1 =
2080 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2081 gpio_context[i].risingdetect =
2082 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2083 gpio_context[i].fallingdetect =
2084 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2085 gpio_context[i].dataout =
2086 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
2087 gpio_context[i].setwkuena =
2088 __raw_readl(bank->base + OMAP24XX_GPIO_SETWKUENA);
2089 gpio_context[i].setdataout =
2090 __raw_readl(bank->base + OMAP24XX_GPIO_SETDATAOUT);
2091 }
2092}
2093
2094/* restore the required registers of bank 2-6 */
2095void omap_gpio_restore_context(void)
2096{
2097 int i;
2098
2099 for (i = 1; i < gpio_bank_count; i++) {
2100 struct gpio_bank *bank = &gpio_bank[i];
2101 __raw_writel(gpio_context[i].sysconfig,
2102 bank->base + OMAP24XX_GPIO_SYSCONFIG);
2103 __raw_writel(gpio_context[i].irqenable1,
2104 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2105 __raw_writel(gpio_context[i].irqenable2,
2106 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2107 __raw_writel(gpio_context[i].wake_en,
2108 bank->base + OMAP24XX_GPIO_WAKE_EN);
2109 __raw_writel(gpio_context[i].ctrl,
2110 bank->base + OMAP24XX_GPIO_CTRL);
2111 __raw_writel(gpio_context[i].oe,
2112 bank->base + OMAP24XX_GPIO_OE);
2113 __raw_writel(gpio_context[i].leveldetect0,
2114 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2115 __raw_writel(gpio_context[i].leveldetect1,
2116 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2117 __raw_writel(gpio_context[i].risingdetect,
2118 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2119 __raw_writel(gpio_context[i].fallingdetect,
2120 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2121 __raw_writel(gpio_context[i].dataout,
2122 bank->base + OMAP24XX_GPIO_DATAOUT);
2123 __raw_writel(gpio_context[i].setwkuena,
2124 bank->base + OMAP24XX_GPIO_SETWKUENA);
2125 __raw_writel(gpio_context[i].setdataout,
2126 bank->base + OMAP24XX_GPIO_SETDATAOUT);
2127 }
2128}
2129#endif
2130
5e1c5ff4
TL		 2131/*
2132 * This may get called early from board specific init
1a8bfa1e 2133 * for boards that have interrupts routed via FPGA.
5e1c5ff4 2134 */
277d58ef 2135int __init omap_gpio_init(void)
5e1c5ff4
TL		 2136{
2137 if (!initialized)
2138 return _omap_gpio_init();
2139 else
2140 return 0;
2141}
2142
92105bb7
TL		 2143static int __init omap_gpio_sysinit(void)
2144{
2145 int ret = 0;
2146
2147 if (!initialized)
2148 ret = _omap_gpio_init();
2149
11a78b79
DB		 2150 mpuio_init();
2151
44169075
SS		 2152#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
2153 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
5492fb1a 2154 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 2155 if (ret == 0) {
2156 ret = sysdev_class_register(&omap_gpio_sysclass);
2157 if (ret == 0)
2158 ret = sysdev_register(&omap_gpio_device);
2159 }
2160 }
2161#endif
2162
2163 return ret;
2164}
2165
92105bb7 2166arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 2167
2168
2169#ifdef CONFIG_DEBUG_FS
2170
2171#include <linux/debugfs.h>
2172#include <linux/seq_file.h>
2173
b9772a22
DB		 2174static int dbg_gpio_show(struct seq_file *s, void *unused)
2175{
2176 unsigned i, j, gpio;
2177
2178 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
2179 struct gpio_bank *bank = gpio_bank + i;
2180 unsigned bankwidth = 16;
2181 u32 mask = 1;
2182
e5c56ed3 2183 if (bank_is_mpuio(bank))
b9772a22 2184 gpio = OMAP_MPUIO(0);
b718aa81 2185 else if (cpu_class_is_omap2() || cpu_is_omap7xx())
b9772a22
DB		 2186 bankwidth = 32;
2187
2188 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
2189 unsigned irq, value, is_in, irqstat;
52e31344 2190 const char *label;
b9772a22 2191
52e31344
DB		 2192 label = gpiochip_is_requested(&bank->chip, j);
2193 if (!label)
b9772a22
DB		 2194 continue;
2195
2196 irq = bank->virtual_irq_start + j;
0b84b5ca 2197 value = gpio_get_value(gpio);
b9772a22
DB		 2198 is_in = gpio_is_input(bank, mask);
2199
e5c56ed3 2200 if (bank_is_mpuio(bank))
52e31344 2201 seq_printf(s, "MPUIO %2d ", j);
b9772a22 2202 else
52e31344 2203 seq_printf(s, "GPIO %3d ", gpio);
21c867f1 2204 seq_printf(s, "(%-20.20s): %s %s",
52e31344 2205 label,
b9772a22
DB		 2206 is_in ? "in " : "out",
2207 value ? "hi" : "lo");
2208
52e31344
DB		 2209/* FIXME for at least omap2, show pullup/pulldown state */
2210
b9772a22 2211 irqstat = irq_desc[irq].status;
3a26e331 2212#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
44169075 2213 defined(CONFIG_ARCH_OMAP34XX) || defined(CONFIG_ARCH_OMAP4)
b9772a22
DB		 2214 if (is_in && ((bank->suspend_wakeup & mask)
2215 || irqstat & IRQ_TYPE_SENSE_MASK)) {
2216 char *trigger = NULL;
2217
2218 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
2219 case IRQ_TYPE_EDGE_FALLING:
2220 trigger = "falling";
2221 break;
2222 case IRQ_TYPE_EDGE_RISING:
2223 trigger = "rising";
2224 break;
2225 case IRQ_TYPE_EDGE_BOTH:
2226 trigger = "bothedge";
2227 break;
2228 case IRQ_TYPE_LEVEL_LOW:
2229 trigger = "low";
2230 break;
2231 case IRQ_TYPE_LEVEL_HIGH:
2232 trigger = "high";
2233 break;
2234 case IRQ_TYPE_NONE:
52e31344 2235 trigger = "(?)";
b9772a22
DB		 2236 break;
2237 }
52e31344 2238 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 2239 irq, trigger,
2240 (bank->suspend_wakeup & mask)
2241 ? " wakeup" : "");
2242 }
3a26e331 2243#endif
b9772a22
DB		 2244 seq_printf(s, "\n");
2245 }
2246
e5c56ed3 2247 if (bank_is_mpuio(bank)) {
b9772a22
DB		 2248 seq_printf(s, "\n");
2249 gpio = 0;
2250 }
2251 }
2252 return 0;
2253}
2254
2255static int dbg_gpio_open(struct inode *inode, struct file *file)
2256{
e5c56ed3 2257 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 2258}
2259
2260static const struct file_operations debug_fops = {
2261 .open = dbg_gpio_open,
2262 .read = seq_read,
2263 .llseek = seq_lseek,
2264 .release = single_release,
2265};
2266
2267static int __init omap_gpio_debuginit(void)
2268{
e5c56ed3
DB		 2269 (void) debugfs_create_file("omap_gpio", S_IRUGO,
2270 NULL, NULL, &debug_fops);
b9772a22
DB		 2271 return 0;
2272}
2273late_initcall(omap_gpio_debuginit);
2274#endif
Michael's Linux tree.