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ad67ef68 PW |
1 | /* |
2 | * OMAP2/3 powerdomain control | |
3 | * | |
55ed9694 PW |
4 | * Copyright (C) 2007-2008 Texas Instruments, Inc. |
5 | * Copyright (C) 2007-2009 Nokia Corporation | |
ad67ef68 PW |
6 | * |
7 | * Written by Paul Walmsley | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | */ | |
13 | ||
14 | #ifndef ASM_ARM_ARCH_OMAP_POWERDOMAIN | |
15 | #define ASM_ARM_ARCH_OMAP_POWERDOMAIN | |
16 | ||
17 | #include <linux/types.h> | |
18 | #include <linux/list.h> | |
19 | ||
20 | #include <asm/atomic.h> | |
21 | ||
ce491cf8 | 22 | #include <plat/cpu.h> |
ad67ef68 PW |
23 | |
24 | ||
25 | /* Powerdomain basic power states */ | |
26 | #define PWRDM_POWER_OFF 0x0 | |
27 | #define PWRDM_POWER_RET 0x1 | |
28 | #define PWRDM_POWER_INACTIVE 0x2 | |
29 | #define PWRDM_POWER_ON 0x3 | |
30 | ||
2354eb5a PW |
31 | #define PWRDM_MAX_PWRSTS 4 |
32 | ||
ad67ef68 | 33 | /* Powerdomain allowable state bitfields */ |
d3353e16 | 34 | #define PWRSTS_ON (1 << PWRDM_POWER_ON) |
ad67ef68 PW |
35 | #define PWRSTS_OFF_ON ((1 << PWRDM_POWER_OFF) | \ |
36 | (1 << PWRDM_POWER_ON)) | |
37 | ||
38 | #define PWRSTS_OFF_RET ((1 << PWRDM_POWER_OFF) | \ | |
39 | (1 << PWRDM_POWER_RET)) | |
40 | ||
f37c6dfa AP |
41 | #define PWRSTS_RET_ON ((1 << PWRDM_POWER_RET) | \ |
42 | (1 << PWRDM_POWER_ON)) | |
43 | ||
ad67ef68 PW |
44 | #define PWRSTS_OFF_RET_ON (PWRSTS_OFF_RET | (1 << PWRDM_POWER_ON)) |
45 | ||
46 | ||
0b7cbfb5 PW |
47 | /* Powerdomain flags */ |
48 | #define PWRDM_HAS_HDWR_SAR (1 << 0) /* hardware save-and-restore support */ | |
3863c74b TG |
49 | #define PWRDM_HAS_MPU_QUIRK (1 << 1) /* MPU pwr domain has MEM bank 0 bits |
50 | * in MEM bank 1 position. This is | |
51 | * true for OMAP3430 | |
52 | */ | |
90dbc7b0 RN |
53 | #define PWRDM_HAS_LOWPOWERSTATECHANGE (1 << 2) /* |
54 | * support to transition from a | |
55 | * sleep state to a lower sleep | |
56 | * state without waking up the | |
57 | * powerdomain | |
58 | */ | |
0b7cbfb5 | 59 | |
ad67ef68 | 60 | /* |
38900c27 AP |
61 | * Number of memory banks that are power-controllable. On OMAP4430, the |
62 | * maximum is 5. | |
ad67ef68 | 63 | */ |
38900c27 | 64 | #define PWRDM_MAX_MEM_BANKS 5 |
ad67ef68 | 65 | |
8420bb13 PW |
66 | /* |
67 | * Maximum number of clockdomains that can be associated with a powerdomain. | |
38900c27 | 68 | * CORE powerdomain on OMAP4 is the worst case |
8420bb13 | 69 | */ |
38900c27 | 70 | #define PWRDM_MAX_CLKDMS 9 |
8420bb13 | 71 | |
ad67ef68 PW |
72 | /* XXX A completely arbitrary number. What is reasonable here? */ |
73 | #define PWRDM_TRANSITION_BAILOUT 100000 | |
74 | ||
8420bb13 | 75 | struct clockdomain; |
ad67ef68 PW |
76 | struct powerdomain; |
77 | ||
f0271d65 PW |
78 | /** |
79 | * struct powerdomain - OMAP powerdomain | |
80 | * @name: Powerdomain name | |
81 | * @omap_chip: represents the OMAP chip types containing this pwrdm | |
82 | * @prcm_offs: the address offset from CM_BASE/PRM_BASE | |
83 | * @pwrsts: Possible powerdomain power states | |
84 | * @pwrsts_logic_ret: Possible logic power states when pwrdm in RETENTION | |
85 | * @flags: Powerdomain flags | |
86 | * @banks: Number of software-controllable memory banks in this powerdomain | |
87 | * @pwrsts_mem_ret: Possible memory bank pwrstates when pwrdm in RETENTION | |
88 | * @pwrsts_mem_on: Possible memory bank pwrstates when pwrdm in ON | |
89 | * @pwrdm_clkdms: Clockdomains in this powerdomain | |
90 | * @node: list_head linking all powerdomains | |
91 | * @state: | |
92 | * @state_counter: | |
93 | * @timer: | |
94 | * @state_timer: | |
95 | */ | |
ad67ef68 | 96 | struct powerdomain { |
ad67ef68 | 97 | const char *name; |
ad67ef68 | 98 | const struct omap_chip_id omap_chip; |
e0594b44 | 99 | const s16 prcm_offs; |
ad67ef68 | 100 | const u8 pwrsts; |
ad67ef68 | 101 | const u8 pwrsts_logic_ret; |
0b7cbfb5 | 102 | const u8 flags; |
ad67ef68 | 103 | const u8 banks; |
ad67ef68 | 104 | const u8 pwrsts_mem_ret[PWRDM_MAX_MEM_BANKS]; |
ad67ef68 | 105 | const u8 pwrsts_mem_on[PWRDM_MAX_MEM_BANKS]; |
8420bb13 | 106 | struct clockdomain *pwrdm_clkdms[PWRDM_MAX_CLKDMS]; |
ad67ef68 | 107 | struct list_head node; |
ba20bb12 | 108 | int state; |
2354eb5a | 109 | unsigned state_counter[PWRDM_MAX_PWRSTS]; |
cde08f81 TG |
110 | unsigned ret_logic_off_counter; |
111 | unsigned ret_mem_off_counter[PWRDM_MAX_MEM_BANKS]; | |
331b93f4 PDS |
112 | |
113 | #ifdef CONFIG_PM_DEBUG | |
114 | s64 timer; | |
2354eb5a | 115 | s64 state_timer[PWRDM_MAX_PWRSTS]; |
331b93f4 | 116 | #endif |
ad67ef68 PW |
117 | }; |
118 | ||
119 | ||
120 | void pwrdm_init(struct powerdomain **pwrdm_list); | |
121 | ||
ad67ef68 PW |
122 | struct powerdomain *pwrdm_lookup(const char *name); |
123 | ||
a23456e9 PDS |
124 | int pwrdm_for_each(int (*fn)(struct powerdomain *pwrdm, void *user), |
125 | void *user); | |
ee894b18 AB |
126 | int pwrdm_for_each_nolock(int (*fn)(struct powerdomain *pwrdm, void *user), |
127 | void *user); | |
ad67ef68 | 128 | |
8420bb13 PW |
129 | int pwrdm_add_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); |
130 | int pwrdm_del_clkdm(struct powerdomain *pwrdm, struct clockdomain *clkdm); | |
131 | int pwrdm_for_each_clkdm(struct powerdomain *pwrdm, | |
132 | int (*fn)(struct powerdomain *pwrdm, | |
133 | struct clockdomain *clkdm)); | |
134 | ||
ad67ef68 PW |
135 | int pwrdm_get_mem_bank_count(struct powerdomain *pwrdm); |
136 | ||
137 | int pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst); | |
138 | int pwrdm_read_next_pwrst(struct powerdomain *pwrdm); | |
fecb494b | 139 | int pwrdm_read_pwrst(struct powerdomain *pwrdm); |
ad67ef68 PW |
140 | int pwrdm_read_prev_pwrst(struct powerdomain *pwrdm); |
141 | int pwrdm_clear_all_prev_pwrst(struct powerdomain *pwrdm); | |
142 | ||
143 | int pwrdm_set_logic_retst(struct powerdomain *pwrdm, u8 pwrst); | |
144 | int pwrdm_set_mem_onst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
145 | int pwrdm_set_mem_retst(struct powerdomain *pwrdm, u8 bank, u8 pwrst); | |
146 | ||
147 | int pwrdm_read_logic_pwrst(struct powerdomain *pwrdm); | |
148 | int pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm); | |
1e3d0d2b | 149 | int pwrdm_read_logic_retst(struct powerdomain *pwrdm); |
ad67ef68 PW |
150 | int pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank); |
151 | int pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank); | |
1e3d0d2b | 152 | int pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank); |
ad67ef68 | 153 | |
0b7cbfb5 PW |
154 | int pwrdm_enable_hdwr_sar(struct powerdomain *pwrdm); |
155 | int pwrdm_disable_hdwr_sar(struct powerdomain *pwrdm); | |
156 | bool pwrdm_has_hdwr_sar(struct powerdomain *pwrdm); | |
157 | ||
ad67ef68 PW |
158 | int pwrdm_wait_transition(struct powerdomain *pwrdm); |
159 | ||
ba20bb12 PDS |
160 | int pwrdm_state_switch(struct powerdomain *pwrdm); |
161 | int pwrdm_clkdm_state_switch(struct clockdomain *clkdm); | |
162 | int pwrdm_pre_transition(void); | |
163 | int pwrdm_post_transition(void); | |
164 | ||
ad67ef68 | 165 | #endif |