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Commit | Line | Data |
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f35ae634 | 1 | /* |
5e1c5ff4 TL |
2 | * arch/arm/plat-omap/usb.c -- platform level USB initialization |
3 | * | |
4 | * Copyright (C) 2004 Texas Instruments, Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | */ | |
20 | ||
21 | #undef DEBUG | |
22 | ||
5e1c5ff4 TL |
23 | #include <linux/module.h> |
24 | #include <linux/kernel.h> | |
25 | #include <linux/types.h> | |
26 | #include <linux/errno.h> | |
27 | #include <linux/init.h> | |
d052d1be | 28 | #include <linux/platform_device.h> |
3a16f7b4 | 29 | #include <linux/usb/otg.h> |
fced80c7 | 30 | #include <linux/io.h> |
5e1c5ff4 | 31 | |
5e1c5ff4 TL |
32 | #include <asm/irq.h> |
33 | #include <asm/system.h> | |
a09e64fb | 34 | #include <mach/hardware.h> |
5e1c5ff4 | 35 | |
a09e64fb RK |
36 | #include <mach/control.h> |
37 | #include <mach/mux.h> | |
38 | #include <mach/usb.h> | |
39 | #include <mach/board.h> | |
5e1c5ff4 | 40 | |
c40fae95 TL |
41 | #ifdef CONFIG_ARCH_OMAP1 |
42 | ||
43 | #define INT_USB_IRQ_GEN IH2_BASE + 20 | |
44 | #define INT_USB_IRQ_NISO IH2_BASE + 30 | |
45 | #define INT_USB_IRQ_ISO IH2_BASE + 29 | |
46 | #define INT_USB_IRQ_HGEN INT_USB_HHC_1 | |
47 | #define INT_USB_IRQ_OTG IH2_BASE + 8 | |
48 | ||
49 | #else | |
50 | ||
51 | #define INT_USB_IRQ_GEN INT_24XX_USB_IRQ_GEN | |
52 | #define INT_USB_IRQ_NISO INT_24XX_USB_IRQ_NISO | |
53 | #define INT_USB_IRQ_ISO INT_24XX_USB_IRQ_ISO | |
54 | #define INT_USB_IRQ_HGEN INT_24XX_USB_IRQ_HGEN | |
55 | #define INT_USB_IRQ_OTG INT_24XX_USB_IRQ_OTG | |
56 | ||
57 | #endif | |
58 | ||
59 | ||
5e1c5ff4 TL |
60 | /* These routines should handle the standard chip-specific modes |
61 | * for usb0/1/2 ports, covering basic mux and transceiver setup. | |
62 | * | |
63 | * Some board-*.c files will need to set up additional mux options, | |
64 | * like for suspend handling, vbus sensing, GPIOs, and the D+ pullup. | |
65 | */ | |
66 | ||
67 | /* TESTED ON: | |
68 | * - 1611B H2 (with usb1 mini-AB) using standard Mini-B or OTG cables | |
69 | * - 5912 OSK OHCI (with usb0 standard-A), standard A-to-B cables | |
70 | * - 5912 OSK UDC, with *nonstandard* A-to-A cable | |
71 | * - 1510 Innovator UDC with bundled usb0 cable | |
72 | * - 1510 Innovator OHCI with bundled usb1/usb2 cable | |
73 | * - 1510 Innovator OHCI with custom usb0 cable, feeding 5V VBUS | |
74 | * - 1710 custom development board using alternate pin group | |
75 | * - 1710 H3 (with usb1 mini-AB) using standard Mini-B or OTG cables | |
76 | */ | |
77 | ||
78 | /*-------------------------------------------------------------------------*/ | |
79 | ||
69d88a00 | 80 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_USB_MUSB_OTG) |
5e1c5ff4 TL |
81 | |
82 | static struct otg_transceiver *xceiv; | |
83 | ||
84 | /** | |
85 | * otg_get_transceiver - find the (single) OTG transceiver driver | |
86 | * | |
87 | * Returns the transceiver driver, after getting a refcount to it; or | |
88 | * null if there is no such transceiver. The caller is responsible for | |
89 | * releasing that count. | |
90 | */ | |
91 | struct otg_transceiver *otg_get_transceiver(void) | |
92 | { | |
93 | if (xceiv) | |
94 | get_device(xceiv->dev); | |
95 | return xceiv; | |
96 | } | |
97 | EXPORT_SYMBOL(otg_get_transceiver); | |
98 | ||
99 | int otg_set_transceiver(struct otg_transceiver *x) | |
100 | { | |
101 | if (xceiv && x) | |
102 | return -EBUSY; | |
103 | xceiv = x; | |
104 | return 0; | |
105 | } | |
106 | EXPORT_SYMBOL(otg_set_transceiver); | |
107 | ||
108 | #endif | |
109 | ||
110 | /*-------------------------------------------------------------------------*/ | |
111 | ||
1a8bfa1e TL |
112 | #if defined(CONFIG_ARCH_OMAP_OTG) || defined(CONFIG_ARCH_OMAP15XX) |
113 | ||
69d88a00 PW |
114 | static void omap2_usb_devconf_clear(u8 port, u32 mask) |
115 | { | |
116 | u32 r; | |
117 | ||
118 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
119 | r &= ~USBTXWRMODEI(port, mask); | |
120 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | |
121 | } | |
122 | ||
123 | static void omap2_usb_devconf_set(u8 port, u32 mask) | |
124 | { | |
125 | u32 r; | |
126 | ||
127 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
128 | r |= USBTXWRMODEI(port, mask); | |
129 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | |
130 | } | |
131 | ||
132 | static void omap2_usb2_disable_5pinbitll(void) | |
133 | { | |
134 | u32 r; | |
135 | ||
136 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
137 | r &= ~(USBTXWRMODEI(2, USB_BIDIR_TLL) | USBT2TLL5PI); | |
138 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | |
139 | } | |
140 | ||
141 | static void omap2_usb2_enable_5pinunitll(void) | |
142 | { | |
143 | u32 r; | |
144 | ||
145 | r = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); | |
146 | r |= USBTXWRMODEI(2, USB_UNIDIR_TLL) | USBT2TLL5PI; | |
147 | omap_ctrl_writel(r, OMAP2_CONTROL_DEVCONF0); | |
148 | } | |
149 | ||
5e1c5ff4 TL |
150 | static u32 __init omap_usb0_init(unsigned nwires, unsigned is_device) |
151 | { | |
152 | u32 syscon1 = 0; | |
153 | ||
c40fae95 | 154 | if (cpu_is_omap24xx()) |
69d88a00 | 155 | omap2_usb_devconf_clear(0, USB_BIDIR_TLL); |
c40fae95 | 156 | |
5e1c5ff4 | 157 | if (nwires == 0) { |
c40fae95 | 158 | if (cpu_class_is_omap1() && !cpu_is_omap15xx()) { |
f35ae634 TL |
159 | u32 l; |
160 | ||
5e1c5ff4 | 161 | /* pulldown D+/D- */ |
f35ae634 TL |
162 | l = omap_readl(USB_TRANSCEIVER_CTRL); |
163 | l &= ~(3 << 1); | |
164 | omap_writel(l, USB_TRANSCEIVER_CTRL); | |
5e1c5ff4 TL |
165 | } |
166 | return 0; | |
167 | } | |
168 | ||
c40fae95 TL |
169 | if (is_device) { |
170 | if (cpu_is_omap24xx()) | |
171 | omap_cfg_reg(J20_24XX_USB0_PUEN); | |
172 | else | |
173 | omap_cfg_reg(W4_USB_PUEN); | |
174 | } | |
5e1c5ff4 | 175 | |
c40fae95 TL |
176 | /* internal transceiver (unavailable on 17xx, 24xx) */ |
177 | if (!cpu_class_is_omap2() && nwires == 2) { | |
f35ae634 TL |
178 | u32 l; |
179 | ||
5e1c5ff4 TL |
180 | // omap_cfg_reg(P9_USB_DP); |
181 | // omap_cfg_reg(R8_USB_DM); | |
182 | ||
183 | if (cpu_is_omap15xx()) { | |
184 | /* This works on 1510-Innovator */ | |
185 | return 0; | |
186 | } | |
187 | ||
188 | /* NOTES: | |
189 | * - peripheral should configure VBUS detection! | |
190 | * - only peripherals may use the internal D+/D- pulldowns | |
191 | * - OTG support on this port not yet written | |
192 | */ | |
193 | ||
f35ae634 TL |
194 | l = omap_readl(USB_TRANSCEIVER_CTRL); |
195 | l &= ~(7 << 4); | |
5e1c5ff4 | 196 | if (!is_device) |
f35ae634 TL |
197 | l |= (3 << 1); |
198 | omap_writel(l, USB_TRANSCEIVER_CTRL); | |
5e1c5ff4 TL |
199 | |
200 | return 3 << 16; | |
201 | } | |
202 | ||
203 | /* alternate pin config, external transceiver */ | |
204 | if (cpu_is_omap15xx()) { | |
205 | printk(KERN_ERR "no usb0 alt pin config on 15xx\n"); | |
206 | return 0; | |
207 | } | |
208 | ||
c40fae95 TL |
209 | if (cpu_is_omap24xx()) { |
210 | omap_cfg_reg(K18_24XX_USB0_DAT); | |
211 | omap_cfg_reg(K19_24XX_USB0_TXEN); | |
212 | omap_cfg_reg(J14_24XX_USB0_SE0); | |
213 | if (nwires != 3) | |
214 | omap_cfg_reg(J18_24XX_USB0_RCV); | |
215 | } else { | |
216 | omap_cfg_reg(V6_USB0_TXD); | |
217 | omap_cfg_reg(W9_USB0_TXEN); | |
218 | omap_cfg_reg(W5_USB0_SE0); | |
219 | if (nwires != 3) | |
220 | omap_cfg_reg(Y5_USB0_RCV); | |
221 | } | |
5e1c5ff4 | 222 | |
c40fae95 TL |
223 | /* NOTE: SPEED and SUSP aren't configured here. OTG hosts |
224 | * may be able to use I2C requests to set those bits along | |
6cbdc8c5 | 225 | * with VBUS switching and overcurrent detection. |
c40fae95 | 226 | */ |
5e1c5ff4 | 227 | |
f35ae634 TL |
228 | if (cpu_class_is_omap1() && nwires != 6) { |
229 | u32 l; | |
230 | ||
231 | l = omap_readl(USB_TRANSCEIVER_CTRL); | |
232 | l &= ~CONF_USB2_UNI_R; | |
233 | omap_writel(l, USB_TRANSCEIVER_CTRL); | |
234 | } | |
5e1c5ff4 TL |
235 | |
236 | switch (nwires) { | |
237 | case 3: | |
238 | syscon1 = 2; | |
c40fae95 | 239 | if (cpu_is_omap24xx()) |
69d88a00 | 240 | omap2_usb_devconf_set(0, USB_BIDIR); |
5e1c5ff4 TL |
241 | break; |
242 | case 4: | |
243 | syscon1 = 1; | |
c40fae95 | 244 | if (cpu_is_omap24xx()) |
69d88a00 | 245 | omap2_usb_devconf_set(0, USB_BIDIR); |
5e1c5ff4 TL |
246 | break; |
247 | case 6: | |
248 | syscon1 = 3; | |
c40fae95 TL |
249 | if (cpu_is_omap24xx()) { |
250 | omap_cfg_reg(J19_24XX_USB0_VP); | |
251 | omap_cfg_reg(K20_24XX_USB0_VM); | |
69d88a00 | 252 | omap2_usb_devconf_set(0, USB_UNIDIR); |
c40fae95 | 253 | } else { |
f35ae634 TL |
254 | u32 l; |
255 | ||
c40fae95 TL |
256 | omap_cfg_reg(AA9_USB0_VP); |
257 | omap_cfg_reg(R9_USB0_VM); | |
f35ae634 TL |
258 | l = omap_readl(USB_TRANSCEIVER_CTRL); |
259 | l |= CONF_USB2_UNI_R; | |
260 | omap_writel(l, USB_TRANSCEIVER_CTRL); | |
c40fae95 | 261 | } |
5e1c5ff4 TL |
262 | break; |
263 | default: | |
264 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", | |
265 | 0, nwires); | |
266 | } | |
267 | return syscon1 << 16; | |
268 | } | |
269 | ||
270 | static u32 __init omap_usb1_init(unsigned nwires) | |
271 | { | |
272 | u32 syscon1 = 0; | |
273 | ||
f35ae634 TL |
274 | if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) { |
275 | u32 l; | |
276 | ||
277 | l = omap_readl(USB_TRANSCEIVER_CTRL); | |
278 | l &= ~CONF_USB1_UNI_R; | |
279 | omap_writel(l, USB_TRANSCEIVER_CTRL); | |
280 | } | |
c40fae95 | 281 | if (cpu_is_omap24xx()) |
69d88a00 | 282 | omap2_usb_devconf_clear(1, USB_BIDIR_TLL); |
c40fae95 | 283 | |
5e1c5ff4 TL |
284 | if (nwires == 0) |
285 | return 0; | |
286 | ||
287 | /* external transceiver */ | |
c40fae95 TL |
288 | if (cpu_class_is_omap1()) { |
289 | omap_cfg_reg(USB1_TXD); | |
290 | omap_cfg_reg(USB1_TXEN); | |
291 | if (nwires != 3) | |
292 | omap_cfg_reg(USB1_RCV); | |
293 | } | |
294 | ||
5e1c5ff4 TL |
295 | if (cpu_is_omap15xx()) { |
296 | omap_cfg_reg(USB1_SEO); | |
297 | omap_cfg_reg(USB1_SPEED); | |
298 | // SUSP | |
299 | } else if (cpu_is_omap1610() || cpu_is_omap5912()) { | |
300 | omap_cfg_reg(W13_1610_USB1_SE0); | |
301 | omap_cfg_reg(R13_1610_USB1_SPEED); | |
302 | // SUSP | |
303 | } else if (cpu_is_omap1710()) { | |
304 | omap_cfg_reg(R13_1710_USB1_SE0); | |
305 | // SUSP | |
c40fae95 TL |
306 | } else if (cpu_is_omap24xx()) { |
307 | /* NOTE: board-specific code must set up pin muxing for usb1, | |
308 | * since each signal could come out on either of two balls. | |
309 | */ | |
5e1c5ff4 | 310 | } else { |
c40fae95 TL |
311 | pr_debug("usb%d cpu unrecognized\n", 1); |
312 | return 0; | |
5e1c5ff4 | 313 | } |
5e1c5ff4 TL |
314 | |
315 | switch (nwires) { | |
c40fae95 TL |
316 | case 2: |
317 | if (!cpu_is_omap24xx()) | |
318 | goto bad; | |
319 | /* NOTE: board-specific code must override this setting if | |
320 | * this TLL link is not using DP/DM | |
321 | */ | |
322 | syscon1 = 1; | |
69d88a00 | 323 | omap2_usb_devconf_set(1, USB_BIDIR_TLL); |
c40fae95 | 324 | break; |
5e1c5ff4 TL |
325 | case 3: |
326 | syscon1 = 2; | |
c40fae95 | 327 | if (cpu_is_omap24xx()) |
69d88a00 | 328 | omap2_usb_devconf_set(1, USB_BIDIR); |
5e1c5ff4 TL |
329 | break; |
330 | case 4: | |
331 | syscon1 = 1; | |
c40fae95 | 332 | if (cpu_is_omap24xx()) |
69d88a00 | 333 | omap2_usb_devconf_set(1, USB_BIDIR); |
5e1c5ff4 TL |
334 | break; |
335 | case 6: | |
c40fae95 TL |
336 | if (cpu_is_omap24xx()) |
337 | goto bad; | |
5e1c5ff4 TL |
338 | syscon1 = 3; |
339 | omap_cfg_reg(USB1_VP); | |
340 | omap_cfg_reg(USB1_VM); | |
f35ae634 TL |
341 | if (!cpu_is_omap15xx()) { |
342 | u32 l; | |
343 | ||
344 | l = omap_readl(USB_TRANSCEIVER_CTRL); | |
345 | l |= CONF_USB1_UNI_R; | |
346 | omap_writel(l, USB_TRANSCEIVER_CTRL); | |
347 | } | |
5e1c5ff4 TL |
348 | break; |
349 | default: | |
c40fae95 | 350 | bad: |
5e1c5ff4 TL |
351 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", |
352 | 1, nwires); | |
353 | } | |
354 | return syscon1 << 20; | |
355 | } | |
356 | ||
357 | static u32 __init omap_usb2_init(unsigned nwires, unsigned alt_pingroup) | |
358 | { | |
359 | u32 syscon1 = 0; | |
360 | ||
c40fae95 | 361 | if (cpu_is_omap24xx()) { |
69d88a00 | 362 | omap2_usb2_disable_5pinbitll(); |
c40fae95 TL |
363 | alt_pingroup = 0; |
364 | } | |
365 | ||
366 | /* NOTE omap1 erratum: must leave USB2_UNI_R set if usb0 in use */ | |
5e1c5ff4 TL |
367 | if (alt_pingroup || nwires == 0) |
368 | return 0; | |
c40fae95 | 369 | |
f35ae634 TL |
370 | if (cpu_class_is_omap1() && !cpu_is_omap15xx() && nwires != 6) { |
371 | u32 l; | |
372 | ||
373 | l = omap_readl(USB_TRANSCEIVER_CTRL); | |
374 | l &= ~CONF_USB2_UNI_R; | |
375 | omap_writel(l, USB_TRANSCEIVER_CTRL); | |
376 | } | |
5e1c5ff4 TL |
377 | |
378 | /* external transceiver */ | |
379 | if (cpu_is_omap15xx()) { | |
380 | omap_cfg_reg(USB2_TXD); | |
381 | omap_cfg_reg(USB2_TXEN); | |
382 | omap_cfg_reg(USB2_SEO); | |
383 | if (nwires != 3) | |
384 | omap_cfg_reg(USB2_RCV); | |
385 | /* there is no USB2_SPEED */ | |
386 | } else if (cpu_is_omap16xx()) { | |
387 | omap_cfg_reg(V6_USB2_TXD); | |
388 | omap_cfg_reg(W9_USB2_TXEN); | |
389 | omap_cfg_reg(W5_USB2_SE0); | |
390 | if (nwires != 3) | |
391 | omap_cfg_reg(Y5_USB2_RCV); | |
392 | // FIXME omap_cfg_reg(USB2_SPEED); | |
c40fae95 TL |
393 | } else if (cpu_is_omap24xx()) { |
394 | omap_cfg_reg(Y11_24XX_USB2_DAT); | |
395 | omap_cfg_reg(AA10_24XX_USB2_SE0); | |
396 | if (nwires > 2) | |
397 | omap_cfg_reg(AA12_24XX_USB2_TXEN); | |
398 | if (nwires > 3) | |
399 | omap_cfg_reg(AA6_24XX_USB2_RCV); | |
5e1c5ff4 | 400 | } else { |
c40fae95 TL |
401 | pr_debug("usb%d cpu unrecognized\n", 1); |
402 | return 0; | |
5e1c5ff4 | 403 | } |
c40fae95 | 404 | // if (cpu_class_is_omap1()) omap_cfg_reg(USB2_SUSP); |
5e1c5ff4 TL |
405 | |
406 | switch (nwires) { | |
c40fae95 TL |
407 | case 2: |
408 | if (!cpu_is_omap24xx()) | |
409 | goto bad; | |
410 | /* NOTE: board-specific code must override this setting if | |
411 | * this TLL link is not using DP/DM | |
412 | */ | |
413 | syscon1 = 1; | |
69d88a00 | 414 | omap2_usb_devconf_set(2, USB_BIDIR_TLL); |
c40fae95 | 415 | break; |
5e1c5ff4 TL |
416 | case 3: |
417 | syscon1 = 2; | |
c40fae95 | 418 | if (cpu_is_omap24xx()) |
69d88a00 | 419 | omap2_usb_devconf_set(2, USB_BIDIR); |
5e1c5ff4 TL |
420 | break; |
421 | case 4: | |
422 | syscon1 = 1; | |
c40fae95 | 423 | if (cpu_is_omap24xx()) |
69d88a00 | 424 | omap2_usb_devconf_set(2, USB_BIDIR); |
c40fae95 TL |
425 | break; |
426 | case 5: | |
427 | if (!cpu_is_omap24xx()) | |
428 | goto bad; | |
429 | omap_cfg_reg(AA4_24XX_USB2_TLLSE0); | |
430 | /* NOTE: board-specific code must override this setting if | |
431 | * this TLL link is not using DP/DM. Something must also | |
432 | * set up OTG_SYSCON2.HMC_TLL{ATTACH,SPEED} | |
433 | */ | |
434 | syscon1 = 3; | |
69d88a00 | 435 | omap2_usb2_enable_5pinunitll(); |
5e1c5ff4 TL |
436 | break; |
437 | case 6: | |
c40fae95 TL |
438 | if (cpu_is_omap24xx()) |
439 | goto bad; | |
5e1c5ff4 TL |
440 | syscon1 = 3; |
441 | if (cpu_is_omap15xx()) { | |
442 | omap_cfg_reg(USB2_VP); | |
443 | omap_cfg_reg(USB2_VM); | |
444 | } else { | |
f35ae634 TL |
445 | u32 l; |
446 | ||
5e1c5ff4 TL |
447 | omap_cfg_reg(AA9_USB2_VP); |
448 | omap_cfg_reg(R9_USB2_VM); | |
f35ae634 TL |
449 | l = omap_readl(USB_TRANSCEIVER_CTRL); |
450 | l |= CONF_USB2_UNI_R; | |
451 | omap_writel(l, USB_TRANSCEIVER_CTRL); | |
5e1c5ff4 TL |
452 | } |
453 | break; | |
454 | default: | |
c40fae95 | 455 | bad: |
5e1c5ff4 TL |
456 | printk(KERN_ERR "illegal usb%d %d-wire transceiver\n", |
457 | 2, nwires); | |
458 | } | |
459 | return syscon1 << 24; | |
460 | } | |
461 | ||
1a8bfa1e TL |
462 | #endif |
463 | ||
5e1c5ff4 TL |
464 | /*-------------------------------------------------------------------------*/ |
465 | ||
466 | #if defined(CONFIG_USB_GADGET_OMAP) || \ | |
467 | defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) || \ | |
468 | (defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG)) | |
469 | static void usb_release(struct device *dev) | |
470 | { | |
471 | /* normally not freed */ | |
472 | } | |
473 | #endif | |
474 | ||
475 | #ifdef CONFIG_USB_GADGET_OMAP | |
476 | ||
477 | static struct resource udc_resources[] = { | |
478 | /* order is significant! */ | |
479 | { /* registers */ | |
480 | .start = UDC_BASE, | |
481 | .end = UDC_BASE + 0xff, | |
482 | .flags = IORESOURCE_MEM, | |
483 | }, { /* general IRQ */ | |
c40fae95 | 484 | .start = INT_USB_IRQ_GEN, |
5e1c5ff4 TL |
485 | .flags = IORESOURCE_IRQ, |
486 | }, { /* PIO IRQ */ | |
c40fae95 | 487 | .start = INT_USB_IRQ_NISO, |
5e1c5ff4 TL |
488 | .flags = IORESOURCE_IRQ, |
489 | }, { /* SOF IRQ */ | |
c40fae95 | 490 | .start = INT_USB_IRQ_ISO, |
5e1c5ff4 TL |
491 | .flags = IORESOURCE_IRQ, |
492 | }, | |
493 | }; | |
494 | ||
495 | static u64 udc_dmamask = ~(u32)0; | |
496 | ||
497 | static struct platform_device udc_device = { | |
498 | .name = "omap_udc", | |
499 | .id = -1, | |
500 | .dev = { | |
501 | .release = usb_release, | |
502 | .dma_mask = &udc_dmamask, | |
503 | .coherent_dma_mask = 0xffffffff, | |
504 | }, | |
505 | .num_resources = ARRAY_SIZE(udc_resources), | |
506 | .resource = udc_resources, | |
507 | }; | |
508 | ||
509 | #endif | |
510 | ||
511 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | |
512 | ||
513 | /* The dmamask must be set for OHCI to work */ | |
514 | static u64 ohci_dmamask = ~(u32)0; | |
515 | ||
516 | static struct resource ohci_resources[] = { | |
517 | { | |
518 | .start = OMAP_OHCI_BASE, | |
c40fae95 | 519 | .end = OMAP_OHCI_BASE + 0xff, |
5e1c5ff4 TL |
520 | .flags = IORESOURCE_MEM, |
521 | }, | |
522 | { | |
c40fae95 | 523 | .start = INT_USB_IRQ_HGEN, |
5e1c5ff4 TL |
524 | .flags = IORESOURCE_IRQ, |
525 | }, | |
526 | }; | |
527 | ||
528 | static struct platform_device ohci_device = { | |
529 | .name = "ohci", | |
530 | .id = -1, | |
531 | .dev = { | |
532 | .release = usb_release, | |
533 | .dma_mask = &ohci_dmamask, | |
534 | .coherent_dma_mask = 0xffffffff, | |
535 | }, | |
536 | .num_resources = ARRAY_SIZE(ohci_resources), | |
537 | .resource = ohci_resources, | |
538 | }; | |
539 | ||
540 | #endif | |
541 | ||
542 | #if defined(CONFIG_USB_OTG) && defined(CONFIG_ARCH_OMAP_OTG) | |
543 | ||
544 | static struct resource otg_resources[] = { | |
545 | /* order is significant! */ | |
546 | { | |
547 | .start = OTG_BASE, | |
548 | .end = OTG_BASE + 0xff, | |
549 | .flags = IORESOURCE_MEM, | |
550 | }, { | |
c40fae95 | 551 | .start = INT_USB_IRQ_OTG, |
5e1c5ff4 TL |
552 | .flags = IORESOURCE_IRQ, |
553 | }, | |
554 | }; | |
555 | ||
556 | static struct platform_device otg_device = { | |
557 | .name = "omap_otg", | |
558 | .id = -1, | |
559 | .dev = { | |
560 | .release = usb_release, | |
561 | }, | |
562 | .num_resources = ARRAY_SIZE(otg_resources), | |
563 | .resource = otg_resources, | |
564 | }; | |
565 | ||
566 | #endif | |
567 | ||
568 | /*-------------------------------------------------------------------------*/ | |
569 | ||
5e1c5ff4 | 570 | // FIXME correct answer depends on hmc_mode, |
c40fae95 | 571 | // as does (on omap1) any nonzero value for config->otg port number |
5e1c5ff4 TL |
572 | #ifdef CONFIG_USB_GADGET_OMAP |
573 | #define is_usb0_device(config) 1 | |
574 | #else | |
575 | #define is_usb0_device(config) 0 | |
576 | #endif | |
577 | ||
578 | /*-------------------------------------------------------------------------*/ | |
579 | ||
580 | #ifdef CONFIG_ARCH_OMAP_OTG | |
581 | ||
582 | void __init | |
583 | omap_otg_init(struct omap_usb_config *config) | |
584 | { | |
f35ae634 | 585 | u32 syscon; |
5e1c5ff4 TL |
586 | int status; |
587 | int alt_pingroup = 0; | |
588 | ||
589 | /* NOTE: no bus or clock setup (yet?) */ | |
590 | ||
f35ae634 | 591 | syscon = omap_readl(OTG_SYSCON_1) & 0xffff; |
5e1c5ff4 TL |
592 | if (!(syscon & OTG_RESET_DONE)) |
593 | pr_debug("USB resets not complete?\n"); | |
594 | ||
f35ae634 | 595 | //omap_writew(0, OTG_IRQ_EN); |
5e1c5ff4 TL |
596 | |
597 | /* pin muxing and transceiver pinouts */ | |
598 | if (config->pins[0] > 2) /* alt pingroup 2 */ | |
599 | alt_pingroup = 1; | |
600 | syscon |= omap_usb0_init(config->pins[0], is_usb0_device(config)); | |
601 | syscon |= omap_usb1_init(config->pins[1]); | |
602 | syscon |= omap_usb2_init(config->pins[2], alt_pingroup); | |
f35ae634 TL |
603 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); |
604 | omap_writel(syscon, OTG_SYSCON_1); | |
5e1c5ff4 TL |
605 | |
606 | syscon = config->hmc_mode; | |
607 | syscon |= USBX_SYNCHRO | (4 << 16) /* B_ASE0_BRST */; | |
608 | #ifdef CONFIG_USB_OTG | |
609 | if (config->otg) | |
610 | syscon |= OTG_EN; | |
611 | #endif | |
c40fae95 | 612 | if (cpu_class_is_omap1()) |
f35ae634 TL |
613 | pr_debug("USB_TRANSCEIVER_CTRL = %03x\n", |
614 | omap_readl(USB_TRANSCEIVER_CTRL)); | |
615 | pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2)); | |
616 | omap_writel(syscon, OTG_SYSCON_2); | |
5e1c5ff4 TL |
617 | |
618 | printk("USB: hmc %d", config->hmc_mode); | |
c40fae95 | 619 | if (!alt_pingroup) |
5e1c5ff4 TL |
620 | printk(", usb2 alt %d wires", config->pins[2]); |
621 | else if (config->pins[0]) | |
622 | printk(", usb0 %d wires%s", config->pins[0], | |
623 | is_usb0_device(config) ? " (dev)" : ""); | |
624 | if (config->pins[1]) | |
625 | printk(", usb1 %d wires", config->pins[1]); | |
626 | if (!alt_pingroup && config->pins[2]) | |
627 | printk(", usb2 %d wires", config->pins[2]); | |
628 | if (config->otg) | |
629 | printk(", Mini-AB on usb%d", config->otg - 1); | |
630 | printk("\n"); | |
631 | ||
c40fae95 | 632 | if (cpu_class_is_omap1()) { |
f35ae634 TL |
633 | u16 w; |
634 | ||
c40fae95 | 635 | /* leave USB clocks/controllers off until needed */ |
f35ae634 TL |
636 | w = omap_readw(ULPD_SOFT_REQ); |
637 | w &= ~SOFT_USB_CLK_REQ; | |
638 | omap_writew(w, ULPD_SOFT_REQ); | |
639 | ||
640 | w = omap_readw(ULPD_CLOCK_CTRL); | |
641 | w &= ~USB_MCLK_EN; | |
642 | w |= DIS_USB_PVCI_CLK; | |
643 | omap_writew(w, ULPD_CLOCK_CTRL); | |
c40fae95 | 644 | } |
f35ae634 | 645 | syscon = omap_readl(OTG_SYSCON_1); |
5e1c5ff4 TL |
646 | syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN; |
647 | ||
648 | #ifdef CONFIG_USB_GADGET_OMAP | |
649 | if (config->otg || config->register_dev) { | |
650 | syscon &= ~DEV_IDLE_EN; | |
651 | udc_device.dev.platform_data = config; | |
652 | /* FIXME patch IRQ numbers for omap730 */ | |
653 | status = platform_device_register(&udc_device); | |
654 | if (status) | |
655 | pr_debug("can't register UDC device, %d\n", status); | |
656 | } | |
657 | #endif | |
658 | ||
659 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | |
660 | if (config->otg || config->register_host) { | |
661 | syscon &= ~HST_IDLE_EN; | |
662 | ohci_device.dev.platform_data = config; | |
663 | if (cpu_is_omap730()) | |
664 | ohci_resources[1].start = INT_730_USB_HHC_1; | |
665 | status = platform_device_register(&ohci_device); | |
666 | if (status) | |
667 | pr_debug("can't register OHCI device, %d\n", status); | |
668 | } | |
669 | #endif | |
670 | ||
671 | #ifdef CONFIG_USB_OTG | |
672 | if (config->otg) { | |
673 | syscon &= ~OTG_IDLE_EN; | |
674 | otg_device.dev.platform_data = config; | |
675 | if (cpu_is_omap730()) | |
676 | otg_resources[1].start = INT_730_USB_OTG; | |
677 | status = platform_device_register(&otg_device); | |
678 | if (status) | |
679 | pr_debug("can't register OTG device, %d\n", status); | |
680 | } | |
681 | #endif | |
f35ae634 TL |
682 | pr_debug("OTG_SYSCON_1 = %08x\n", omap_readl(OTG_SYSCON_1)); |
683 | omap_writel(syscon, OTG_SYSCON_1); | |
5e1c5ff4 TL |
684 | |
685 | status = 0; | |
686 | } | |
687 | ||
688 | #else | |
689 | static inline void omap_otg_init(struct omap_usb_config *config) {} | |
690 | #endif | |
691 | ||
692 | /*-------------------------------------------------------------------------*/ | |
693 | ||
1a8bfa1e | 694 | #ifdef CONFIG_ARCH_OMAP15XX |
5e1c5ff4 | 695 | |
f35ae634 | 696 | /* ULPD_DPLL_CTRL */ |
5e1c5ff4 TL |
697 | #define DPLL_IOB (1 << 13) |
698 | #define DPLL_PLL_ENABLE (1 << 4) | |
699 | #define DPLL_LOCK (1 << 0) | |
700 | ||
f35ae634 | 701 | /* ULPD_APLL_CTRL */ |
5e1c5ff4 TL |
702 | #define APLL_NDPLL_SWITCH (1 << 0) |
703 | ||
704 | ||
705 | static void __init omap_1510_usb_init(struct omap_usb_config *config) | |
706 | { | |
5e1c5ff4 | 707 | unsigned int val; |
f35ae634 | 708 | u16 w; |
5e1c5ff4 TL |
709 | |
710 | omap_usb0_init(config->pins[0], is_usb0_device(config)); | |
711 | omap_usb1_init(config->pins[1]); | |
712 | omap_usb2_init(config->pins[2], 0); | |
713 | ||
714 | val = omap_readl(MOD_CONF_CTRL_0) & ~(0x3f << 1); | |
715 | val |= (config->hmc_mode << 1); | |
716 | omap_writel(val, MOD_CONF_CTRL_0); | |
717 | ||
718 | printk("USB: hmc %d", config->hmc_mode); | |
719 | if (config->pins[0]) | |
720 | printk(", usb0 %d wires%s", config->pins[0], | |
721 | is_usb0_device(config) ? " (dev)" : ""); | |
722 | if (config->pins[1]) | |
723 | printk(", usb1 %d wires", config->pins[1]); | |
724 | if (config->pins[2]) | |
725 | printk(", usb2 %d wires", config->pins[2]); | |
726 | printk("\n"); | |
727 | ||
728 | /* use DPLL for 48 MHz function clock */ | |
f35ae634 TL |
729 | pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL), |
730 | omap_readw(ULPD_DPLL_CTRL), omap_readw(ULPD_SOFT_REQ)); | |
731 | ||
732 | w = omap_readw(ULPD_APLL_CTRL); | |
733 | w &= ~APLL_NDPLL_SWITCH; | |
734 | omap_writew(w, ULPD_APLL_CTRL); | |
735 | ||
736 | w = omap_readw(ULPD_DPLL_CTRL); | |
737 | w |= DPLL_IOB | DPLL_PLL_ENABLE; | |
738 | omap_writew(w, ULPD_DPLL_CTRL); | |
739 | ||
740 | w = omap_readw(ULPD_SOFT_REQ); | |
741 | w |= SOFT_UDC_REQ | SOFT_DPLL_REQ; | |
742 | omap_writew(w, ULPD_SOFT_REQ); | |
743 | ||
744 | while (!(omap_readw(ULPD_DPLL_CTRL) & DPLL_LOCK)) | |
5e1c5ff4 TL |
745 | cpu_relax(); |
746 | ||
747 | #ifdef CONFIG_USB_GADGET_OMAP | |
748 | if (config->register_dev) { | |
1a8bfa1e TL |
749 | int status; |
750 | ||
5e1c5ff4 TL |
751 | udc_device.dev.platform_data = config; |
752 | status = platform_device_register(&udc_device); | |
753 | if (status) | |
754 | pr_debug("can't register UDC device, %d\n", status); | |
755 | /* udc driver gates 48MHz by D+ pullup */ | |
756 | } | |
757 | #endif | |
758 | ||
759 | #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) | |
760 | if (config->register_host) { | |
1a8bfa1e TL |
761 | int status; |
762 | ||
5e1c5ff4 TL |
763 | ohci_device.dev.platform_data = config; |
764 | status = platform_device_register(&ohci_device); | |
765 | if (status) | |
766 | pr_debug("can't register OHCI device, %d\n", status); | |
767 | /* hcd explicitly gates 48MHz */ | |
768 | } | |
769 | #endif | |
770 | } | |
771 | ||
772 | #else | |
773 | static inline void omap_1510_usb_init(struct omap_usb_config *config) {} | |
774 | #endif | |
775 | ||
776 | /*-------------------------------------------------------------------------*/ | |
777 | ||
778 | static struct omap_usb_config platform_data; | |
779 | ||
780 | static int __init | |
781 | omap_usb_init(void) | |
782 | { | |
783 | const struct omap_usb_config *config; | |
784 | ||
785 | config = omap_get_config(OMAP_TAG_USB, struct omap_usb_config); | |
786 | if (config == NULL) { | |
787 | printk(KERN_ERR "USB: No board-specific " | |
788 | "platform config found\n"); | |
789 | return -ENODEV; | |
790 | } | |
791 | platform_data = *config; | |
792 | ||
c40fae95 | 793 | if (cpu_is_omap730() || cpu_is_omap16xx() || cpu_is_omap24xx()) |
5e1c5ff4 TL |
794 | omap_otg_init(&platform_data); |
795 | else if (cpu_is_omap15xx()) | |
796 | omap_1510_usb_init(&platform_data); | |
797 | else { | |
798 | printk(KERN_ERR "USB: No init for your chip yet\n"); | |
799 | return -ENODEV; | |
800 | } | |
801 | return 0; | |
802 | } | |
803 | ||
804 | subsys_initcall(omap_usb_init); |