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Merge tag 'io_uring-5.7-2020-05-22' of git://git.kernel.dk/linux-block
[thirdparty/linux.git] / arch / arm64 / boot / dts / freescale / imx8mm.dtsi
CommitLineData
a05ea40e
JB		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2019 NXP
4 */
5
6#include <dt-bindings/clock/imx8mm-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/thermal/thermal.h>
11
12#include "imx8mm-pinfunc.h"
13
14/ {
a05ea40e
JB		 15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 aliases {
20 ethernet0 = &fec1;
21 i2c0 = &i2c1;
22 i2c1 = &i2c2;
23 i2c2 = &i2c3;
24 i2c3 = &i2c4;
25 serial0 = &uart1;
26 serial1 = &uart2;
27 serial2 = &uart3;
28 serial3 = &uart4;
29 spi0 = &ecspi1;
30 spi1 = &ecspi2;
31 spi2 = &ecspi3;
32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3;
35 gpio0 = &gpio1;
36 gpio1 = &gpio2;
37 gpio2 = &gpio3;
38 gpio3 = &gpio4;
39 gpio4 = &gpio5;
40 };
41
42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
a1406b72
AH		 46 idle-states {
47 entry-method = "psci";
48
49 cpu_pd_wait: cpu-pd-wait {
50 compatible = "arm,idle-state";
51 arm,psci-suspend-param = <0x0010033>;
52 local-timer-stop;
53 entry-latency-us = <1000>;
54 exit-latency-us = <700>;
55 min-residency-us = <2700>;
56 };
57 };
58
a05ea40e
JB		 59 A53_0: cpu@0 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a53";
62 reg = <0x0>;
e85c9d0f
LC		 63 clock-latency = <61036>; /* two CLK32 periods */
64 clocks = <&clk IMX8MM_CLK_ARM>;
a05ea40e
JB		 65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
e85c9d0f 67 operating-points-v2 = <&a53_opp_table>;
f403a26c
LC		 68 nvmem-cells = <&cpu_speed_grade>;
69 nvmem-cell-names = "speed_grade";
a1406b72 70 cpu-idle-states = <&cpu_pd_wait>;
11699fd5 71 #cooling-cells = <2>;
a05ea40e
JB		 72 };
73
74 A53_1: cpu@1 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a53";
77 reg = <0x1>;
e85c9d0f
LC		 78 clock-latency = <61036>; /* two CLK32 periods */
79 clocks = <&clk IMX8MM_CLK_ARM>;
a05ea40e
JB		 80 enable-method = "psci";
81 next-level-cache = <&A53_L2>;
e85c9d0f 82 operating-points-v2 = <&a53_opp_table>;
a1406b72 83 cpu-idle-states = <&cpu_pd_wait>;
11699fd5 84 #cooling-cells = <2>;
a05ea40e
JB		 85 };
86
87 A53_2: cpu@2 {
88 device_type = "cpu";
89 compatible = "arm,cortex-a53";
90 reg = <0x2>;
e85c9d0f
LC		 91 clock-latency = <61036>; /* two CLK32 periods */
92 clocks = <&clk IMX8MM_CLK_ARM>;
a05ea40e
JB		 93 enable-method = "psci";
94 next-level-cache = <&A53_L2>;
e85c9d0f 95 operating-points-v2 = <&a53_opp_table>;
a1406b72 96 cpu-idle-states = <&cpu_pd_wait>;
11699fd5 97 #cooling-cells = <2>;
a05ea40e
JB		 98 };
99
100 A53_3: cpu@3 {
101 device_type = "cpu";
102 compatible = "arm,cortex-a53";
103 reg = <0x3>;
e85c9d0f
LC		 104 clock-latency = <61036>; /* two CLK32 periods */
105 clocks = <&clk IMX8MM_CLK_ARM>;
a05ea40e
JB		 106 enable-method = "psci";
107 next-level-cache = <&A53_L2>;
e85c9d0f 108 operating-points-v2 = <&a53_opp_table>;
a1406b72 109 cpu-idle-states = <&cpu_pd_wait>;
11699fd5 110 #cooling-cells = <2>;
a05ea40e
JB		 111 };
112
113 A53_L2: l2-cache0 {
114 compatible = "cache";
115 };
116 };
117
e85c9d0f
LC		 118 a53_opp_table: opp-table {
119 compatible = "operating-points-v2";
120 opp-shared;
121
122 opp-1200000000 {
123 opp-hz = /bits/ 64 <1200000000>;
124 opp-microvolt = <850000>;
f403a26c 125 opp-supported-hw = <0xe>, <0x7>;
e85c9d0f 126 clock-latency-ns = <150000>;
0d9df581 127 opp-suspend;
e85c9d0f
LC		 128 };
129
130 opp-1600000000 {
131 opp-hz = /bits/ 64 <1600000000>;
132 opp-microvolt = <900000>;
f403a26c
LC		 133 opp-supported-hw = <0xc>, <0x7>;
134 clock-latency-ns = <150000>;
0d9df581 135 opp-suspend;
f403a26c
LC		 136 };
137
138 opp-1800000000 {
139 opp-hz = /bits/ 64 <1800000000>;
140 opp-microvolt = <1000000>;
cd7c2ddf 141 opp-supported-hw = <0x8>, <0x3>;
e85c9d0f 142 clock-latency-ns = <150000>;
0d9df581 143 opp-suspend;
e85c9d0f
LC		 144 };
145 };
146
a05ea40e
JB		 147 osc_32k: clock-osc-32k {
148 compatible = "fixed-clock";
149 #clock-cells = <0>;
150 clock-frequency = <32768>;
151 clock-output-names = "osc_32k";
152 };
153
154 osc_24m: clock-osc-24m {
155 compatible = "fixed-clock";
156 #clock-cells = <0>;
157 clock-frequency = <24000000>;
158 clock-output-names = "osc_24m";
159 };
160
161 clk_ext1: clock-ext1 {
162 compatible = "fixed-clock";
163 #clock-cells = <0>;
164 clock-frequency = <133000000>;
165 clock-output-names = "clk_ext1";
166 };
167
168 clk_ext2: clock-ext2 {
169 compatible = "fixed-clock";
170 #clock-cells = <0>;
171 clock-frequency = <133000000>;
172 clock-output-names = "clk_ext2";
173 };
174
175 clk_ext3: clock-ext3 {
176 compatible = "fixed-clock";
177 #clock-cells = <0>;
178 clock-frequency = <133000000>;
179 clock-output-names = "clk_ext3";
180 };
181
182 clk_ext4: clock-ext4 {
183 compatible = "fixed-clock";
184 #clock-cells = <0>;
185 clock-frequency= <133000000>;
186 clock-output-names = "clk_ext4";
187 };
188
a05ea40e
JB		 189 psci {
190 compatible = "arm,psci-1.0";
191 method = "smc";
192 };
193
194 pmu {
195 compatible = "arm,armv8-pmuv3";
196 interrupts = <GIC_PPI 7
197 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
198 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
199 };
200
201 timer {
202 compatible = "arm,armv8-timer";
203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
204 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
205 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
206 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
207 clock-frequency = <8000000>;
208 arm,no-tick-in-suspend;
209 };
210
11699fd5
AH		 211 thermal-zones {
212 cpu-thermal {
213 polling-delay-passive = <250>;
214 polling-delay = <2000>;
215 thermal-sensors = <&tmu>;
216 trips {
217 cpu_alert0: trip0 {
218 temperature = <85000>;
219 hysteresis = <2000>;
220 type = "passive";
221 };
222
223 cpu_crit0: trip1 {
224 temperature = <95000>;
225 hysteresis = <2000>;
226 type = "critical";
227 };
228 };
229
230 cooling-maps {
231 map0 {
232 trip = <&cpu_alert0>;
233 cooling-device =
234 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
235 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
236 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
237 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
238 };
239 };
240 };
241 };
242
a656622a
FE		 243 usbphynop1: usbphynop1 {
244 compatible = "usb-nop-xceiv";
245 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
246 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
247 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
248 clock-names = "main_clk";
249 };
250
251 usbphynop2: usbphynop2 {
252 compatible = "usb-nop-xceiv";
253 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
254 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
255 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
256 clock-names = "main_clk";
257 };
258
951c1d37 259 soc@0 {
a05ea40e
JB		 260 compatible = "simple-bus";
261 #address-cells = <1>;
262 #size-cells = <1>;
263 ranges = <0x0 0x0 0x0 0x3e000000>;
264
265 aips1: bus@30000000 {
dc3efc6f 266 compatible = "fsl,aips-bus", "simple-bus";
921a6845 267 reg = <0x30000000 0x400000>;
a05ea40e
JB		 268 #address-cells = <1>;
269 #size-cells = <1>;
10c74207 270 ranges = <0x30000000 0x30000000 0x400000>;
a05ea40e 271
4bee4357
DB		 272 sai1: sai@30010000 {
273 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
274 reg = <0x30010000 0x10000>;
275 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
276 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
277 <&clk IMX8MM_CLK_SAI1_ROOT>,
278 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
279 clock-names = "bus", "mclk1", "mclk2", "mclk3";
280 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
281 dma-names = "rx", "tx";
282 status = "disabled";
283 };
284
285 sai2: sai@30020000 {
286 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
287 reg = <0x30020000 0x10000>;
288 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
290 <&clk IMX8MM_CLK_SAI2_ROOT>,
291 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
292 clock-names = "bus", "mclk1", "mclk2", "mclk3";
293 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
294 dma-names = "rx", "tx";
295 status = "disabled";
296 };
297
298 sai3: sai@30030000 {
299 #sound-dai-cells = <0>;
300 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
301 reg = <0x30030000 0x10000>;
302 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
304 <&clk IMX8MM_CLK_SAI3_ROOT>,
305 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
306 clock-names = "bus", "mclk1", "mclk2", "mclk3";
307 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
308 dma-names = "rx", "tx";
309 status = "disabled";
310 };
311
312 sai5: sai@30050000 {
313 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
314 reg = <0x30050000 0x10000>;
315 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
317 <&clk IMX8MM_CLK_SAI5_ROOT>,
318 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
319 clock-names = "bus", "mclk1", "mclk2", "mclk3";
320 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
321 dma-names = "rx", "tx";
322 status = "disabled";
323 };
324
325 sai6: sai@30060000 {
326 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
327 reg = <0x30060000 0x10000>;
328 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
329 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
330 <&clk IMX8MM_CLK_SAI6_ROOT>,
331 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
332 clock-names = "bus", "mclk1", "mclk2", "mclk3";
333 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
334 dma-names = "rx", "tx";
335 status = "disabled";
336 };
a05ea40e
JB		 337
338 gpio1: gpio@30200000 {
339 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
340 reg = <0x30200000 0x10000>;
341 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
09892aa1 343 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
a05ea40e
JB		 344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
347 #interrupt-cells = <2>;
15626359 348 gpio-ranges = <&iomuxc 0 10 30>;
a05ea40e
JB		 349 };
350
351 gpio2: gpio@30210000 {
352 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
353 reg = <0x30210000 0x10000>;
354 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
09892aa1 356 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
a05ea40e
JB		 357 gpio-controller;
358 #gpio-cells = <2>;
359 interrupt-controller;
360 #interrupt-cells = <2>;
15626359 361 gpio-ranges = <&iomuxc 0 40 21>;
a05ea40e
JB		 362 };
363
364 gpio3: gpio@30220000 {
365 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
366 reg = <0x30220000 0x10000>;
367 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
09892aa1 369 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
a05ea40e
JB		 370 gpio-controller;
371 #gpio-cells = <2>;
372 interrupt-controller;
373 #interrupt-cells = <2>;
15626359 374 gpio-ranges = <&iomuxc 0 61 26>;
a05ea40e
JB		 375 };
376
377 gpio4: gpio@30230000 {
378 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
379 reg = <0x30230000 0x10000>;
380 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
381 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
09892aa1 382 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
a05ea40e
JB		 383 gpio-controller;
384 #gpio-cells = <2>;
385 interrupt-controller;
386 #interrupt-cells = <2>;
15626359 387 gpio-ranges = <&iomuxc 0 87 32>;
a05ea40e
JB		 388 };
389
390 gpio5: gpio@30240000 {
391 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
392 reg = <0x30240000 0x10000>;
393 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
394 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
09892aa1 395 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
a05ea40e
JB		 396 gpio-controller;
397 #gpio-cells = <2>;
398 interrupt-controller;
399 #interrupt-cells = <2>;
15626359 400 gpio-ranges = <&iomuxc 0 119 30>;
a05ea40e
JB		 401 };
402
11699fd5
AH		 403 tmu: tmu@30260000 {
404 compatible = "fsl,imx8mm-tmu";
405 reg = <0x30260000 0x10000>;
406 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
407 #thermal-sensor-cells = <0>;
408 };
409
a05ea40e
JB		 410 wdog1: watchdog@30280000 {
411 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
412 reg = <0x30280000 0x10000>;
413 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
415 status = "disabled";
416 };
417
418 wdog2: watchdog@30290000 {
419 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
420 reg = <0x30290000 0x10000>;
421 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
422 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
423 status = "disabled";
424 };
425
426 wdog3: watchdog@302a0000 {
427 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
428 reg = <0x302a0000 0x10000>;
429 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
431 status = "disabled";
432 };
433
434 sdma2: dma-controller@302c0000 {
e346ff93 435 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
a05ea40e
JB		 436 reg = <0x302c0000 0x10000>;
437 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
438 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
439 <&clk IMX8MM_CLK_SDMA2_ROOT>;
440 clock-names = "ipg", "ahb";
441 #dma-cells = <3>;
442 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
443 };
444
445 sdma3: dma-controller@302b0000 {
e346ff93 446 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
a05ea40e
JB		 447 reg = <0x302b0000 0x10000>;
448 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
450 <&clk IMX8MM_CLK_SDMA3_ROOT>;
451 clock-names = "ipg", "ahb";
452 #dma-cells = <3>;
453 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
454 };
455
456 iomuxc: pinctrl@30330000 {
457 compatible = "fsl,imx8mm-iomuxc";
458 reg = <0x30330000 0x10000>;
459 };
460
461 gpr: iomuxc-gpr@30340000 {
462 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
463 reg = <0x30340000 0x10000>;
464 };
465
466 ocotp: ocotp-ctrl@30350000 {
b09802a0 467 compatible = "fsl,imx8mm-ocotp", "syscon";
a05ea40e
JB		 468 reg = <0x30350000 0x10000>;
469 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
470 /* For nvmem subnodes */
471 #address-cells = <1>;
472 #size-cells = <1>;
f403a26c
LC		 473
474 cpu_speed_grade: speed-grade@10 {
475 reg = <0x10 4>;
476 };
a05ea40e
JB		 477 };
478
479 anatop: anatop@30360000 {
0900a484 480 compatible = "fsl,imx8mm-anatop", "syscon";
a05ea40e
JB		 481 reg = <0x30360000 0x10000>;
482 };
483
484 snvs: snvs@30370000 {
485 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
486 reg = <0x30370000 0x10000>;
487
488 snvs_rtc: snvs-rtc-lp {
489 compatible = "fsl,sec-v4.0-mon-rtc-lp";
490 regmap = <&snvs>;
491 offset = <0x34>;
492 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
f145b209
AH		 494 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
495 clock-names = "snvs-rtc";
a05ea40e
JB		 496 };
497
498 snvs_pwrkey: snvs-powerkey {
499 compatible = "fsl,sec-v4.0-pwrkey";
500 regmap = <&snvs>;
501 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
46770eae
AD		 502 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
503 clock-names = "snvs-pwrkey";
a05ea40e
JB		 504 linux,keycode = <KEY_POWER>;
505 wakeup-source;
d038c1dc 506 status = "disabled";
a05ea40e
JB		 507 };
508 };
509
510 clk: clock-controller@30380000 {
511 compatible = "fsl,imx8mm-ccm";
512 reg = <0x30380000 0x10000>;
513 #clock-cells = <1>;
514 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
515 <&clk_ext3>, <&clk_ext4>;
516 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
517 "clk_ext3", "clk_ext4";
6b392e16
AV		 518 assigned-clocks = <&clk IMX8MM_CLK_NOC>,
519 <&clk IMX8MM_CLK_AUDIO_AHB>,
520 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
521 <&clk IMX8MM_SYS_PLL3>,
e8b395b2
W		 522 <&clk IMX8MM_VIDEO_PLL1>,
523 <&clk IMX8MM_AUDIO_PLL1>,
524 <&clk IMX8MM_AUDIO_PLL2>;
6b392e16
AV		 525 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
526 <&clk IMX8MM_SYS_PLL1_800M>;
527 assigned-clock-rates = <0>,
528 <400000000>,
529 <400000000>,
530 <750000000>,
e8b395b2
W		 531 <594000000>,
532 <393216000>,
533 <361267200>;
a05ea40e
JB		 534 };
535
536 src: reset-controller@30390000 {
46b29f4b 537 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
a05ea40e
JB		 538 reg = <0x30390000 0x10000>;
539 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
540 #reset-cells = <1>;
541 };
542 };
543
544 aips2: bus@30400000 {
dc3efc6f 545 compatible = "fsl,aips-bus", "simple-bus";
921a6845 546 reg = <0x30400000 0x400000>;
a05ea40e
JB		 547 #address-cells = <1>;
548 #size-cells = <1>;
10c74207 549 ranges = <0x30400000 0x30400000 0x400000>;
a05ea40e
JB		 550
551 pwm1: pwm@30660000 {
552 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
553 reg = <0x30660000 0x10000>;
554 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
555 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
556 <&clk IMX8MM_CLK_PWM1_ROOT>;
557 clock-names = "ipg", "per";
558 #pwm-cells = <2>;
559 status = "disabled";
560 };
561
562 pwm2: pwm@30670000 {
563 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
564 reg = <0x30670000 0x10000>;
565 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
566 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
567 <&clk IMX8MM_CLK_PWM2_ROOT>;
568 clock-names = "ipg", "per";
569 #pwm-cells = <2>;
570 status = "disabled";
571 };
572
573 pwm3: pwm@30680000 {
574 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
575 reg = <0x30680000 0x10000>;
576 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
577 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
578 <&clk IMX8MM_CLK_PWM3_ROOT>;
579 clock-names = "ipg", "per";
580 #pwm-cells = <2>;
581 status = "disabled";
582 };
583
584 pwm4: pwm@30690000 {
585 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
586 reg = <0x30690000 0x10000>;
587 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
588 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
589 <&clk IMX8MM_CLK_PWM4_ROOT>;
590 clock-names = "ipg", "per";
591 #pwm-cells = <2>;
592 status = "disabled";
593 };
5b0221bf
AH		 594
595 system_counter: timer@306a0000 {
596 compatible = "nxp,sysctr-timer";
597 reg = <0x306a0000 0x20000>;
598 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&osc_24m>;
600 clock-names = "per";
601 };
a05ea40e
JB		 602 };
603
604 aips3: bus@30800000 {
dc3efc6f 605 compatible = "fsl,aips-bus", "simple-bus";
921a6845 606 reg = <0x30800000 0x400000>;
a05ea40e
JB		 607 #address-cells = <1>;
608 #size-cells = <1>;
f0692bb8
AF		 609 ranges = <0x30800000 0x30800000 0x400000>,
610 <0x8000000 0x8000000 0x10000000>;
a05ea40e
JB		 611
612 ecspi1: spi@30820000 {
613 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
614 #address-cells = <1>;
615 #size-cells = <0>;
616 reg = <0x30820000 0x10000>;
617 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
619 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
620 clock-names = "ipg", "per";
621 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
622 dma-names = "rx", "tx";
623 status = "disabled";
624 };
625
626 ecspi2: spi@30830000 {
627 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
628 #address-cells = <1>;
629 #size-cells = <0>;
630 reg = <0x30830000 0x10000>;
631 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
633 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
634 clock-names = "ipg", "per";
635 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
636 dma-names = "rx", "tx";
637 status = "disabled";
638 };
639
640 ecspi3: spi@30840000 {
641 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
642 #address-cells = <1>;
643 #size-cells = <0>;
644 reg = <0x30840000 0x10000>;
645 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
646 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
647 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
648 clock-names = "ipg", "per";
649 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
650 dma-names = "rx", "tx";
651 status = "disabled";
652 };
653
654 uart1: serial@30860000 {
655 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
656 reg = <0x30860000 0x10000>;
657 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
658 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
659 <&clk IMX8MM_CLK_UART1_ROOT>;
660 clock-names = "ipg", "per";
661 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
662 dma-names = "rx", "tx";
663 status = "disabled";
664 };
665
666 uart3: serial@30880000 {
667 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
668 reg = <0x30880000 0x10000>;
669 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
671 <&clk IMX8MM_CLK_UART3_ROOT>;
672 clock-names = "ipg", "per";
673 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
674 dma-names = "rx", "tx";
675 status = "disabled";
676 };
677
678 uart2: serial@30890000 {
679 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
680 reg = <0x30890000 0x10000>;
681 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
683 <&clk IMX8MM_CLK_UART2_ROOT>;
684 clock-names = "ipg", "per";
685 status = "disabled";
686 };
687
bff5b972
AF		 688 crypto: crypto@30900000 {
689 compatible = "fsl,sec-v4.0";
690 #address-cells = <1>;
691 #size-cells = <1>;
692 reg = <0x30900000 0x40000>;
693 ranges = <0 0x30900000 0x40000>;
694 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&clk IMX8MM_CLK_AHB>,
696 <&clk IMX8MM_CLK_IPG_ROOT>;
697 clock-names = "aclk", "ipg";
698
699 sec_jr0: jr@1000 {
700 compatible = "fsl,sec-v4.0-job-ring";
701 reg = <0x1000 0x1000>;
702 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
703 };
704
705 sec_jr1: jr@2000 {
706 compatible = "fsl,sec-v4.0-job-ring";
707 reg = <0x2000 0x1000>;
708 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
709 };
710
711 sec_jr2: jr@3000 {
712 compatible = "fsl,sec-v4.0-job-ring";
713 reg = <0x3000 0x1000>;
714 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
715 };
716 };
717
a05ea40e
JB		 718 i2c1: i2c@30a20000 {
719 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
720 #address-cells = <1>;
721 #size-cells = <0>;
722 reg = <0x30a20000 0x10000>;
723 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
724 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
725 status = "disabled";
726 };
727
728 i2c2: i2c@30a30000 {
729 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
730 #address-cells = <1>;
731 #size-cells = <0>;
732 reg = <0x30a30000 0x10000>;
733 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
734 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
735 status = "disabled";
736 };
737
738 i2c3: i2c@30a40000 {
739 #address-cells = <1>;
740 #size-cells = <0>;
741 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
742 reg = <0x30a40000 0x10000>;
743 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
745 status = "disabled";
746 };
747
748 i2c4: i2c@30a50000 {
749 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
750 #address-cells = <1>;
751 #size-cells = <0>;
752 reg = <0x30a50000 0x10000>;
753 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
754 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
755 status = "disabled";
756 };
757
758 uart4: serial@30a60000 {
759 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
760 reg = <0x30a60000 0x10000>;
761 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
762 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
763 <&clk IMX8MM_CLK_UART4_ROOT>;
764 clock-names = "ipg", "per";
765 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
766 dma-names = "rx", "tx";
767 status = "disabled";
768 };
769
770 usdhc1: mmc@30b40000 {
771 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
772 reg = <0x30b40000 0x10000>;
773 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
a6a40d56 774 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
a05ea40e
JB		 775 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
776 <&clk IMX8MM_CLK_USDHC1_ROOT>;
777 clock-names = "ipg", "ahb", "per";
a05ea40e
JB		 778 fsl,tuning-start-tap = <20>;
779 fsl,tuning-step= <2>;
780 bus-width = <4>;
781 status = "disabled";
782 };
783
784 usdhc2: mmc@30b50000 {
785 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
786 reg = <0x30b50000 0x10000>;
787 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
a6a40d56 788 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
a05ea40e
JB		 789 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
790 <&clk IMX8MM_CLK_USDHC2_ROOT>;
791 clock-names = "ipg", "ahb", "per";
792 fsl,tuning-start-tap = <20>;
793 fsl,tuning-step= <2>;
794 bus-width = <4>;
795 status = "disabled";
796 };
797
798 usdhc3: mmc@30b60000 {
799 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
800 reg = <0x30b60000 0x10000>;
801 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
a6a40d56 802 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
a05ea40e
JB		 803 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
804 <&clk IMX8MM_CLK_USDHC3_ROOT>;
805 clock-names = "ipg", "ahb", "per";
a05ea40e
JB		 806 fsl,tuning-start-tap = <20>;
807 fsl,tuning-step= <2>;
808 bus-width = <4>;
809 status = "disabled";
810 };
811
f0692bb8
AF		 812 flexspi: spi@30bb0000 {
813 #address-cells = <1>;
814 #size-cells = <0>;
815 compatible = "nxp,imx8mm-fspi";
816 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
817 reg-names = "fspi_base", "fspi_mmap";
818 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
819 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
820 <&clk IMX8MM_CLK_QSPI_ROOT>;
821 clock-names = "fspi", "fspi_en";
822 status = "disabled";
823 };
824
a05ea40e 825 sdma1: dma-controller@30bd0000 {
e346ff93 826 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
a05ea40e
JB		 827 reg = <0x30bd0000 0x10000>;
828 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
24a572bf 830 <&clk IMX8MM_CLK_AHB>;
a05ea40e
JB		 831 clock-names = "ipg", "ahb";
832 #dma-cells = <3>;
833 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
834 };
835
836 fec1: ethernet@30be0000 {
837 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
838 reg = <0x30be0000 0x10000>;
839 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
840 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
841 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
842 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
843 <&clk IMX8MM_CLK_ENET1_ROOT>,
844 <&clk IMX8MM_CLK_ENET_TIMER>,
845 <&clk IMX8MM_CLK_ENET_REF>,
846 <&clk IMX8MM_CLK_ENET_PHY_REF>;
847 clock-names = "ipg", "ahb", "ptp",
848 "enet_clk_ref", "enet_out";
849 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
850 <&clk IMX8MM_CLK_ENET_TIMER>,
851 <&clk IMX8MM_CLK_ENET_REF>,
852 <&clk IMX8MM_CLK_ENET_TIMER>;
853 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
854 <&clk IMX8MM_SYS_PLL2_100M>,
855 <&clk IMX8MM_SYS_PLL2_125M>;
856 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
857 fsl,num-tx-queues = <3>;
858 fsl,num-rx-queues = <3>;
859 status = "disabled";
860 };
861
862 };
863
864 aips4: bus@32c00000 {
dc3efc6f 865 compatible = "fsl,aips-bus", "simple-bus";
921a6845 866 reg = <0x32c00000 0x400000>;
a05ea40e
JB		 867 #address-cells = <1>;
868 #size-cells = <1>;
10c74207 869 ranges = <0x32c00000 0x32c00000 0x400000>;
a05ea40e
JB		 870
871 usbotg1: usb@32e40000 {
872 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
873 reg = <0x32e40000 0x200>;
874 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
876 clock-names = "usb1_ctrl_root_clk";
8b01840e
LJ		 877 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
878 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
a05ea40e
JB		 879 fsl,usbphy = <&usbphynop1>;
880 fsl,usbmisc = <&usbmisc1 0>;
881 status = "disabled";
882 };
883
a05ea40e
JB		 884 usbmisc1: usbmisc@32e40200 {
885 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
886 #index-cells = <1>;
887 reg = <0x32e40200 0x200>;
888 };
889
890 usbotg2: usb@32e50000 {
891 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
892 reg = <0x32e50000 0x200>;
893 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
895 clock-names = "usb1_ctrl_root_clk";
8b01840e
LJ		 896 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
897 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
a05ea40e
JB		 898 fsl,usbphy = <&usbphynop2>;
899 fsl,usbmisc = <&usbmisc2 0>;
900 status = "disabled";
901 };
902
a05ea40e
JB		 903 usbmisc2: usbmisc@32e50200 {
904 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
905 #index-cells = <1>;
906 reg = <0x32e50200 0x200>;
907 };
908
909 };
910
911 dma_apbh: dma-controller@33000000 {
912 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
913 reg = <0x33000000 0x2000>;
914 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
915 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
916 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
917 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
918 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
919 #dma-cells = <1>;
920 dma-channels = <4>;
921 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
922 };
923
924 gpmi: nand-controller@33002000{
925 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
926 #address-cells = <1>;
927 #size-cells = <1>;
928 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
929 reg-names = "gpmi-nand", "bch";
930 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
931 interrupt-names = "bch";
932 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
933 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
934 clock-names = "gpmi_io", "gpmi_bch_apb";
935 dmas = <&dma_apbh 0>;
936 dma-names = "rx-tx";
937 status = "disabled";
938 };
b4e3e54a
AH		 939
940 gic: interrupt-controller@38800000 {
941 compatible = "arm,gic-v3";
942 reg = <0x38800000 0x10000>, /* GIC Dist */
943 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
944 #interrupt-cells = <3>;
945 interrupt-controller;
946 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
947 };
1efe85c9 948
0376f6ec
LC		 949 ddrc: memory-controller@3d400000 {
950 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
951 reg = <0x3d400000 0x400000>;
952 clock-names = "core", "pll", "alt", "apb";
953 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
954 <&clk IMX8MM_DRAM_PLL>,
955 <&clk IMX8MM_CLK_DRAM_ALT>,
956 <&clk IMX8MM_CLK_DRAM_APB>;
957 };
958
1efe85c9
LC		 959 ddr-pmu@3d800000 {
960 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
961 reg = <0x3d800000 0x400000>;
1efe85c9
LC		 962 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
963 };
a05ea40e
JB		 964 };
965};
A mirror of Linus' kernel repository