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Merge tag 'loongarch-kvm-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhu...
[thirdparty/kernel/stable.git] / arch / arm64 / boot / dts / freescale / imx93.dtsi
CommitLineData
ec8b5b50
PF		 1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 NXP
4 */
5
6#include <dt-bindings/clock/imx93-clock.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/input/input.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
a90a37bb 10#include <dt-bindings/power/fsl,imx93-power.h>
7f916a6f 11#include <dt-bindings/thermal/thermal.h>
ec8b5b50
PF		 12
13#include "imx93-pinfunc.h"
14
15/ {
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
435bfa00
HC		 21 gpio0 = &gpio1;
22 gpio1 = &gpio2;
23 gpio2 = &gpio3;
24 gpio3 = &gpio4;
1225396f
PF		 25 i2c0 = &lpi2c1;
26 i2c1 = &lpi2c2;
27 i2c2 = &lpi2c3;
28 i2c3 = &lpi2c4;
29 i2c4 = &lpi2c5;
30 i2c5 = &lpi2c6;
31 i2c6 = &lpi2c7;
32 i2c7 = &lpi2c8;
ec8b5b50
PF		 33 mmc0 = &usdhc1;
34 mmc1 = &usdhc2;
35 mmc2 = &usdhc3;
36 serial0 = &lpuart1;
37 serial1 = &lpuart2;
38 serial2 = &lpuart3;
39 serial3 = &lpuart4;
40 serial4 = &lpuart5;
41 serial5 = &lpuart6;
42 serial6 = &lpuart7;
43 serial7 = &lpuart8;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
afbd37e8
PF		 50 idle-states {
51 entry-method = "psci";
52
53 cpu_pd_wait: cpu-pd-wait {
54 compatible = "arm,idle-state";
55 arm,psci-suspend-param = <0x0010033>;
56 local-timer-stop;
57 entry-latency-us = <10000>;
58 exit-latency-us = <7000>;
59 min-residency-us = <27000>;
60 wakeup-latency-us = <15000>;
61 };
62 };
63
ec8b5b50
PF		 64 A55_0: cpu@0 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a55";
67 reg = <0x0>;
68 enable-method = "psci";
69 #cooling-cells = <2>;
afbd37e8 70 cpu-idle-states = <&cpu_pd_wait>;
ec8b5b50
PF		 71 };
72
73 A55_1: cpu@100 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a55";
76 reg = <0x100>;
77 enable-method = "psci";
78 #cooling-cells = <2>;
afbd37e8 79 cpu-idle-states = <&cpu_pd_wait>;
ec8b5b50
PF		 80 };
81
82 };
83
84 osc_32k: clock-osc-32k {
85 compatible = "fixed-clock";
86 #clock-cells = <0>;
87 clock-frequency = <32768>;
88 clock-output-names = "osc_32k";
89 };
90
91 osc_24m: clock-osc-24m {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <24000000>;
95 clock-output-names = "osc_24m";
96 };
97
98 clk_ext1: clock-ext1 {
99 compatible = "fixed-clock";
100 #clock-cells = <0>;
101 clock-frequency = <133000000>;
102 clock-output-names = "clk_ext1";
103 };
104
b4aa33b3
PF		 105 pmu {
106 compatible = "arm,cortex-a55-pmu";
107 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
108 };
109
ec8b5b50
PF		 110 psci {
111 compatible = "arm,psci-1.0";
112 method = "smc";
113 };
114
115 timer {
116 compatible = "arm,armv8-timer";
117 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
118 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
119 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
120 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
121 clock-frequency = <24000000>;
122 arm,no-tick-in-suspend;
123 interrupt-parent = <&gic>;
124 };
125
126 gic: interrupt-controller@48000000 {
127 compatible = "arm,gic-v3";
128 reg = <0 0x48000000 0 0x10000>,
129 <0 0x48040000 0 0xc0000>;
130 #interrupt-cells = <3>;
131 interrupt-controller;
132 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
133 interrupt-parent = <&gic>;
134 };
135
7f916a6f
PF		 136 thermal-zones {
137 cpu-thermal {
138 polling-delay-passive = <250>;
139 polling-delay = <2000>;
140
141 thermal-sensors = <&tmu 0>;
142
143 trips {
144 cpu_alert: cpu-alert {
145 temperature = <80000>;
146 hysteresis = <2000>;
147 type = "passive";
148 };
149
150 cpu_crit: cpu-crit {
151 temperature = <90000>;
152 hysteresis = <2000>;
153 type = "critical";
154 };
155 };
156
157 cooling-maps {
158 map0 {
159 trip = <&cpu_alert>;
160 cooling-device =
161 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
162 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
163 };
164 };
165 };
166 };
167
48a3c682
PF		 168 cm33: remoteproc-cm33 {
169 compatible = "fsl,imx93-cm33";
170 clocks = <&clk IMX93_CLK_CM33_GATE>;
171 status = "disabled";
172 };
173
ec8b5b50
PF		 174 soc@0 {
175 compatible = "simple-bus";
176 #address-cells = <1>;
177 #size-cells = <1>;
178 ranges = <0x0 0x0 0x0 0x80000000>,
179 <0x28000000 0x0 0x28000000 0x10000000>;
180
181 aips1: bus@44000000 {
182 compatible = "fsl,aips-bus", "simple-bus";
183 reg = <0x44000000 0x800000>;
184 #address-cells = <1>;
185 #size-cells = <1>;
186 ranges;
187
d34d2aa5
FL		 188 edma1: dma-controller@44000000 {
189 compatible = "fsl,imx93-edma3";
190 reg = <0x44000000 0x200000>;
191 #dma-cells = <3>;
192 dma-channels = <31>;
193 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved
194 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1
195 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved
196 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0
197 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1
198 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus
199 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus
200 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX
201 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX
202 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX
203 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX
204 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX
205 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX
206 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX
207 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX
208 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1
209 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX
210 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX
211 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX
212 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX
213 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400
214 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX
215 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX
216 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2
217 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3
218 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow
219 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2
220 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3
221 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow
222 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM
223 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1
224 clocks = <&clk IMX93_CLK_EDMA1_GATE>;
225 clock-names = "dma";
226 };
227
23ed2be5 228 aonmix_ns_gpr: syscon@44210000 {
000aed86
PF		 229 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon";
230 reg = <0x44210000 0x1000>;
231 };
232
ec8b5b50
PF		 233 mu1: mailbox@44230000 {
234 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
235 reg = <0x44230000 0x10000>;
236 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
d8f011d7 237 clocks = <&clk IMX93_CLK_MU1_B_GATE>;
ec8b5b50
PF		 238 #mbox-cells = <2>;
239 status = "disabled";
240 };
241
242 system_counter: timer@44290000 {
243 compatible = "nxp,sysctr-timer";
244 reg = <0x44290000 0x30000>;
245 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
246 clocks = <&osc_24m>;
247 clock-names = "per";
bce9f6f7 248 nxp,no-divider;
ec8b5b50
PF		 249 };
250
84e29d79
PF		 251 wdog1: watchdog@442d0000 {
252 compatible = "fsl,imx93-wdt";
253 reg = <0x442d0000 0x10000>;
254 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
255 clocks = <&clk IMX93_CLK_WDOG1_GATE>;
256 timeout-sec = <40>;
257 status = "disabled";
258 };
259
260 wdog2: watchdog@442e0000 {
261 compatible = "fsl,imx93-wdt";
262 reg = <0x442e0000 0x10000>;
263 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clk IMX93_CLK_WDOG2_GATE>;
265 timeout-sec = <40>;
266 status = "disabled";
267 };
268
20d4640b
MN		 269 tpm1: pwm@44310000 {
270 compatible = "fsl,imx7ulp-pwm";
271 reg = <0x44310000 0x1000>;
272 clocks = <&clk IMX93_CLK_TPM1_GATE>;
273 #pwm-cells = <3>;
274 status = "disabled";
275 };
276
3f932b4d
PF		 277 tpm2: pwm@44320000 {
278 compatible = "fsl,imx7ulp-pwm";
279 reg = <0x44320000 0x10000>;
280 clocks = <&clk IMX93_CLK_TPM2_GATE>;
281 #pwm-cells = <3>;
282 status = "disabled";
ec8b5b50
PF		 283 };
284
1225396f
PF		 285 lpi2c1: i2c@44340000 {
286 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
287 reg = <0x44340000 0x10000>;
b3cdf730
AS		 288 #address-cells = <1>;
289 #size-cells = <0>;
1225396f
PF		 290 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&clk IMX93_CLK_LPI2C1_GATE>,
292 <&clk IMX93_CLK_BUS_AON>;
293 clock-names = "per", "ipg";
294 status = "disabled";
295 };
296
297 lpi2c2: i2c@44350000 {
298 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
299 reg = <0x44350000 0x10000>;
b3cdf730
AS		 300 #address-cells = <1>;
301 #size-cells = <0>;
1225396f
PF		 302 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&clk IMX93_CLK_LPI2C2_GATE>,
304 <&clk IMX93_CLK_BUS_AON>;
305 clock-names = "per", "ipg";
306 status = "disabled";
307 };
308
aff77421
PF		 309 lpspi1: spi@44360000 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
313 reg = <0x44360000 0x10000>;
314 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&clk IMX93_CLK_LPSPI1_GATE>,
316 <&clk IMX93_CLK_BUS_AON>;
317 clock-names = "per", "ipg";
318 status = "disabled";
319 };
320
321 lpspi2: spi@44370000 {
322 #address-cells = <1>;
323 #size-cells = <0>;
324 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
325 reg = <0x44370000 0x10000>;
326 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&clk IMX93_CLK_LPSPI2_GATE>,
328 <&clk IMX93_CLK_BUS_AON>;
329 clock-names = "per", "ipg";
330 status = "disabled";
331 };
332
ec8b5b50 333 lpuart1: serial@44380000 {
258bd863 334 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
ec8b5b50
PF		 335 reg = <0x44380000 0x1000>;
336 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&clk IMX93_CLK_LPUART1_GATE>;
338 clock-names = "ipg";
a7259905
FE		 339 dmas = <&edma1 17 0 1>, <&edma1 16 0 0>;
340 dma-names = "rx", "tx";
ec8b5b50
PF		 341 status = "disabled";
342 };
343
344 lpuart2: serial@44390000 {
258bd863 345 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
ec8b5b50
PF		 346 reg = <0x44390000 0x1000>;
347 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&clk IMX93_CLK_LPUART2_GATE>;
349 clock-names = "ipg";
a7259905
FE		 350 dmas = <&edma1 19 0 1>, <&edma1 18 0 0>;
351 dma-names = "rx", "tx";
ec8b5b50
PF		 352 status = "disabled";
353 };
354
b579e901
HC		 355 flexcan1: can@443a0000 {
356 compatible = "fsl,imx93-flexcan";
357 reg = <0x443a0000 0x10000>;
358 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&clk IMX93_CLK_BUS_AON>,
360 <&clk IMX93_CLK_CAN1_GATE>;
361 clock-names = "ipg", "per";
362 assigned-clocks = <&clk IMX93_CLK_CAN1>;
363 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
364 assigned-clock-rates = <40000000>;
365 fsl,clk-source = /bits/ 8 <0>;
23ed2be5 366 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>;
b579e901
HC		 367 status = "disabled";
368 };
369
ec8b5b50
PF		 370 iomuxc: pinctrl@443c0000 {
371 compatible = "fsl,imx93-iomuxc";
372 reg = <0x443c0000 0x10000>;
373 status = "okay";
374 };
375
cc3cb392
JB		 376 bbnsm: bbnsm@44440000 {
377 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd";
378 reg = <0x44440000 0x10000>;
379
380 bbnsm_rtc: rtc {
381 compatible = "nxp,imx93-bbnsm-rtc";
382 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
383 };
384
385 bbnsm_pwrkey: pwrkey {
386 compatible = "nxp,imx93-bbnsm-pwrkey";
387 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
388 linux,code = <KEY_POWER>;
389 };
390 };
391
ec8b5b50
PF		 392 clk: clock-controller@44450000 {
393 compatible = "fsl,imx93-ccm";
394 reg = <0x44450000 0x10000>;
395 #clock-cells = <1>;
396 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>;
397 clock-names = "osc_32k", "osc_24m", "clk_ext1";
398 status = "okay";
399 };
400
e85d3458
PF		 401 src: system-controller@44460000 {
402 compatible = "fsl,imx93-src", "syscon";
403 reg = <0x44460000 0x10000>;
404 #address-cells = <1>;
405 #size-cells = <1>;
406 ranges;
407
e85d3458
PF		 408 mlmix: power-domain@44461800 {
409 compatible = "fsl,imx93-src-slice";
410 reg = <0x44461800 0x400>, <0x44464800 0x400>;
411 #power-domain-cells = <0>;
412 clocks = <&clk IMX93_CLK_ML_APB>,
413 <&clk IMX93_CLK_ML>;
414 };
f2d03ba9
PF		 415
416 mediamix: power-domain@44462400 {
417 compatible = "fsl,imx93-src-slice";
418 reg = <0x44462400 0x400>, <0x44465800 0x400>;
419 #power-domain-cells = <0>;
d4cb68a5 420 clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>,
f2d03ba9
PF		 421 <&clk IMX93_CLK_MEDIA_APB>;
422 };
e85d3458
PF		 423 };
424
ec8b5b50
PF		 425 anatop: anatop@44480000 {
426 compatible = "fsl,imx93-anatop", "syscon";
78e869dd 427 reg = <0x44480000 0x2000>;
ec8b5b50 428 };
5d11fe56 429
7f916a6f
PF		 430 tmu: tmu@44482000 {
431 compatible = "fsl,qoriq-tmu";
432 reg = <0x44482000 0x1000>;
109ff9ed 433 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
7f916a6f
PF		 434 clocks = <&clk IMX93_CLK_TMC_GATE>;
435 little-endian;
436 fsl,tmu-range = <0x800000da 0x800000e9
437 0x80000102 0x8000012a
438 0x80000166 0x800001a7
439 0x800001b6>;
440 fsl,tmu-calibration = <0x00000000 0x0000000e
441 0x00000001 0x00000029
442 0x00000002 0x00000056
443 0x00000003 0x000000a2
444 0x00000004 0x00000116
445 0x00000005 0x00000195
446 0x00000006 0x000001b2>;
447 #thermal-sensor-cells = <1>;
448 };
449
450
5d11fe56
HC		 451 adc1: adc@44530000 {
452 compatible = "nxp,imx93-adc";
453 reg = <0x44530000 0x10000>;
454 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
455 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
456 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
457 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
458 clocks = <&clk IMX93_CLK_ADC1_GATE>;
459 clock-names = "ipg";
460 #io-channel-cells = <1>;
461 status = "disabled";
462 };
ec8b5b50
PF		 463 };
464
465 aips2: bus@42000000 {
466 compatible = "fsl,aips-bus", "simple-bus";
467 reg = <0x42000000 0x800000>;
468 #address-cells = <1>;
469 #size-cells = <1>;
470 ranges;
471
d34d2aa5
FL		 472 edma2: dma-controller@42000000 {
473 compatible = "fsl,imx93-edma4";
474 reg = <0x42000000 0x210000>;
475 #dma-cells = <3>;
476 shared-interrupt;
477 dma-channels = <64>;
478 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
505 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
506 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
507 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
508 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
509 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
511 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
512 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
513 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
514 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
518 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
519 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
520 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
521 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
522 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
523 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
542 clocks = <&clk IMX93_CLK_EDMA2_GATE>;
543 clock-names = "dma";
544 };
545
000aed86
PF		 546 wakeupmix_gpr: syscon@42420000 {
547 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon";
548 reg = <0x42420000 0x1000>;
549 };
550
ec8b5b50
PF		 551 mu2: mailbox@42440000 {
552 compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
553 reg = <0x42440000 0x10000>;
554 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
d8f011d7 555 clocks = <&clk IMX93_CLK_MU2_B_GATE>;
ec8b5b50
PF		 556 #mbox-cells = <2>;
557 status = "disabled";
558 };
559
84e29d79
PF		 560 wdog3: watchdog@42490000 {
561 compatible = "fsl,imx93-wdt";
562 reg = <0x42490000 0x10000>;
563 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&clk IMX93_CLK_WDOG3_GATE>;
565 timeout-sec = <40>;
566 status = "disabled";
567 };
568
569 wdog4: watchdog@424a0000 {
570 compatible = "fsl,imx93-wdt";
571 reg = <0x424a0000 0x10000>;
572 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clk IMX93_CLK_WDOG4_GATE>;
574 timeout-sec = <40>;
575 status = "disabled";
576 };
577
578 wdog5: watchdog@424b0000 {
579 compatible = "fsl,imx93-wdt";
580 reg = <0x424b0000 0x10000>;
581 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&clk IMX93_CLK_WDOG5_GATE>;
583 timeout-sec = <40>;
584 status = "disabled";
585 };
586
20d4640b
MN		 587 tpm3: pwm@424e0000 {
588 compatible = "fsl,imx7ulp-pwm";
589 reg = <0x424e0000 0x1000>;
590 clocks = <&clk IMX93_CLK_TPM3_GATE>;
591 #pwm-cells = <3>;
592 status = "disabled";
593 };
594
3f932b4d
PF		 595 tpm4: pwm@424f0000 {
596 compatible = "fsl,imx7ulp-pwm";
597 reg = <0x424f0000 0x10000>;
598 clocks = <&clk IMX93_CLK_TPM4_GATE>;
599 #pwm-cells = <3>;
600 status = "disabled";
601 };
602
603 tpm5: pwm@42500000 {
604 compatible = "fsl,imx7ulp-pwm";
605 reg = <0x42500000 0x10000>;
606 clocks = <&clk IMX93_CLK_TPM5_GATE>;
607 #pwm-cells = <3>;
608 status = "disabled";
609 };
610
611 tpm6: pwm@42510000 {
612 compatible = "fsl,imx7ulp-pwm";
613 reg = <0x42510000 0x10000>;
614 clocks = <&clk IMX93_CLK_TPM6_GATE>;
615 #pwm-cells = <3>;
616 status = "disabled";
617 };
618
1225396f
PF		 619 lpi2c3: i2c@42530000 {
620 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
621 reg = <0x42530000 0x10000>;
b3cdf730
AS		 622 #address-cells = <1>;
623 #size-cells = <0>;
1225396f
PF		 624 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&clk IMX93_CLK_LPI2C3_GATE>,
626 <&clk IMX93_CLK_BUS_WAKEUP>;
627 clock-names = "per", "ipg";
628 status = "disabled";
629 };
630
631 lpi2c4: i2c@42540000 {
632 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
633 reg = <0x42540000 0x10000>;
b3cdf730
AS		 634 #address-cells = <1>;
635 #size-cells = <0>;
1225396f
PF		 636 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
637 clocks = <&clk IMX93_CLK_LPI2C4_GATE>,
638 <&clk IMX93_CLK_BUS_WAKEUP>;
639 clock-names = "per", "ipg";
640 status = "disabled";
641 };
642
80e56689
PF		 643 lpspi3: spi@42550000 {
644 #address-cells = <1>;
645 #size-cells = <0>;
646 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
647 reg = <0x42550000 0x10000>;
648 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
649 clocks = <&clk IMX93_CLK_LPSPI3_GATE>,
650 <&clk IMX93_CLK_BUS_WAKEUP>;
651 clock-names = "per", "ipg";
652 status = "disabled";
653 };
654
655 lpspi4: spi@42560000 {
656 #address-cells = <1>;
657 #size-cells = <0>;
658 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
659 reg = <0x42560000 0x10000>;
660 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&clk IMX93_CLK_LPSPI4_GATE>,
662 <&clk IMX93_CLK_BUS_WAKEUP>;
663 clock-names = "per", "ipg";
664 status = "disabled";
665 };
666
ec8b5b50 667 lpuart3: serial@42570000 {
258bd863 668 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
ec8b5b50
PF		 669 reg = <0x42570000 0x1000>;
670 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
671 clocks = <&clk IMX93_CLK_LPUART3_GATE>;
672 clock-names = "ipg";
a7259905
FE		 673 dmas = <&edma2 18 0 1>, <&edma2 17 0 0>;
674 dma-names = "rx", "tx";
ec8b5b50
PF		 675 status = "disabled";
676 };
677
678 lpuart4: serial@42580000 {
258bd863 679 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
ec8b5b50
PF		 680 reg = <0x42580000 0x1000>;
681 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&clk IMX93_CLK_LPUART4_GATE>;
683 clock-names = "ipg";
a7259905
FE		 684 dmas = <&edma2 20 0 1>, <&edma2 19 0 0>;
685 dma-names = "rx", "tx";
ec8b5b50
PF		 686 status = "disabled";
687 };
688
689 lpuart5: serial@42590000 {
258bd863 690 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
ec8b5b50
PF		 691 reg = <0x42590000 0x1000>;
692 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
693 clocks = <&clk IMX93_CLK_LPUART5_GATE>;
694 clock-names = "ipg";
a7259905
FE		 695 dmas = <&edma2 22 0 1>, <&edma2 21 0 0>;
696 dma-names = "rx", "tx";
ec8b5b50
PF		 697 status = "disabled";
698 };
699
700 lpuart6: serial@425a0000 {
258bd863 701 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
ec8b5b50
PF		 702 reg = <0x425a0000 0x1000>;
703 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
704 clocks = <&clk IMX93_CLK_LPUART6_GATE>;
705 clock-names = "ipg";
a7259905
FE		 706 dmas = <&edma2 24 0 1>, <&edma2 23 0 0>;
707 dma-names = "rx", "tx";
ec8b5b50
PF		 708 status = "disabled";
709 };
710
b579e901
HC		 711 flexcan2: can@425b0000 {
712 compatible = "fsl,imx93-flexcan";
713 reg = <0x425b0000 0x10000>;
714 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
716 <&clk IMX93_CLK_CAN2_GATE>;
717 clock-names = "ipg", "per";
718 assigned-clocks = <&clk IMX93_CLK_CAN2>;
719 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
720 assigned-clock-rates = <40000000>;
721 fsl,clk-source = /bits/ 8 <0>;
23ed2be5 722 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>;
b579e901
HC		 723 status = "disabled";
724 };
725
09220adf
AS		 726 flexspi1: spi@425e0000 {
727 compatible = "nxp,imx8mm-fspi";
728 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>;
729 reg-names = "fspi_base", "fspi_mmap";
730 #address-cells = <1>;
731 #size-cells = <0>;
732 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
733 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>,
734 <&clk IMX93_CLK_FLEXSPI1_GATE>;
735 clock-names = "fspi_en", "fspi";
736 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>;
737 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>;
738 status = "disabled";
739 };
740
ec8b5b50 741 lpuart7: serial@42690000 {
258bd863 742 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
ec8b5b50
PF		 743 reg = <0x42690000 0x1000>;
744 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
745 clocks = <&clk IMX93_CLK_LPUART7_GATE>;
746 clock-names = "ipg";
a7259905
FE		 747 dmas = <&edma2 88 0 1>, <&edma2 87 0 0>;
748 dma-names = "rx", "tx";
ec8b5b50
PF		 749 status = "disabled";
750 };
751
752 lpuart8: serial@426a0000 {
258bd863 753 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart";
ec8b5b50
PF		 754 reg = <0x426a0000 0x1000>;
755 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
756 clocks = <&clk IMX93_CLK_LPUART8_GATE>;
757 clock-names = "ipg";
a7259905
FE		 758 dmas = <&edma2 90 0 1>, <&edma2 89 0 0>;
759 dma-names = "rx", "tx";
ec8b5b50
PF		 760 status = "disabled";
761 };
1225396f
PF		 762
763 lpi2c5: i2c@426b0000 {
764 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
765 reg = <0x426b0000 0x10000>;
b3cdf730
AS		 766 #address-cells = <1>;
767 #size-cells = <0>;
1225396f
PF		 768 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
769 clocks = <&clk IMX93_CLK_LPI2C5_GATE>,
770 <&clk IMX93_CLK_BUS_WAKEUP>;
771 clock-names = "per", "ipg";
772 status = "disabled";
773 };
774
775 lpi2c6: i2c@426c0000 {
776 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
777 reg = <0x426c0000 0x10000>;
b3cdf730
AS		 778 #address-cells = <1>;
779 #size-cells = <0>;
1225396f
PF		 780 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&clk IMX93_CLK_LPI2C6_GATE>,
782 <&clk IMX93_CLK_BUS_WAKEUP>;
783 clock-names = "per", "ipg";
784 status = "disabled";
785 };
786
787 lpi2c7: i2c@426d0000 {
788 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
789 reg = <0x426d0000 0x10000>;
b3cdf730
AS		 790 #address-cells = <1>;
791 #size-cells = <0>;
1225396f
PF		 792 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
793 clocks = <&clk IMX93_CLK_LPI2C7_GATE>,
794 <&clk IMX93_CLK_BUS_WAKEUP>;
795 clock-names = "per", "ipg";
796 status = "disabled";
797 };
798
799 lpi2c8: i2c@426e0000 {
800 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c";
801 reg = <0x426e0000 0x10000>;
b3cdf730
AS		 802 #address-cells = <1>;
803 #size-cells = <0>;
1225396f
PF		 804 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
805 clocks = <&clk IMX93_CLK_LPI2C8_GATE>,
806 <&clk IMX93_CLK_BUS_WAKEUP>;
807 clock-names = "per", "ipg";
808 status = "disabled";
809 };
810
80e56689
PF		 811 lpspi5: spi@426f0000 {
812 #address-cells = <1>;
813 #size-cells = <0>;
814 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
815 reg = <0x426f0000 0x10000>;
816 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
817 clocks = <&clk IMX93_CLK_LPSPI5_GATE>,
818 <&clk IMX93_CLK_BUS_WAKEUP>;
819 clock-names = "per", "ipg";
820 status = "disabled";
821 };
822
823 lpspi6: spi@42700000 {
824 #address-cells = <1>;
825 #size-cells = <0>;
826 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
827 reg = <0x42700000 0x10000>;
828 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&clk IMX93_CLK_LPSPI6_GATE>,
830 <&clk IMX93_CLK_BUS_WAKEUP>;
831 clock-names = "per", "ipg";
832 status = "disabled";
833 };
834
835 lpspi7: spi@42710000 {
836 #address-cells = <1>;
837 #size-cells = <0>;
838 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
839 reg = <0x42710000 0x10000>;
840 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
841 clocks = <&clk IMX93_CLK_LPSPI7_GATE>,
842 <&clk IMX93_CLK_BUS_WAKEUP>;
843 clock-names = "per", "ipg";
844 status = "disabled";
845 };
846
847 lpspi8: spi@42720000 {
848 #address-cells = <1>;
849 #size-cells = <0>;
850 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi";
851 reg = <0x42720000 0x10000>;
852 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
853 clocks = <&clk IMX93_CLK_LPSPI8_GATE>,
854 <&clk IMX93_CLK_BUS_WAKEUP>;
855 clock-names = "per", "ipg";
856 status = "disabled";
1225396f
PF		 857 };
858
ec8b5b50
PF		 859 };
860
861 aips3: bus@42800000 {
862 compatible = "fsl,aips-bus", "simple-bus";
863 reg = <0x42800000 0x800000>;
864 #address-cells = <1>;
865 #size-cells = <1>;
866 ranges;
867
868 usdhc1: mmc@42850000 {
869 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
870 reg = <0x42850000 0x10000>;
871 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
f2484a94
PF		 872 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
873 <&clk IMX93_CLK_WAKEUP_AXI>,
ec8b5b50
PF		 874 <&clk IMX93_CLK_USDHC1_GATE>;
875 clock-names = "ipg", "ahb", "per";
876 bus-width = <8>;
877 fsl,tuning-start-tap = <20>;
ca788bb1 878 fsl,tuning-step = <2>;
ec8b5b50
PF		 879 status = "disabled";
880 };
881
882 usdhc2: mmc@42860000 {
883 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
884 reg = <0x42860000 0x10000>;
885 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
f2484a94
PF		 886 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
887 <&clk IMX93_CLK_WAKEUP_AXI>,
ec8b5b50
PF		 888 <&clk IMX93_CLK_USDHC2_GATE>;
889 clock-names = "ipg", "ahb", "per";
890 bus-width = <4>;
891 fsl,tuning-start-tap = <20>;
ca788bb1 892 fsl,tuning-step = <2>;
ec8b5b50
PF		 893 status = "disabled";
894 };
895
eaaf4710
CW		 896 fec: ethernet@42890000 {
897 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
898 reg = <0x42890000 0x10000>;
899 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
900 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
901 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
902 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
903 clocks = <&clk IMX93_CLK_ENET1_GATE>,
904 <&clk IMX93_CLK_ENET1_GATE>,
905 <&clk IMX93_CLK_ENET_TIMER1>,
906 <&clk IMX93_CLK_ENET_REF>,
907 <&clk IMX93_CLK_ENET_REF_PHY>;
908 clock-names = "ipg", "ahb", "ptp",
909 "enet_clk_ref", "enet_out";
910 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>,
911 <&clk IMX93_CLK_ENET_REF>,
912 <&clk IMX93_CLK_ENET_REF_PHY>;
913 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
914 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>,
915 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
916 assigned-clock-rates = <100000000>, <250000000>, <50000000>;
917 fsl,num-tx-queues = <3>;
918 fsl,num-rx-queues = <3>;
e8b4c363 919 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>;
eaaf4710
CW		 920 status = "disabled";
921 };
922
f2d03ba9
PF		 923 eqos: ethernet@428a0000 {
924 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a";
925 reg = <0x428a0000 0x10000>;
926 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
927 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
928 interrupt-names = "macirq", "eth_wake_irq";
929 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>,
930 <&clk IMX93_CLK_ENET_QOS_GATE>,
931 <&clk IMX93_CLK_ENET_TIMER2>,
932 <&clk IMX93_CLK_ENET>,
933 <&clk IMX93_CLK_ENET_QOS_GATE>;
934 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem";
935 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>,
936 <&clk IMX93_CLK_ENET>;
937 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
938 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>;
939 assigned-clock-rates = <100000000>, <250000000>;
940 intf_mode = <&wakeupmix_gpr 0x28>;
941 snps,clk-csr = <0>;
942 status = "disabled";
943 };
944
ec8b5b50
PF		 945 usdhc3: mmc@428b0000 {
946 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc";
947 reg = <0x428b0000 0x10000>;
948 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
f2484a94
PF		 949 clocks = <&clk IMX93_CLK_BUS_WAKEUP>,
950 <&clk IMX93_CLK_WAKEUP_AXI>,
ec8b5b50
PF		 951 <&clk IMX93_CLK_USDHC3_GATE>;
952 clock-names = "ipg", "ahb", "per";
953 bus-width = <4>;
954 fsl,tuning-start-tap = <20>;
ca788bb1 955 fsl,tuning-step = <2>;
ec8b5b50
PF		 956 status = "disabled";
957 };
958 };
959
4af1b258 960 gpio2: gpio@43810000 {
c1d0782b
PF		 961 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
962 reg = <0x43810000 0x1000>;
ec8b5b50
PF		 963 gpio-controller;
964 #gpio-cells = <2>;
c1d0782b
PF		 965 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
ec8b5b50
PF		 967 interrupt-controller;
968 #interrupt-cells = <2>;
e41ba695
PF		 969 clocks = <&clk IMX93_CLK_GPIO2_GATE>,
970 <&clk IMX93_CLK_GPIO2_GATE>;
971 clock-names = "gpio", "port";
d92a1101 972 gpio-ranges = <&iomuxc 0 4 30>;
ec8b5b50
PF		 973 };
974
4af1b258 975 gpio3: gpio@43820000 {
c1d0782b
PF		 976 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
977 reg = <0x43820000 0x1000>;
ec8b5b50
PF		 978 gpio-controller;
979 #gpio-cells = <2>;
c1d0782b
PF		 980 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
ec8b5b50
PF		 982 interrupt-controller;
983 #interrupt-cells = <2>;
e41ba695
PF		 984 clocks = <&clk IMX93_CLK_GPIO3_GATE>,
985 <&clk IMX93_CLK_GPIO3_GATE>;
986 clock-names = "gpio", "port";
d92a1101
PF		 987 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>,
988 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>;
ec8b5b50
PF		 989 };
990
4af1b258 991 gpio4: gpio@43830000 {
c1d0782b
PF		 992 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
993 reg = <0x43830000 0x1000>;
ec8b5b50
PF		 994 gpio-controller;
995 #gpio-cells = <2>;
c1d0782b
PF		 996 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
ec8b5b50
PF		 998 interrupt-controller;
999 #interrupt-cells = <2>;
e41ba695
PF		 1000 clocks = <&clk IMX93_CLK_GPIO4_GATE>,
1001 <&clk IMX93_CLK_GPIO4_GATE>;
1002 clock-names = "gpio", "port";
d92a1101 1003 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>;
ec8b5b50
PF		 1004 };
1005
4af1b258 1006 gpio1: gpio@47400000 {
c1d0782b
PF		 1007 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio";
1008 reg = <0x47400000 0x1000>;
ec8b5b50
PF		 1009 gpio-controller;
1010 #gpio-cells = <2>;
c1d0782b
PF		 1011 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
1012 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
ec8b5b50
PF		 1013 interrupt-controller;
1014 #interrupt-cells = <2>;
e41ba695
PF		 1015 clocks = <&clk IMX93_CLK_GPIO1_GATE>,
1016 <&clk IMX93_CLK_GPIO1_GATE>;
1017 clock-names = "gpio", "port";
d92a1101 1018 gpio-ranges = <&iomuxc 0 92 16>;
ec8b5b50 1019 };
0dfb380d 1020
5a866baa
PF		 1021 ocotp: efuse@47510000 {
1022 compatible = "fsl,imx93-ocotp", "syscon";
1023 reg = <0x47510000 0x10000>;
1024 #address-cells = <1>;
1025 #size-cells = <1>;
1026 };
1027
0dfb380d
PF		 1028 s4muap: mailbox@47520000 {
1029 compatible = "fsl,imx93-mu-s4";
1030 reg = <0x47520000 0x10000>;
1031 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
1032 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
82ce5919 1033 interrupt-names = "tx", "rx";
0dfb380d
PF		 1034 #mbox-cells = <2>;
1035 };
a90a37bb
PF		 1036
1037 media_blk_ctrl: system-controller@4ac10000 {
1038 compatible = "fsl,imx93-media-blk-ctrl", "syscon";
1039 reg = <0x4ac10000 0x10000>;
1040 power-domains = <&mediamix>;
1041 clocks = <&clk IMX93_CLK_MEDIA_APB>,
1042 <&clk IMX93_CLK_MEDIA_AXI>,
1043 <&clk IMX93_CLK_NIC_MEDIA_GATE>,
1044 <&clk IMX93_CLK_MEDIA_DISP_PIX>,
1045 <&clk IMX93_CLK_CAM_PIX>,
1046 <&clk IMX93_CLK_PXP_GATE>,
1047 <&clk IMX93_CLK_LCDIF_GATE>,
1048 <&clk IMX93_CLK_ISI_GATE>,
1049 <&clk IMX93_CLK_MIPI_CSI_GATE>,
1050 <&clk IMX93_CLK_MIPI_DSI_GATE>;
1051 clock-names = "apb", "axi", "nic", "disp", "cam",
1052 "pxp", "lcdif", "isi", "csi", "dsi";
1053 #power-domain-cells = <1>;
1054 status = "disabled";
1055 };
a6af62dd
XY		 1056
1057 ddr-pmu@4e300dc0 {
1058 compatible = "fsl,imx93-ddr-pmu";
1059 reg = <0x4e300dc0 0x200>;
1060 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1061 };
ec8b5b50
PF		 1062 };
1063};
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git