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Merge tag 'loongarch-kvm-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhu...
[thirdparty/kernel/stable.git] / arch / arm64 / boot / dts / mediatek / mt8195-cherry.dtsi
CommitLineData
5eb2e303
ADR		 1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright (C) 2021 MediaTek Inc.
4 */
5
6#include <dt-bindings/gpio/gpio.h>
260c04d4 7#include <dt-bindings/spmi/spmi.h>
5eb2e303 8#include "mt8195.dtsi"
37242cb9 9#include "mt6359.dtsi"
5eb2e303
ADR		 10
11/ {
12 aliases {
d82b3562
ADR		 13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c7 = &i2c7;
4d380708 20 mmc0 = &mmc0;
07984e82 21 mmc1 = &mmc1;
5eb2e303
ADR		 22 serial0 = &uart0;
23 };
24
ee508454
ADR		 25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
31 pwms = <&disp_pwm0 0 500000>;
32 power-supply = <&ppvar_sys>;
33 };
34
5eb2e303
ADR		 35 chosen {
36 stdout-path = "serial0:115200n8";
37 };
38
4b4e0508
ADR		 39 dmic-codec {
40 compatible = "dmic-codec";
41 num-channels = <2>;
42 wakeup-delay-ms = <50>;
43 };
44
5eb2e303
ADR		 45 memory@40000000 {
46 device_type = "memory";
47 reg = <0 0x40000000 0 0x80000000>;
48 };
37242cb9 49
73a2a319
ADR		 50 pp3300_disp_x: regulator-pp3300-disp-x {
51 compatible = "regulator-fixed";
52 regulator-name = "pp3300_disp_x";
53 regulator-min-microvolt = <3300000>;
54 regulator-max-microvolt = <3300000>;
55 regulator-enable-ramp-delay = <2500>;
56 enable-active-high;
57 gpio = <&pio 55 GPIO_ACTIVE_HIGH>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&panel_fixed_pins>;
60 vin-supply = <&pp3300_z2>;
61 };
62
37242cb9
ADR		 63 /* system wide LDO 3.3V power rail */
64 pp3300_z5: regulator-pp3300-ldo-z5 {
65 compatible = "regulator-fixed";
66 regulator-name = "pp3300_ldo_z5";
67 regulator-always-on;
68 regulator-boot-on;
69 regulator-min-microvolt = <3300000>;
70 regulator-max-microvolt = <3300000>;
71 vin-supply = <&ppvar_sys>;
72 };
73
74 /* separately switched 3.3V power rail */
75 pp3300_s3: regulator-pp3300-s3 {
76 compatible = "regulator-fixed";
77 regulator-name = "pp3300_s3";
78 /* automatically sequenced by PMIC EXT_PMIC_EN2 */
79 regulator-always-on;
80 regulator-boot-on;
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 vin-supply = <&pp3300_z2>;
84 };
85
86 /* system wide 3.3V power rail */
87 pp3300_z2: regulator-pp3300-z2 {
88 compatible = "regulator-fixed";
89 regulator-name = "pp3300_z2";
90 /* EN pin tied to pp4200_z2, which is controlled by EC */
91 regulator-always-on;
92 regulator-boot-on;
93 regulator-min-microvolt = <3300000>;
94 regulator-max-microvolt = <3300000>;
95 vin-supply = <&ppvar_sys>;
96 };
97
98 /* system wide 4.2V power rail */
99 pp4200_z2: regulator-pp4200-z2 {
100 compatible = "regulator-fixed";
101 regulator-name = "pp4200_z2";
102 /* controlled by EC */
103 regulator-always-on;
104 regulator-boot-on;
105 regulator-min-microvolt = <4200000>;
106 regulator-max-microvolt = <4200000>;
107 vin-supply = <&ppvar_sys>;
108 };
109
110 /* system wide switching 5.0V power rail */
111 pp5000_s5: regulator-pp5000-s5 {
112 compatible = "regulator-fixed";
113 regulator-name = "pp5000_s5";
114 /* controlled by EC */
115 regulator-always-on;
116 regulator-boot-on;
117 regulator-min-microvolt = <5000000>;
118 regulator-max-microvolt = <5000000>;
119 vin-supply = <&ppvar_sys>;
120 };
121
122 /* system wide semi-regulated power rail from battery or USB */
123 ppvar_sys: regulator-ppvar-sys {
124 compatible = "regulator-fixed";
125 regulator-name = "ppvar_sys";
126 regulator-always-on;
127 regulator-boot-on;
128 };
b6267a39
ADR		 129
130 usb_vbus: regulator-5v0-usb-vbus {
131 compatible = "regulator-fixed";
132 regulator-name = "usb-vbus";
133 regulator-min-microvolt = <5000000>;
134 regulator-max-microvolt = <5000000>;
135 enable-active-high;
136 regulator-always-on;
137 };
d86a1c69
ADR		 138
139 reserved_memory: reserved-memory {
140 #address-cells = <2>;
141 #size-cells = <2>;
142 ranges;
143
144 scp_mem: memory@50000000 {
145 compatible = "shared-dma-pool";
146 reg = <0 0x50000000 0 0x2900000>;
147 no-map;
148 };
84af4359 149
b26de6b6
ADR		 150 adsp_mem: memory@60000000 {
151 compatible = "shared-dma-pool";
152 reg = <0 0x60000000 0 0xd80000>;
153 no-map;
154 };
155
84af4359
ADR		 156 afe_mem: memory@60d80000 {
157 compatible = "shared-dma-pool";
158 reg = <0 0x60d80000 0 0x100000>;
159 no-map;
160 };
b26de6b6
ADR		 161
162 adsp_device_mem: memory@60e80000 {
163 compatible = "shared-dma-pool";
164 reg = <0 0x60e80000 0 0x280000>;
165 no-map;
166 };
d86a1c69 167 };
4b4e0508
ADR		 168
169 spk_amplifier: rt1019p {
170 compatible = "realtek,rt1019p";
171 label = "rt1019p";
172 pinctrl-names = "default";
173 pinctrl-0 = <&rt1019p_pins_default>;
174 sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>;
175 };
37242cb9
ADR		 176};
177
b26de6b6
ADR		 178&adsp {
179 status = "okay";
180
181 memory-region = <&adsp_device_mem>, <&adsp_mem>;
182};
183
84af4359
ADR		 184&afe {
185 status = "okay";
186
187 mediatek,etdm-in2-cowork-source = <2>;
188 mediatek,etdm-out2-cowork-source = <0>;
189 memory-region = <&afe_mem>;
190};
191
b1bf5570
BCC		 192&dp_intf0 {
193 status = "okay";
194
195 port {
196 dp_intf0_out: endpoint {
957d4ac7 197 remote-endpoint = <&edp_in>;
b1bf5570
BCC		 198 };
199 };
200};
201
202&dp_intf1 {
203 status = "okay";
204
205 port {
206 dp_intf1_out: endpoint {
957d4ac7
BCC		 207 remote-endpoint = <&dptx_in>;
208 };
209 };
210};
211
212&edp_tx {
213 status = "okay";
214
215 pinctrl-names = "default";
216 pinctrl-0 = <&edptx_pins_default>;
217
218 ports {
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 port@0 {
223 reg = <0>;
224 edp_in: endpoint {
225 remote-endpoint = <&dp_intf0_out>;
226 };
227 };
228
229 port@1 {
230 reg = <1>;
231 edp_out: endpoint {
232 data-lanes = <0 1 2 3>;
73a2a319
ADR		 233 remote-endpoint = <&panel_in>;
234 };
235 };
236 };
237
238 aux-bus {
239 panel {
240 compatible = "edp-panel";
241 power-supply = <&pp3300_disp_x>;
242 backlight = <&backlight_lcd0>;
243 port {
244 panel_in: endpoint {
245 remote-endpoint = <&edp_out>;
246 };
957d4ac7
BCC		 247 };
248 };
249 };
250};
251
ee508454
ADR		 252&disp_pwm0 {
253 status = "okay";
254
255 pinctrl-names = "default";
256 pinctrl-0 = <&disp_pwm0_pin_default>;
257};
258
957d4ac7
BCC		 259&dp_tx {
260 status = "okay";
261
262 pinctrl-names = "default";
263 pinctrl-0 = <&dptx_pin>;
264
265 ports {
266 #address-cells = <1>;
267 #size-cells = <0>;
268
269 port@0 {
270 reg = <0>;
271 dptx_in: endpoint {
272 remote-endpoint = <&dp_intf1_out>;
273 };
274 };
275
276 port@1 {
277 reg = <1>;
278 dptx_out: endpoint {
279 data-lanes = <0 1 2 3>;
280 };
b1bf5570
BCC		 281 };
282 };
283};
284
ea6c5f21
DA		 285&gic {
286 mediatek,broken-save-restore-fw;
287};
288
673f8b60
ADR		 289&gpu {
290 status = "okay";
291 mali-supply = <&mt6315_7_vbuck1>;
292};
293
d82b3562
ADR		 294&i2c0 {
295 status = "okay";
296
297 clock-frequency = <400000>;
298 pinctrl-names = "default";
299 pinctrl-0 = <&i2c0_pins>;
300};
301
302&i2c1 {
303 status = "okay";
304
305 clock-frequency = <400000>;
306 i2c-scl-internal-delay-ns = <12500>;
307 pinctrl-names = "default";
308 pinctrl-0 = <&i2c1_pins>;
b53f3724
ADR		 309
310 trackpad@15 {
311 compatible = "elan,ekth3000";
312 reg = <0x15>;
313 interrupts-extended = <&pio 6 IRQ_TYPE_LEVEL_LOW>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&trackpad_pins>;
316 vcc-supply = <&pp3300_s3>;
317 wakeup-source;
318 };
d82b3562
ADR		 319};
320
321&i2c2 {
322 status = "okay";
323
324 clock-frequency = <400000>;
325 pinctrl-names = "default";
326 pinctrl-0 = <&i2c2_pins>;
4b4e0508
ADR		 327
328 audio_codec: codec@1a {
329 /* Realtek RT5682i or RT5682s, sharing the same configuration */
330 reg = <0x1a>;
331 interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>;
332 realtek,jd-src = <1>;
333
334 AVDD-supply = <&mt6359_vio18_ldo_reg>;
335 MICVDD-supply = <&pp3300_z2>;
336 VBAT-supply = <&pp3300_z5>;
337 };
d82b3562
ADR		 338};
339
340&i2c3 {
341 status = "okay";
342
343 clock-frequency = <400000>;
344 pinctrl-names = "default";
345 pinctrl-0 = <&i2c3_pins>;
63ce81b2
ADR		 346
347 tpm@50 {
348 compatible = "google,cr50";
349 reg = <0x50>;
350 interrupts-extended = <&pio 88 IRQ_TYPE_EDGE_FALLING>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&cr50_int>;
353 };
d82b3562
ADR		 354};
355
356&i2c4 {
357 status = "okay";
358
359 clock-frequency = <400000>;
360 pinctrl-names = "default";
361 pinctrl-0 = <&i2c4_pins>;
10d4a706
ADR		 362
363 ts_10: touchscreen@10 {
364 compatible = "hid-over-i2c";
365 reg = <0x10>;
366 hid-descr-addr = <0x0001>;
367 interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>;
368 pinctrl-names = "default";
369 pinctrl-0 = <&touchscreen_pins>;
370 post-power-on-delay-ms = <10>;
371 vdd-supply = <&pp3300_s3>;
372 status = "disabled";
373 };
d82b3562
ADR		 374};
375
376&i2c5 {
377 status = "okay";
378
379 clock-frequency = <400000>;
380 pinctrl-names = "default";
381 pinctrl-0 = <&i2c5_pins>;
382};
383
384&i2c7 {
385 status = "okay";
386
387 clock-frequency = <400000>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&i2c7_pins>;
0de0fe95
ADR		 390
391 pmic@34 {
5943b8f7 392 #interrupt-cells = <2>;
0de0fe95
ADR		 393 compatible = "mediatek,mt6360";
394 reg = <0x34>;
395 interrupt-controller;
396 interrupts-extended = <&pio 130 IRQ_TYPE_EDGE_FALLING>;
397 interrupt-names = "IRQB";
398 pinctrl-names = "default";
399 pinctrl-0 = <&subpmic_default>;
400 wakeup-source;
401 };
d82b3562
ADR		 402};
403
4d380708
ADR		 404&mmc0 {
405 status = "okay";
406
407 bus-width = <8>;
408 cap-mmc-highspeed;
409 cap-mmc-hw-reset;
410 hs400-ds-delay = <0x14c11>;
411 max-frequency = <200000000>;
412 mmc-hs200-1_8v;
413 mmc-hs400-1_8v;
414 no-sdio;
415 no-sd;
416 non-removable;
417 pinctrl-names = "default", "state_uhs";
418 pinctrl-0 = <&mmc0_pins_default>;
419 pinctrl-1 = <&mmc0_pins_uhs>;
420 vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
421 vqmmc-supply = <&mt6359_vufs_ldo_reg>;
422};
423
07984e82
ADR		 424&mmc1 {
425 status = "okay";
426
427 bus-width = <4>;
428 cap-sd-highspeed;
429 cd-gpios = <&pio 54 GPIO_ACTIVE_LOW>;
430 max-frequency = <200000000>;
431 no-mmc;
432 no-sdio;
433 pinctrl-names = "default", "state_uhs";
434 pinctrl-0 = <&mmc1_pins_default>, <&mmc1_pins_detect>;
435 pinctrl-1 = <&mmc1_pins_default>;
436 sd-uhs-sdr50;
437 sd-uhs-sdr104;
438 vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
439 vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
440};
441
4b4e0508
ADR		 442&mt6359codec {
443 mediatek,dmic-mode = <1>; /* one-wire */
444 mediatek,mic-type-0 = <2>; /* DMIC */
445};
446
37242cb9
ADR		 447/* for CPU-L */
448&mt6359_vcore_buck_reg {
449 regulator-always-on;
450};
451
452/* for CORE */
453&mt6359_vgpu11_buck_reg {
454 regulator-always-on;
455};
456
457&mt6359_vgpu11_sshub_buck_reg {
458 regulator-always-on;
459 regulator-min-microvolt = <550000>;
460 regulator-max-microvolt = <550000>;
461};
462
463/* for CORE SRAM */
464&mt6359_vpu_buck_reg {
465 regulator-always-on;
466};
467
468&mt6359_vrf12_ldo_reg {
469 regulator-always-on;
470};
471
472/* for GPU SRAM */
473&mt6359_vsram_others_ldo_reg {
474 regulator-always-on;
475 regulator-min-microvolt = <750000>;
476 regulator-max-microvolt = <750000>;
477};
478
479&mt6359_vufs_ldo_reg {
480 regulator-always-on;
5eb2e303
ADR		 481};
482
c34bc660
ADR		 483&nor_flash {
484 status = "okay";
485
486 pinctrl-names = "default";
487 pinctrl-0 = <&nor_pins_default>;
488
489 flash@0 {
490 compatible = "jedec,spi-nor";
491 reg = <0>;
492 spi-max-frequency = <52000000>;
493 spi-rx-bus-width = <2>;
494 spi-tx-bus-width = <2>;
495 };
496};
497
58d7dae8
ADR		 498&pcie1 {
499 status = "okay";
500
501 pinctrl-names = "default";
502 pinctrl-0 = <&pcie1_pins_default>;
503};
504
4d380708 505&pio {
5bf7dabe
ADR		 506 mediatek,rsel-resistance-in-si-unit;
507 pinctrl-names = "default";
508 pinctrl-0 = <&pio_default>;
509
510 /* 144 lines */
511 gpio-line-names =
512 "I2S_SPKR_MCLK",
513 "I2S_SPKR_DATAIN",
514 "I2S_SPKR_LRCK",
515 "I2S_SPKR_BCLK",
516 "EC_AP_INT_ODL",
517 /*
518 * AP_FLASH_WP_L is crossystem ABI. Schematics
519 * call it AP_FLASH_WP_ODL.
520 */
521 "AP_FLASH_WP_L",
522 "TCHPAD_INT_ODL",
523 "EDP_HPD_1V8",
524 "AP_I2C_CAM_SDA",
525 "AP_I2C_CAM_SCL",
526 "AP_I2C_TCHPAD_SDA_1V8",
527 "AP_I2C_TCHPAD_SCL_1V8",
528 "AP_I2C_AUD_SDA",
529 "AP_I2C_AUD_SCL",
530 "AP_I2C_TPM_SDA_1V8",
531 "AP_I2C_TPM_SCL_1V8",
532 "AP_I2C_TCHSCR_SDA_1V8",
533 "AP_I2C_TCHSCR_SCL_1V8",
534 "EC_AP_HPD_OD",
535 "",
536 "PCIE_NVME_RST_L",
537 "PCIE_NVME_CLKREQ_ODL",
538 "PCIE_RST_1V8_L",
539 "PCIE_CLKREQ_1V8_ODL",
540 "PCIE_WAKE_1V8_ODL",
541 "CLK_24M_CAM0",
542 "CAM1_SEN_EN",
543 "AP_I2C_PWR_SCL_1V8",
544 "AP_I2C_PWR_SDA_1V8",
545 "AP_I2C_MISC_SCL",
546 "AP_I2C_MISC_SDA",
547 "EN_PP5000_HDMI_X",
548 "AP_HDMITX_HTPLG",
549 "",
550 "AP_HDMITX_SCL_1V8",
551 "AP_HDMITX_SDA_1V8",
552 "AP_RTC_CLK32K",
553 "AP_EC_WATCHDOG_L",
554 "SRCLKENA0",
555 "SRCLKENA1",
556 "PWRAP_SPI0_CS_L",
557 "PWRAP_SPI0_CK",
558 "PWRAP_SPI0_MOSI",
559 "PWRAP_SPI0_MISO",
560 "SPMI_SCL",
561 "SPMI_SDA",
562 "",
563 "",
564 "",
565 "I2S_HP_DATAIN",
566 "I2S_HP_MCLK",
567 "I2S_HP_BCK",
568 "I2S_HP_LRCK",
569 "I2S_HP_DATAOUT",
570 "SD_CD_ODL",
571 "EN_PP3300_DISP_X",
572 "TCHSCR_RST_1V8_L",
573 "TCHSCR_REPORT_DISABLE",
574 "EN_PP3300_WLAN_X",
575 "BT_KILL_1V8_L",
576 "I2S_SPKR_DATAOUT",
577 "WIFI_KILL_1V8_L",
578 "BEEP_ON",
579 "SCP_I2C_SENSOR_SCL_1V8",
580 "SCP_I2C_SENSOR_SDA_1V8",
581 "",
582 "",
583 "",
584 "",
585 "AUD_CLK_MOSI",
586 "AUD_SYNC_MOSI",
587 "AUD_DAT_MOSI0",
588 "AUD_DAT_MOSI1",
589 "AUD_DAT_MISO0",
590 "AUD_DAT_MISO1",
591 "AUD_DAT_MISO2",
592 "SCP_VREQ_VAO",
593 "AP_SPI_GSC_TPM_CLK",
594 "AP_SPI_GSC_TPM_MOSI",
595 "AP_SPI_GSC_TPM_CS_L",
596 "AP_SPI_GSC_TPM_MISO",
597 "EN_PP1000_CAM_X",
598 "AP_EDP_BKLTEN",
599 "",
600 "USB3_HUB_RST_L",
601 "",
602 "WLAN_ALERT_ODL",
603 "EC_IN_RW_ODL",
604 "GSC_AP_INT_ODL",
605 "HP_INT_ODL",
606 "CAM0_RST_L",
607 "CAM1_RST_L",
608 "TCHSCR_INT_1V8_L",
609 "CAM1_DET_L",
610 "RST_ALC1011_L",
611 "",
612 "",
613 "BL_PWM_1V8",
614 "UART_AP_TX_DBG_RX",
615 "UART_DBG_TX_AP_RX",
616 "EN_SPKR",
617 "AP_EC_WARM_RST_REQ",
618 "UART_SCP_TX_DBGCON_RX",
619 "UART_DBGCON_TX_SCP_RX",
620 "",
621 "",
622 "KPCOL0",
623 "",
624 "MT6315_GPU_INT",
625 "MT6315_PROC_BC_INT",
626 "SD_CMD",
627 "SD_CLK",
628 "SD_DAT0",
629 "SD_DAT1",
630 "SD_DAT2",
631 "SD_DAT3",
632 "EMMC_DAT7",
633 "EMMC_DAT6",
634 "EMMC_DAT5",
635 "EMMC_DAT4",
636 "EMMC_RSTB",
637 "EMMC_CMD",
638 "EMMC_CLK",
639 "EMMC_DAT3",
640 "EMMC_DAT2",
641 "EMMC_DAT1",
642 "EMMC_DAT0",
643 "EMMC_DSL",
644 "",
645 "",
646 "MT6360_INT_ODL",
647 "SCP_JTAG0_TRSTN",
648 "AP_SPI_EC_CS_L",
649 "AP_SPI_EC_CLK",
650 "AP_SPI_EC_MOSI",
651 "AP_SPI_EC_MISO",
652 "SCP_JTAG0_TMS",
653 "SCP_JTAG0_TCK",
654 "SCP_JTAG0_TDO",
655 "SCP_JTAG0_TDI",
656 "AP_SPI_FLASH_CS_L",
657 "AP_SPI_FLASH_CLK",
658 "AP_SPI_FLASH_MOSI",
659 "AP_SPI_FLASH_MISO";
660
6d886dd4
ADR		 661 aud_pins_default: audio-default-pins {
662 pins-cmd-dat {
663 pinmux = <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
664 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
665 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
666 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
667 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
668 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
669 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>,
670 <PINMUX_GPIO0__FUNC_TDMIN_MCK>,
671 <PINMUX_GPIO1__FUNC_TDMIN_DI>,
672 <PINMUX_GPIO2__FUNC_TDMIN_LRCK>,
673 <PINMUX_GPIO3__FUNC_TDMIN_BCK>,
674 <PINMUX_GPIO60__FUNC_I2SO2_D0>,
675 <PINMUX_GPIO49__FUNC_I2SIN_D0>,
676 <PINMUX_GPIO50__FUNC_I2SO1_MCK>,
677 <PINMUX_GPIO51__FUNC_I2SO1_BCK>,
678 <PINMUX_GPIO52__FUNC_I2SO1_WS>,
679 <PINMUX_GPIO53__FUNC_I2SO1_D0>;
680 };
681
682 pins-hp-jack-int-odl {
683 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>;
684 input-enable;
685 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
686 };
687 };
688
63ce81b2
ADR		 689 cr50_int: cr50-irq-default-pins {
690 pins-gsc-ap-int-odl {
691 pinmux = <PINMUX_GPIO88__FUNC_GPIO88>;
692 input-enable;
693 };
694 };
695
e775cc1a
ADR		 696 cros_ec_int: cros-ec-irq-default-pins {
697 pins-ec-ap-int-odl {
698 pinmux = <PINMUX_GPIO4__FUNC_GPIO4>;
699 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
700 input-enable;
701 };
702 };
703
957d4ac7
BCC		 704 edptx_pins_default: edptx-default-pins {
705 pins-cmd-dat {
706 pinmux = <PINMUX_GPIO7__FUNC_EDP_TX_HPD>;
707 bias-pull-up;
708 };
709 };
710
ee508454
ADR		 711 disp_pwm0_pin_default: disp-pwm0-default-pins {
712 pins-disp-pwm {
713 pinmux = <PINMUX_GPIO82__FUNC_GPIO82>,
714 <PINMUX_GPIO97__FUNC_DISP_PWM0>;
715 };
716 };
717
957d4ac7
BCC		 718 dptx_pin: dptx-default-pins {
719 pins-cmd-dat {
720 pinmux = <PINMUX_GPIO18__FUNC_DP_TX_HPD>;
721 bias-pull-up;
722 };
723 };
724
d82b3562
ADR		 725 i2c0_pins: i2c0-default-pins {
726 pins-bus {
727 pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
728 <PINMUX_GPIO9__FUNC_SCL0>;
729 bias-disable;
730 drive-strength-microamp = <1000>;
731 };
732 };
733
734 i2c1_pins: i2c1-default-pins {
735 pins-bus {
736 pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
737 <PINMUX_GPIO11__FUNC_SCL1>;
738 bias-pull-up = <1000>;
739 drive-strength-microamp = <1000>;
740 };
741 };
742
743 i2c2_pins: i2c2-default-pins {
744 pins-bus {
745 pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
746 <PINMUX_GPIO13__FUNC_SCL2>;
747 bias-disable;
748 drive-strength-microamp = <1000>;
749 };
750 };
751
752 i2c3_pins: i2c3-default-pins {
753 pins-bus {
754 pinmux = <PINMUX_GPIO14__FUNC_SDA3>,
755 <PINMUX_GPIO15__FUNC_SCL3>;
756 bias-pull-up = <1000>;
757 drive-strength-microamp = <1000>;
758 };
759 };
760
761 i2c4_pins: i2c4-default-pins {
762 pins-bus {
763 pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
764 <PINMUX_GPIO17__FUNC_SCL4>;
765 bias-pull-up = <1000>;
766 drive-strength = <4>;
767 };
768 };
769
770 i2c5_pins: i2c5-default-pins {
771 pins-bus {
772 pinmux = <PINMUX_GPIO29__FUNC_SCL5>,
773 <PINMUX_GPIO30__FUNC_SDA5>;
774 bias-disable;
775 drive-strength-microamp = <1000>;
776 };
777 };
778
779 i2c7_pins: i2c7-default-pins {
780 pins-bus {
781 pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
782 <PINMUX_GPIO28__FUNC_SDA7>;
783 bias-disable;
784 };
785 };
786
4d380708
ADR		 787 mmc0_pins_default: mmc0-default-pins {
788 pins-cmd-dat {
789 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
790 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
791 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
792 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
793 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
794 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
795 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
796 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
797 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
798 input-enable;
799 drive-strength = <6>;
800 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
801 };
802
803 pins-clk {
804 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
805 drive-strength = <6>;
806 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
807 };
808
809 pins-rst {
810 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
811 drive-strength = <6>;
812 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
813 };
814 };
815
816 mmc0_pins_uhs: mmc0-uhs-pins {
817 pins-cmd-dat {
818 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
819 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
820 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
821 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
822 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
823 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
824 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
825 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
826 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
827 input-enable;
828 drive-strength = <8>;
829 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
830 };
831
832 pins-clk {
833 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
834 drive-strength = <8>;
835 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
836 };
837
838 pins-ds {
839 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
840 drive-strength = <8>;
841 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
842 };
843
844 pins-rst {
845 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
846 drive-strength = <8>;
847 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
848 };
849 };
5bf7dabe 850
07984e82
ADR		 851 mmc1_pins_detect: mmc1-detect-pins {
852 pins-insert {
853 pinmux = <PINMUX_GPIO54__FUNC_GPIO54>;
854 bias-pull-up;
855 };
856 };
857
858 mmc1_pins_default: mmc1-default-pins {
859 pins-cmd-dat {
860 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
861 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
862 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
863 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
864 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
865 input-enable;
866 drive-strength = <8>;
867 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
868 };
869
870 pins-clk {
871 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
872 drive-strength = <8>;
873 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
874 };
875 };
876
c34bc660
ADR		 877 nor_pins_default: nor-default-pins {
878 pins-ck-io {
879 pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
880 <PINMUX_GPIO141__FUNC_SPINOR_CK>,
881 <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
882 drive-strength = <6>;
883 bias-pull-down;
884 };
885
886 pins-cs {
887 pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>;
888 drive-strength = <6>;
889 bias-pull-up;
890 };
891 };
892
58d7dae8
ADR		 893 pcie0_pins_default: pcie0-default-pins {
894 pins-bus {
895 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
896 <PINMUX_GPIO20__FUNC_PERSTN>,
897 <PINMUX_GPIO21__FUNC_CLKREQN>;
898 bias-pull-up;
899 };
900 };
901
902 pcie1_pins_default: pcie1-default-pins {
903 pins-bus {
904 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
905 <PINMUX_GPIO23__FUNC_CLKREQN_1>,
906 <PINMUX_GPIO24__FUNC_WAKEN_1>;
907 bias-pull-up;
908 };
909 };
910
73a2a319
ADR		 911 panel_fixed_pins: panel-pwr-default-pins {
912 pins-vreg-en {
913 pinmux = <PINMUX_GPIO55__FUNC_GPIO55>;
914 };
915 };
916
5bf7dabe
ADR		 917 pio_default: pio-default-pins {
918 pins-wifi-enable {
919 pinmux = <PINMUX_GPIO58__FUNC_GPIO58>;
920 output-high;
921 drive-strength = <14>;
922 };
923
924 pins-low-power-pd {
925 pinmux = <PINMUX_GPIO25__FUNC_GPIO25>,
926 <PINMUX_GPIO26__FUNC_GPIO26>,
927 <PINMUX_GPIO46__FUNC_GPIO46>,
928 <PINMUX_GPIO47__FUNC_GPIO47>,
929 <PINMUX_GPIO48__FUNC_GPIO48>,
930 <PINMUX_GPIO65__FUNC_GPIO65>,
931 <PINMUX_GPIO66__FUNC_GPIO66>,
932 <PINMUX_GPIO67__FUNC_GPIO67>,
933 <PINMUX_GPIO68__FUNC_GPIO68>,
934 <PINMUX_GPIO128__FUNC_GPIO128>,
935 <PINMUX_GPIO129__FUNC_GPIO129>;
936 input-enable;
937 bias-pull-down;
938 };
939
940 pins-low-power-pupd {
941 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
942 <PINMUX_GPIO78__FUNC_GPIO78>,
943 <PINMUX_GPIO79__FUNC_GPIO79>,
944 <PINMUX_GPIO80__FUNC_GPIO80>,
945 <PINMUX_GPIO83__FUNC_GPIO83>,
946 <PINMUX_GPIO85__FUNC_GPIO85>,
947 <PINMUX_GPIO90__FUNC_GPIO90>,
948 <PINMUX_GPIO91__FUNC_GPIO91>,
949 <PINMUX_GPIO93__FUNC_GPIO93>,
950 <PINMUX_GPIO94__FUNC_GPIO94>,
951 <PINMUX_GPIO95__FUNC_GPIO95>,
952 <PINMUX_GPIO96__FUNC_GPIO96>,
953 <PINMUX_GPIO104__FUNC_GPIO104>,
954 <PINMUX_GPIO105__FUNC_GPIO105>,
955 <PINMUX_GPIO107__FUNC_GPIO107>;
956 input-enable;
957 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
958 };
959 };
d82b3562 960
4b4e0508
ADR		 961 rt1019p_pins_default: rt1019p-default-pins {
962 pins-amp-sdb {
963 pinmux = <PINMUX_GPIO100__FUNC_GPIO100>;
964 output-low;
965 };
966 };
967
d86a1c69
ADR		 968 scp_pins: scp-default-pins {
969 pins-vreq {
970 pinmux = <PINMUX_GPIO76__FUNC_SCP_VREQ_VAO>;
971 bias-disable;
972 input-enable;
973 };
974 };
975
d82b3562
ADR		 976 spi0_pins: spi0-default-pins {
977 pins-cs-mosi-clk {
978 pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>,
979 <PINMUX_GPIO134__FUNC_SPIM0_MO>,
980 <PINMUX_GPIO133__FUNC_SPIM0_CLK>;
981 bias-disable;
982 };
983
984 pins-miso {
985 pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>;
986 bias-pull-down;
987 };
988 };
0de0fe95
ADR		 989
990 subpmic_default: subpmic-default-pins {
991 subpmic_pin_irq: pins-subpmic-int-n {
992 pinmux = <PINMUX_GPIO130__FUNC_GPIO130>;
993 input-enable;
994 bias-pull-up;
995 };
996 };
10d4a706 997
b53f3724
ADR		 998 trackpad_pins: trackpad-default-pins {
999 pins-int-n {
1000 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
1001 input-enable;
1002 bias-pull-up;
1003 };
1004 };
1005
10d4a706
ADR		 1006 touchscreen_pins: touchscreen-default-pins {
1007 pins-int-n {
1008 pinmux = <PINMUX_GPIO92__FUNC_GPIO92>;
1009 input-enable;
1010 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1011 };
1012 pins-rst {
1013 pinmux = <PINMUX_GPIO56__FUNC_GPIO56>;
1014 output-high;
1015 };
1016 pins-report-sw {
1017 pinmux = <PINMUX_GPIO57__FUNC_GPIO57>;
1018 output-low;
1019 };
1020 };
4d380708
ADR		 1021};
1022
9e056506
ADR		 1023&pmic {
1024 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
1025};
1026
d86a1c69
ADR		 1027&scp {
1028 status = "okay";
1029
1030 firmware-name = "mediatek/mt8195/scp.img";
1031 memory-region = <&scp_mem>;
1032 pinctrl-names = "default";
1033 pinctrl-0 = <&scp_pins>;
e775cc1a
ADR		 1034
1035 cros-ec-rpmsg {
1036 compatible = "google,cros-ec-rpmsg";
1037 mediatek,rpmsg-name = "cros-ec-rpmsg";
1038 };
d86a1c69
ADR		 1039};
1040
6d886dd4
ADR		 1041&sound {
1042 status = "okay";
1043
1044 mediatek,adsp = <&adsp>;
1045 mediatek,dai-link =
1046 "DL10_FE", "DPTX_BE", "ETDM1_IN_BE", "ETDM2_IN_BE",
1047 "ETDM1_OUT_BE", "ETDM2_OUT_BE","UL_SRC1_BE",
1048 "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5";
1049 pinctrl-names = "default";
1050 pinctrl-0 = <&aud_pins_default>;
1051};
1052
d82b3562
ADR		 1053&spi0 {
1054 status = "okay";
1055
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&spi0_pins>;
1058 mediatek,pad-select = <0>;
e775cc1a
ADR		 1059
1060 cros_ec: ec@0 {
1061 #address-cells = <1>;
1062 #size-cells = <0>;
1063
1064 compatible = "google,cros-ec-spi";
1065 reg = <0>;
1066 interrupts-extended = <&pio 4 IRQ_TYPE_LEVEL_LOW>;
1067 pinctrl-names = "default";
1068 pinctrl-0 = <&cros_ec_int>;
1069 spi-max-frequency = <3000000>;
1070
1071 keyboard-backlight {
1072 compatible = "google,cros-kbd-led-backlight";
1073 };
1074
1075 i2c_tunnel: i2c-tunnel {
1076 compatible = "google,cros-ec-i2c-tunnel";
1077 google,remote-bus = <0>;
1078 #address-cells = <1>;
1079 #size-cells = <0>;
1080 };
1081
1082 mt_pmic_vmc_ldo_reg: regulator@0 {
1083 compatible = "google,cros-ec-regulator";
1084 reg = <0>;
1085 regulator-name = "mt_pmic_vmc_ldo";
1086 regulator-min-microvolt = <1200000>;
1087 regulator-max-microvolt = <3600000>;
1088 };
1089
1090 mt_pmic_vmch_ldo_reg: regulator@1 {
1091 compatible = "google,cros-ec-regulator";
1092 reg = <1>;
1093 regulator-name = "mt_pmic_vmch_ldo";
1094 regulator-min-microvolt = <2700000>;
1095 regulator-max-microvolt = <3600000>;
1096 };
1097
1098 typec {
1099 compatible = "google,cros-ec-typec";
1100 #address-cells = <1>;
1101 #size-cells = <0>;
1102
1103 usb_c0: connector@0 {
1104 compatible = "usb-c-connector";
1105 reg = <0>;
1106 power-role = "dual";
1107 data-role = "host";
1108 try-power-role = "source";
1109 };
1110
1111 usb_c1: connector@1 {
1112 compatible = "usb-c-connector";
1113 reg = <1>;
1114 power-role = "dual";
1115 data-role = "host";
1116 try-power-role = "source";
1117 };
1118 };
1119 };
d82b3562
ADR		 1120};
1121
260c04d4
ADR		 1122&spmi {
1123 #address-cells = <2>;
1124 #size-cells = <0>;
1125
1126 mt6315@6 {
1127 compatible = "mediatek,mt6315-regulator";
1128 reg = <0x6 SPMI_USID>;
1129
1130 regulators {
1131 mt6315_6_vbuck1: vbuck1 {
1132 regulator-compatible = "vbuck1";
1133 regulator-name = "Vbcpu";
1134 regulator-min-microvolt = <300000>;
1135 regulator-max-microvolt = <1193750>;
1136 regulator-enable-ramp-delay = <256>;
1137 regulator-ramp-delay = <6250>;
1138 regulator-allowed-modes = <0 1 2>;
1139 regulator-always-on;
1140 };
1141 };
1142 };
1143
1144 mt6315@7 {
1145 compatible = "mediatek,mt6315-regulator";
1146 reg = <0x7 SPMI_USID>;
1147
1148 regulators {
1149 mt6315_7_vbuck1: vbuck1 {
1150 regulator-compatible = "vbuck1";
1151 regulator-name = "Vgpu";
1152 regulator-min-microvolt = <625000>;
1153 regulator-max-microvolt = <1193750>;
1154 regulator-enable-ramp-delay = <256>;
1155 regulator-ramp-delay = <6250>;
1156 regulator-allowed-modes = <0 1 2>;
1157 regulator-always-on;
1158 };
1159 };
1160 };
1161};
1162
b6267a39
ADR		 1163&u3phy0 {
1164 status = "okay";
1165};
1166
1167&u3phy1 {
1168 status = "okay";
1169};
1170
1171&u3phy2 {
1172 status = "okay";
1173};
1174
1175&u3phy3 {
1176 status = "okay";
1177};
1178
5eb2e303
ADR		 1179&uart0 {
1180 status = "okay";
1181};
b6267a39
ADR		 1182
1183&xhci0 {
1184 status = "okay";
1185
1186 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1187 vbus-supply = <&usb_vbus>;
1188};
1189
1190&xhci1 {
1191 status = "okay";
1192
1193 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1194 vbus-supply = <&usb_vbus>;
1195};
1196
1197&xhci2 {
1198 status = "okay";
1199
1200 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1201 vbus-supply = <&usb_vbus>;
1202};
1203
1204&xhci3 {
1205 status = "okay";
1206
1207 /* MT7921's USB Bluetooth has issues with USB2 LPM */
1208 usb2-lpm-disable;
1209 vusb33-supply = <&mt6359_vusb_ldo_reg>;
1210 vbus-supply = <&usb_vbus>;
1211};
e775cc1a
ADR		 1212
1213#include <arm/cros-ec-keyboard.dtsi>
1214#include <arm/cros-ec-sbs.dtsi>
824fae69
ADR		 1215
1216&keyboard_controller {
1217 function-row-physmap = <
1218 MATRIX_KEY(0x00, 0x02, 0) /* T1 */
1219 MATRIX_KEY(0x03, 0x02, 0) /* T2 */
1220 MATRIX_KEY(0x02, 0x02, 0) /* T3 */
1221 MATRIX_KEY(0x01, 0x02, 0) /* T4 */
1222 MATRIX_KEY(0x03, 0x04, 0) /* T5 */
1223 MATRIX_KEY(0x02, 0x04, 0) /* T6 */
1224 MATRIX_KEY(0x01, 0x04, 0) /* T7 */
1225 MATRIX_KEY(0x02, 0x09, 0) /* T8 */
1226 MATRIX_KEY(0x01, 0x09, 0) /* T9 */
1227 MATRIX_KEY(0x00, 0x04, 0) /* T10 */
1228 >;
1229
1230 linux,keymap = <
1231 MATRIX_KEY(0x00, 0x02, KEY_BACK)
1232 MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
1233 MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
1234 MATRIX_KEY(0x01, 0x02, KEY_SCALE)
1235 MATRIX_KEY(0x03, 0x04, KEY_SYSRQ)
1236 MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN)
1237 MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP)
1238 MATRIX_KEY(0x02, 0x09, KEY_MUTE)
1239 MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
1240 MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
1241
1242 CROS_STD_MAIN_KEYMAP
1243 >;
1244};
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git