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Commit | Line | Data |
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b2441318 | 1 | // SPDX-License-Identifier: GPL-2.0 |
5d17ba6e JH |
2 | /dts-v1/; |
3 | ||
a26f3963 | 4 | #include <dt-bindings/input/input.h> |
1b4c8420 | 5 | #include <dt-bindings/mfd/max77620.h> |
c1fd85b4 | 6 | #include <dt-bindings/pinctrl/pinctrl-tegra.h> |
a26f3963 | 7 | |
5d17ba6e JH |
8 | #include "tegra210.dtsi" |
9 | ||
10 | / { | |
11 | model = "Google Pixel C"; | |
12 | compatible = "google,smaug-rev8", "google,smaug-rev7", | |
13 | "google,smaug-rev6", "google,smaug-rev5", | |
14 | "google,smaug-rev4", "google,smaug-rev3", | |
816c60c1 AC |
15 | "google,smaug-rev2", "google,smaug-rev1", |
16 | "google,smaug", "nvidia,tegra210"; | |
5d17ba6e JH |
17 | |
18 | aliases { | |
19 | serial0 = &uarta; | |
a63c0cd8 | 20 | serial3 = &uartd; |
5d17ba6e JH |
21 | }; |
22 | ||
23 | chosen { | |
24 | bootargs = "earlycon"; | |
25 | stdout-path = "serial0:115200n8"; | |
26 | }; | |
27 | ||
28 | memory { | |
29 | device_type = "memory"; | |
30 | reg = <0x0 0x80000000 0x0 0xc0000000>; | |
31 | }; | |
32 | ||
b4f10afd JH |
33 | host1x@50000000 { |
34 | dpaux: dpaux@545c0000 { | |
35 | status = "okay"; | |
36 | }; | |
37 | }; | |
38 | ||
e2dbd577 DI |
39 | gpu@57000000 { |
40 | vdd-supply = <&max77621_gpu>; | |
41 | status = "okay"; | |
42 | }; | |
43 | ||
c1fd85b4 RK |
44 | pinmux: pinmux@700008d4 { |
45 | pinctrl-names = "boot"; | |
46 | pinctrl-0 = <&state_boot>; | |
47 | ||
48 | state_boot: pinmux { | |
49 | pex_l0_rst_n_pa0 { | |
50 | nvidia,pins = "pex_l0_rst_n_pa0"; | |
51 | nvidia,function = "rsvd1"; | |
52 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
53 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
54 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
55 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
56 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
57 | }; | |
58 | pex_l0_clkreq_n_pa1 { | |
59 | nvidia,pins = "pex_l0_clkreq_n_pa1"; | |
60 | nvidia,function = "rsvd1"; | |
61 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
62 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
63 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
64 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
65 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
66 | }; | |
67 | pex_wake_n_pa2 { | |
68 | nvidia,pins = "pex_wake_n_pa2"; | |
69 | nvidia,function = "rsvd1"; | |
70 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
71 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
72 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
73 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
74 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
75 | }; | |
76 | pex_l1_rst_n_pa3 { | |
77 | nvidia,pins = "pex_l1_rst_n_pa3"; | |
78 | nvidia,function = "rsvd1"; | |
79 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
80 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
81 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
82 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
83 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
84 | }; | |
85 | pex_l1_clkreq_n_pa4 { | |
86 | nvidia,pins = "pex_l1_clkreq_n_pa4"; | |
87 | nvidia,function = "rsvd1"; | |
88 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
89 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
90 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
91 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
92 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
93 | }; | |
94 | sata_led_active_pa5 { | |
95 | nvidia,pins = "sata_led_active_pa5"; | |
96 | nvidia,function = "rsvd1"; | |
97 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
98 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
99 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
100 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
101 | }; | |
102 | pa6 { | |
103 | nvidia,pins = "pa6"; | |
104 | nvidia,function = "rsvd1"; | |
105 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
106 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
107 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
108 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
109 | }; | |
110 | dap1_fs_pb0 { | |
111 | nvidia,pins = "dap1_fs_pb0"; | |
112 | nvidia,function = "i2s1"; | |
113 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
114 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
115 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
116 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
117 | }; | |
118 | dap1_din_pb1 { | |
119 | nvidia,pins = "dap1_din_pb1"; | |
120 | nvidia,function = "i2s1"; | |
121 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
122 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
123 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
124 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
125 | }; | |
126 | dap1_dout_pb2 { | |
127 | nvidia,pins = "dap1_dout_pb2"; | |
128 | nvidia,function = "i2s1"; | |
129 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
130 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
131 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
132 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
133 | }; | |
134 | dap1_sclk_pb3 { | |
135 | nvidia,pins = "dap1_sclk_pb3"; | |
136 | nvidia,function = "i2s1"; | |
137 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
138 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
139 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
140 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
141 | }; | |
142 | spi2_mosi_pb4 { | |
143 | nvidia,pins = "spi2_mosi_pb4"; | |
144 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
145 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
146 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
147 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
148 | }; | |
149 | spi2_miso_pb5 { | |
150 | nvidia,pins = "spi2_miso_pb5"; | |
151 | nvidia,function = "rsvd2"; | |
152 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
153 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
154 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
155 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
156 | }; | |
157 | spi2_sck_pb6 { | |
158 | nvidia,pins = "spi2_sck_pb6"; | |
159 | nvidia,function = "rsvd2"; | |
160 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
161 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
162 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
163 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
164 | }; | |
165 | spi2_cs0_pb7 { | |
166 | nvidia,pins = "spi2_cs0_pb7"; | |
167 | nvidia,function = "rsvd2"; | |
168 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
169 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
170 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
171 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
172 | }; | |
173 | spi1_mosi_pc0 { | |
174 | nvidia,pins = "spi1_mosi_pc0"; | |
175 | nvidia,function = "spi1"; | |
176 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
177 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
178 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
179 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
180 | }; | |
181 | spi1_miso_pc1 { | |
182 | nvidia,pins = "spi1_miso_pc1"; | |
183 | nvidia,function = "spi1"; | |
184 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
185 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
186 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
187 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
188 | }; | |
189 | spi1_sck_pc2 { | |
190 | nvidia,pins = "spi1_sck_pc2"; | |
191 | nvidia,function = "spi1"; | |
192 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
193 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
194 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
195 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
196 | }; | |
197 | spi1_cs0_pc3 { | |
198 | nvidia,pins = "spi1_cs0_pc3"; | |
199 | nvidia,function = "spi1"; | |
200 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
201 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
202 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
203 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
204 | }; | |
205 | spi1_cs1_pc4 { | |
206 | nvidia,pins = "spi1_cs1_pc4"; | |
207 | nvidia,function = "rsvd1"; | |
208 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
209 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
210 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
211 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
212 | }; | |
213 | spi4_sck_pc5 { | |
214 | nvidia,pins = "spi4_sck_pc5"; | |
215 | nvidia,function = "rsvd1"; | |
216 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
217 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
218 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
219 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
220 | }; | |
221 | spi4_cs0_pc6 { | |
222 | nvidia,pins = "spi4_cs0_pc6"; | |
223 | nvidia,function = "rsvd1"; | |
224 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
225 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
226 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
227 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
228 | }; | |
229 | spi4_mosi_pc7 { | |
230 | nvidia,pins = "spi4_mosi_pc7"; | |
231 | nvidia,function = "rsvd1"; | |
232 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
233 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
234 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
235 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
236 | }; | |
237 | spi4_miso_pd0 { | |
238 | nvidia,pins = "spi4_miso_pd0"; | |
239 | nvidia,function = "rsvd1"; | |
240 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
241 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
242 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
243 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
244 | }; | |
245 | uart3_tx_pd1 { | |
246 | nvidia,pins = "uart3_tx_pd1"; | |
247 | nvidia,function = "uartc"; | |
248 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
249 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
250 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
251 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
252 | }; | |
253 | uart3_rx_pd2 { | |
254 | nvidia,pins = "uart3_rx_pd2"; | |
255 | nvidia,function = "uartc"; | |
256 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
257 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
258 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
259 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
260 | }; | |
261 | uart3_rts_pd3 { | |
262 | nvidia,pins = "uart3_rts_pd3"; | |
263 | nvidia,function = "uartc"; | |
264 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
265 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
266 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
267 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
268 | }; | |
269 | uart3_cts_pd4 { | |
270 | nvidia,pins = "uart3_cts_pd4"; | |
271 | nvidia,function = "uartc"; | |
272 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
273 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
274 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
275 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
276 | }; | |
277 | dmic1_clk_pe0 { | |
278 | nvidia,pins = "dmic1_clk_pe0"; | |
279 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
280 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
281 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
282 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
283 | }; | |
284 | dmic1_dat_pe1 { | |
285 | nvidia,pins = "dmic1_dat_pe1"; | |
286 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
287 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
288 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
289 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
290 | }; | |
291 | dmic2_clk_pe2 { | |
292 | nvidia,pins = "dmic2_clk_pe2"; | |
293 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
294 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
295 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
296 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
297 | }; | |
298 | dmic2_dat_pe3 { | |
299 | nvidia,pins = "dmic2_dat_pe3"; | |
300 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
301 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
302 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
303 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
304 | }; | |
305 | dmic3_clk_pe4 { | |
306 | nvidia,pins = "dmic3_clk_pe4"; | |
307 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
308 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
309 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
310 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
311 | }; | |
312 | dmic3_dat_pe5 { | |
313 | nvidia,pins = "dmic3_dat_pe5"; | |
314 | nvidia,function = "rsvd2"; | |
315 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
316 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
317 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
318 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
319 | }; | |
320 | pe6 { | |
321 | nvidia,pins = "pe6"; | |
322 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
323 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
324 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
325 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
326 | }; | |
327 | pe7 { | |
328 | nvidia,pins = "pe7"; | |
329 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
330 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
331 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
332 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
333 | }; | |
334 | gen3_i2c_scl_pf0 { | |
335 | nvidia,pins = "gen3_i2c_scl_pf0"; | |
336 | nvidia,function = "i2c3"; | |
337 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
338 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
339 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
340 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
341 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
342 | }; | |
343 | gen3_i2c_sda_pf1 { | |
344 | nvidia,pins = "gen3_i2c_sda_pf1"; | |
345 | nvidia,function = "i2c3"; | |
346 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
347 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
348 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
349 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
350 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
351 | }; | |
352 | uart2_tx_pg0 { | |
353 | nvidia,pins = "uart2_tx_pg0"; | |
354 | nvidia,function = "uartb"; | |
355 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
356 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
357 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
358 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
359 | }; | |
360 | uart2_rx_pg1 { | |
361 | nvidia,pins = "uart2_rx_pg1"; | |
362 | nvidia,function = "uartb"; | |
363 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
364 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
365 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
366 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
367 | }; | |
368 | uart2_rts_pg2 { | |
369 | nvidia,pins = "uart2_rts_pg2"; | |
370 | nvidia,function = "rsvd2"; | |
371 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
372 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
373 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
374 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
375 | }; | |
376 | uart2_cts_pg3 { | |
377 | nvidia,pins = "uart2_cts_pg3"; | |
378 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
379 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
380 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
381 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
382 | }; | |
383 | wifi_en_ph0 { | |
384 | nvidia,pins = "wifi_en_ph0"; | |
385 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
386 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
387 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
388 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
389 | }; | |
390 | wifi_rst_ph1 { | |
391 | nvidia,pins = "wifi_rst_ph1"; | |
392 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
393 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
394 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
395 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
396 | }; | |
397 | wifi_wake_ap_ph2 { | |
398 | nvidia,pins = "wifi_wake_ap_ph2"; | |
399 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
400 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
401 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
402 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
403 | }; | |
404 | ap_wake_bt_ph3 { | |
405 | nvidia,pins = "ap_wake_bt_ph3"; | |
406 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
407 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
408 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
409 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
410 | }; | |
411 | bt_rst_ph4 { | |
412 | nvidia,pins = "bt_rst_ph4"; | |
413 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
414 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
415 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
416 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
417 | }; | |
418 | bt_wake_ap_ph5 { | |
419 | nvidia,pins = "bt_wake_ap_ph5"; | |
420 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
421 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
422 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
423 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
424 | }; | |
425 | ph6 { | |
426 | nvidia,pins = "ph6"; | |
427 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
428 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
429 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
430 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
431 | }; | |
432 | ap_wake_nfc_ph7 { | |
433 | nvidia,pins = "ap_wake_nfc_ph7"; | |
434 | nvidia,function = "rsvd0"; | |
435 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
436 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
437 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
438 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
439 | }; | |
440 | nfc_en_pi0 { | |
441 | nvidia,pins = "nfc_en_pi0"; | |
442 | nvidia,function = "rsvd0"; | |
443 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
444 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
445 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
446 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
447 | }; | |
448 | nfc_int_pi1 { | |
449 | nvidia,pins = "nfc_int_pi1"; | |
450 | nvidia,function = "rsvd0"; | |
451 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
452 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
453 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
454 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
455 | }; | |
456 | gps_en_pi2 { | |
457 | nvidia,pins = "gps_en_pi2"; | |
458 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
459 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
460 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
461 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
462 | }; | |
463 | gps_rst_pi3 { | |
464 | nvidia,pins = "gps_rst_pi3"; | |
465 | nvidia,function = "rsvd0"; | |
466 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
467 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
468 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
469 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
470 | }; | |
471 | uart4_tx_pi4 { | |
472 | nvidia,pins = "uart4_tx_pi4"; | |
473 | nvidia,function = "uartd"; | |
474 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
475 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
476 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
477 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
478 | }; | |
479 | uart4_rx_pi5 { | |
480 | nvidia,pins = "uart4_rx_pi5"; | |
481 | nvidia,function = "uartd"; | |
482 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
483 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
484 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
485 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
486 | }; | |
487 | uart4_rts_pi6 { | |
488 | nvidia,pins = "uart4_rts_pi6"; | |
489 | nvidia,function = "uartd"; | |
490 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
491 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
492 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
493 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
494 | }; | |
495 | uart4_cts_pi7 { | |
496 | nvidia,pins = "uart4_cts_pi7"; | |
497 | nvidia,function = "uartd"; | |
498 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
499 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
500 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
501 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
502 | }; | |
503 | gen1_i2c_sda_pj0 { | |
504 | nvidia,pins = "gen1_i2c_sda_pj0"; | |
505 | nvidia,function = "i2c1"; | |
506 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
507 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
508 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
509 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
510 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
511 | }; | |
512 | gen1_i2c_scl_pj1 { | |
513 | nvidia,pins = "gen1_i2c_scl_pj1"; | |
514 | nvidia,function = "i2c1"; | |
515 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
516 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
517 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
518 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
519 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
520 | }; | |
521 | gen2_i2c_scl_pj2 { | |
522 | nvidia,pins = "gen2_i2c_scl_pj2"; | |
523 | nvidia,function = "i2c2"; | |
524 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
525 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
526 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
527 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
528 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
529 | }; | |
530 | gen2_i2c_sda_pj3 { | |
531 | nvidia,pins = "gen2_i2c_sda_pj3"; | |
532 | nvidia,function = "i2c2"; | |
533 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
534 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
535 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
536 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
537 | nvidia,io-hv = <TEGRA_PIN_ENABLE>; | |
538 | }; | |
539 | dap4_fs_pj4 { | |
540 | nvidia,pins = "dap4_fs_pj4"; | |
541 | nvidia,function = "rsvd1"; | |
542 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
543 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
544 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
545 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
546 | }; | |
547 | dap4_din_pj5 { | |
548 | nvidia,pins = "dap4_din_pj5"; | |
549 | nvidia,function = "rsvd1"; | |
550 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
551 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
552 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
553 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
554 | }; | |
555 | dap4_dout_pj6 { | |
556 | nvidia,pins = "dap4_dout_pj6"; | |
557 | nvidia,function = "rsvd1"; | |
558 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
559 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
560 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
561 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
562 | }; | |
563 | dap4_sclk_pj7 { | |
564 | nvidia,pins = "dap4_sclk_pj7"; | |
565 | nvidia,function = "rsvd1"; | |
566 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
567 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
568 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
569 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
570 | }; | |
571 | pk0 { | |
572 | nvidia,pins = "pk0"; | |
573 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
574 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
575 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
576 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
577 | }; | |
578 | pk1 { | |
579 | nvidia,pins = "pk1"; | |
580 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
581 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
582 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
583 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
584 | }; | |
585 | pk2 { | |
586 | nvidia,pins = "pk2"; | |
587 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
588 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
589 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
590 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
591 | }; | |
592 | pk3 { | |
593 | nvidia,pins = "pk3"; | |
594 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
595 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
596 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
597 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
598 | }; | |
599 | pk4 { | |
600 | nvidia,pins = "pk4"; | |
601 | nvidia,function = "rsvd1"; | |
602 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
603 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
604 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
605 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
606 | }; | |
607 | pk5 { | |
608 | nvidia,pins = "pk5"; | |
609 | nvidia,function = "rsvd1"; | |
610 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
611 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
612 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
613 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
614 | }; | |
615 | pk6 { | |
616 | nvidia,pins = "pk6"; | |
617 | nvidia,function = "rsvd1"; | |
618 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
619 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
620 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
621 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
622 | }; | |
623 | pk7 { | |
624 | nvidia,pins = "pk7"; | |
625 | nvidia,function = "rsvd1"; | |
626 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
627 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
628 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
629 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
630 | }; | |
631 | pl0 { | |
632 | nvidia,pins = "pl0"; | |
633 | nvidia,function = "rsvd0"; | |
634 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
635 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
636 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
637 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
638 | }; | |
639 | pl1 { | |
640 | nvidia,pins = "pl1"; | |
641 | nvidia,function = "rsvd1"; | |
642 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
643 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
644 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
645 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
646 | }; | |
647 | sdmmc1_clk_pm0 { | |
648 | nvidia,pins = "sdmmc1_clk_pm0"; | |
649 | nvidia,function = "rsvd1"; | |
650 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
651 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
652 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
653 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
654 | }; | |
655 | sdmmc1_cmd_pm1 { | |
656 | nvidia,pins = "sdmmc1_cmd_pm1"; | |
657 | nvidia,function = "rsvd2"; | |
658 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
659 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
660 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
661 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
662 | }; | |
663 | sdmmc1_dat3_pm2 { | |
664 | nvidia,pins = "sdmmc1_dat3_pm2"; | |
665 | nvidia,function = "rsvd2"; | |
666 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
667 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
668 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
669 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
670 | }; | |
671 | sdmmc1_dat2_pm3 { | |
672 | nvidia,pins = "sdmmc1_dat2_pm3"; | |
673 | nvidia,function = "rsvd2"; | |
674 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
675 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
676 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
677 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
678 | }; | |
679 | sdmmc1_dat1_pm4 { | |
680 | nvidia,pins = "sdmmc1_dat1_pm4"; | |
681 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
682 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
683 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
684 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
685 | }; | |
686 | sdmmc1_dat0_pm5 { | |
687 | nvidia,pins = "sdmmc1_dat0_pm5"; | |
688 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
689 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
690 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
691 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
692 | }; | |
693 | sdmmc3_clk_pp0 { | |
694 | nvidia,pins = "sdmmc3_clk_pp0"; | |
695 | nvidia,function = "rsvd1"; | |
696 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
697 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
698 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
699 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
700 | }; | |
701 | sdmmc3_cmd_pp1 { | |
702 | nvidia,pins = "sdmmc3_cmd_pp1"; | |
703 | nvidia,function = "rsvd1"; | |
704 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
705 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
706 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
707 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
708 | }; | |
709 | sdmmc3_dat3_pp2 { | |
710 | nvidia,pins = "sdmmc3_dat3_pp2"; | |
711 | nvidia,function = "rsvd1"; | |
712 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
713 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
714 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
715 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
716 | }; | |
717 | sdmmc3_dat2_pp3 { | |
718 | nvidia,pins = "sdmmc3_dat2_pp3"; | |
719 | nvidia,function = "rsvd1"; | |
720 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
721 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
722 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
723 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
724 | }; | |
725 | sdmmc3_dat1_pp4 { | |
726 | nvidia,pins = "sdmmc3_dat1_pp4"; | |
727 | nvidia,function = "rsvd1"; | |
728 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
729 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
730 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
731 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
732 | }; | |
733 | sdmmc3_dat0_pp5 { | |
734 | nvidia,pins = "sdmmc3_dat0_pp5"; | |
735 | nvidia,function = "rsvd1"; | |
736 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
737 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
738 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
739 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
740 | }; | |
741 | cam1_mclk_ps0 { | |
742 | nvidia,pins = "cam1_mclk_ps0"; | |
743 | nvidia,function = "extperiph3"; | |
744 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
745 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
746 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
747 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
748 | }; | |
749 | cam2_mclk_ps1 { | |
750 | nvidia,pins = "cam2_mclk_ps1"; | |
751 | nvidia,function = "extperiph3"; | |
752 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
753 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
754 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
755 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
756 | }; | |
757 | cam_i2c_scl_ps2 { | |
758 | nvidia,pins = "cam_i2c_scl_ps2"; | |
759 | nvidia,function = "i2cvi"; | |
760 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
761 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
762 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
763 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
764 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
765 | }; | |
766 | cam_i2c_sda_ps3 { | |
767 | nvidia,pins = "cam_i2c_sda_ps3"; | |
768 | nvidia,function = "i2cvi"; | |
769 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
770 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
771 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
772 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
773 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
774 | }; | |
775 | cam_rst_ps4 { | |
776 | nvidia,pins = "cam_rst_ps4"; | |
777 | nvidia,function = "rsvd1"; | |
778 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
779 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
780 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
781 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
782 | }; | |
783 | cam_af_en_ps5 { | |
784 | nvidia,pins = "cam_af_en_ps5"; | |
785 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
786 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
787 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
788 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
789 | }; | |
790 | cam_flash_en_ps6 { | |
791 | nvidia,pins = "cam_flash_en_ps6"; | |
792 | nvidia,function = "rsvd2"; | |
793 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
794 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
795 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
796 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
797 | }; | |
798 | cam1_pwdn_ps7 { | |
799 | nvidia,pins = "cam1_pwdn_ps7"; | |
800 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
801 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
802 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
803 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
804 | }; | |
805 | cam2_pwdn_pt0 { | |
806 | nvidia,pins = "cam2_pwdn_pt0"; | |
807 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
808 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
809 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
810 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
811 | }; | |
812 | cam1_strobe_pt1 { | |
813 | nvidia,pins = "cam1_strobe_pt1"; | |
814 | nvidia,function = "rsvd1"; | |
815 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
816 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
817 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
818 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
819 | }; | |
820 | uart1_tx_pu0 { | |
821 | nvidia,pins = "uart1_tx_pu0"; | |
822 | nvidia,function = "uarta"; | |
823 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
824 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
825 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
826 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
827 | }; | |
828 | uart1_rx_pu1 { | |
829 | nvidia,pins = "uart1_rx_pu1"; | |
830 | nvidia,function = "uarta"; | |
831 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
832 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
833 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
834 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
835 | }; | |
836 | uart1_rts_pu2 { | |
837 | nvidia,pins = "uart1_rts_pu2"; | |
838 | nvidia,function = "rsvd1"; | |
839 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
840 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
841 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
842 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
843 | }; | |
844 | uart1_cts_pu3 { | |
845 | nvidia,pins = "uart1_cts_pu3"; | |
846 | nvidia,function = "rsvd1"; | |
847 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
848 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
849 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
850 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
851 | }; | |
852 | lcd_bl_pwm_pv0 { | |
853 | nvidia,pins = "lcd_bl_pwm_pv0"; | |
854 | nvidia,function = "rsvd3"; | |
855 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
856 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
857 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
858 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
859 | }; | |
860 | lcd_bl_en_pv1 { | |
861 | nvidia,pins = "lcd_bl_en_pv1"; | |
862 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
863 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
864 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
865 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
866 | }; | |
867 | lcd_rst_pv2 { | |
868 | nvidia,pins = "lcd_rst_pv2"; | |
869 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
870 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
871 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
872 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
873 | }; | |
874 | lcd_gpio1_pv3 { | |
875 | nvidia,pins = "lcd_gpio1_pv3"; | |
876 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
877 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
878 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
879 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
880 | }; | |
881 | lcd_gpio2_pv4 { | |
882 | nvidia,pins = "lcd_gpio2_pv4"; | |
883 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
884 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
885 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
886 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
887 | }; | |
888 | ap_ready_pv5 { | |
889 | nvidia,pins = "ap_ready_pv5"; | |
890 | nvidia,function = "rsvd0"; | |
891 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
892 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
893 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
894 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
895 | }; | |
896 | touch_rst_pv6 { | |
897 | nvidia,pins = "touch_rst_pv6"; | |
898 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
899 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
900 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
901 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
902 | }; | |
903 | touch_clk_pv7 { | |
904 | nvidia,pins = "touch_clk_pv7"; | |
905 | nvidia,function = "touch"; | |
906 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
907 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
908 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
909 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
910 | }; | |
911 | modem_wake_ap_px0 { | |
912 | nvidia,pins = "modem_wake_ap_px0"; | |
913 | nvidia,function = "rsvd0"; | |
914 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
915 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
916 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
917 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
918 | }; | |
919 | touch_int_px1 { | |
920 | nvidia,pins = "touch_int_px1"; | |
921 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
922 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
923 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
924 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
925 | }; | |
926 | motion_int_px2 { | |
927 | nvidia,pins = "motion_int_px2"; | |
928 | nvidia,function = "rsvd0"; | |
929 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
930 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
931 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
932 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
933 | }; | |
934 | als_prox_int_px3 { | |
935 | nvidia,pins = "als_prox_int_px3"; | |
936 | nvidia,function = "rsvd0"; | |
937 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
938 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
939 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
940 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
941 | }; | |
942 | temp_alert_px4 { | |
943 | nvidia,pins = "temp_alert_px4"; | |
944 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
945 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
946 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
947 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
948 | }; | |
949 | button_power_on_px5 { | |
950 | nvidia,pins = "button_power_on_px5"; | |
951 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
952 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
953 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
954 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
955 | }; | |
956 | button_vol_up_px6 { | |
957 | nvidia,pins = "button_vol_up_px6"; | |
958 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
959 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
960 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
961 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
962 | }; | |
963 | button_vol_down_px7 { | |
964 | nvidia,pins = "button_vol_down_px7"; | |
965 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
966 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
967 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
968 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
969 | }; | |
970 | button_slide_sw_py0 { | |
971 | nvidia,pins = "button_slide_sw_py0"; | |
972 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
973 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
974 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
975 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
976 | }; | |
977 | button_home_py1 { | |
978 | nvidia,pins = "button_home_py1"; | |
979 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
980 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
981 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
982 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
983 | }; | |
984 | lcd_te_py2 { | |
985 | nvidia,pins = "lcd_te_py2"; | |
986 | nvidia,function = "displaya"; | |
987 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
988 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
989 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
990 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
991 | }; | |
992 | pwr_i2c_scl_py3 { | |
993 | nvidia,pins = "pwr_i2c_scl_py3"; | |
994 | nvidia,function = "i2cpmu"; | |
995 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
996 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
997 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
998 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
999 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1000 | }; | |
1001 | pwr_i2c_sda_py4 { | |
1002 | nvidia,pins = "pwr_i2c_sda_py4"; | |
1003 | nvidia,function = "i2cpmu"; | |
1004 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1005 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1006 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1007 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1008 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1009 | }; | |
1010 | clk_32k_out_py5 { | |
1011 | nvidia,pins = "clk_32k_out_py5"; | |
1012 | nvidia,function = "soc"; | |
1013 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1014 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1015 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1016 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1017 | }; | |
1018 | pz0 { | |
1019 | nvidia,pins = "pz0"; | |
1020 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1021 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1022 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1023 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1024 | }; | |
1025 | pz1 { | |
1026 | nvidia,pins = "pz1"; | |
1027 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1028 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1029 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1030 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1031 | }; | |
1032 | pz2 { | |
1033 | nvidia,pins = "pz2"; | |
1034 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1035 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1036 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1037 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1038 | }; | |
1039 | pz3 { | |
1040 | nvidia,pins = "pz3"; | |
1041 | nvidia,function = "rsvd1"; | |
1042 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1043 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1044 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1045 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1046 | }; | |
1047 | pz4 { | |
1048 | nvidia,pins = "pz4"; | |
1049 | nvidia,function = "rsvd1"; | |
1050 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1051 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1052 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1053 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1054 | }; | |
1055 | pz5 { | |
1056 | nvidia,pins = "pz5"; | |
1057 | nvidia,function = "soc"; | |
1058 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1059 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1060 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1061 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1062 | }; | |
1063 | dap2_fs_paa0 { | |
1064 | nvidia,pins = "dap2_fs_paa0"; | |
1065 | nvidia,function = "i2s2"; | |
1066 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1067 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1068 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1069 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1070 | }; | |
1071 | dap2_sclk_paa1 { | |
1072 | nvidia,pins = "dap2_sclk_paa1"; | |
1073 | nvidia,function = "i2s2"; | |
1074 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1075 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1076 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1077 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1078 | }; | |
1079 | dap2_din_paa2 { | |
1080 | nvidia,pins = "dap2_din_paa2"; | |
1081 | nvidia,function = "i2s2"; | |
1082 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1083 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1084 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1085 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1086 | }; | |
1087 | dap2_dout_paa3 { | |
1088 | nvidia,pins = "dap2_dout_paa3"; | |
1089 | nvidia,function = "i2s2"; | |
1090 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1091 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1092 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1093 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1094 | }; | |
1095 | aud_mclk_pbb0 { | |
1096 | nvidia,pins = "aud_mclk_pbb0"; | |
1097 | nvidia,function = "aud"; | |
1098 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1099 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1100 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1101 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1102 | }; | |
1103 | dvfs_pwm_pbb1 { | |
1104 | nvidia,pins = "dvfs_pwm_pbb1"; | |
1105 | nvidia,function = "rsvd0"; | |
1106 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1107 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1108 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1109 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1110 | }; | |
1111 | dvfs_clk_pbb2 { | |
1112 | nvidia,pins = "dvfs_clk_pbb2"; | |
1113 | nvidia,function = "rsvd0"; | |
1114 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1115 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1116 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1117 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1118 | }; | |
1119 | gpio_x1_aud_pbb3 { | |
1120 | nvidia,pins = "gpio_x1_aud_pbb3"; | |
1121 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1122 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1123 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1124 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1125 | }; | |
1126 | gpio_x3_aud_pbb4 { | |
1127 | nvidia,pins = "gpio_x3_aud_pbb4"; | |
1128 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1129 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1130 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1131 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1132 | }; | |
1133 | hdmi_cec_pcc0 { | |
1134 | nvidia,pins = "hdmi_cec_pcc0"; | |
1135 | nvidia,function = "rsvd1"; | |
1136 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1137 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1138 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1139 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1140 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1141 | }; | |
1142 | hdmi_int_dp_hpd_pcc1 { | |
1143 | nvidia,pins = "hdmi_int_dp_hpd_pcc1"; | |
1144 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1145 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1146 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1147 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1148 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1149 | }; | |
1150 | spdif_out_pcc2 { | |
1151 | nvidia,pins = "spdif_out_pcc2"; | |
1152 | nvidia,function = "rsvd1"; | |
1153 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1154 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1155 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1156 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1157 | }; | |
1158 | spdif_in_pcc3 { | |
1159 | nvidia,pins = "spdif_in_pcc3"; | |
1160 | nvidia,function = "rsvd1"; | |
1161 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1162 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1163 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1164 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1165 | }; | |
1166 | usb_vbus_en0_pcc4 { | |
1167 | nvidia,pins = "usb_vbus_en0_pcc4"; | |
1168 | nvidia,function = "rsvd1"; | |
1169 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1170 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1171 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1172 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1173 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1174 | }; | |
1175 | usb_vbus_en1_pcc5 { | |
1176 | nvidia,pins = "usb_vbus_en1_pcc5"; | |
1177 | nvidia,function = "rsvd1"; | |
1178 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1179 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1180 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1181 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1182 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1183 | }; | |
1184 | dp_hpd0_pcc6 { | |
1185 | nvidia,pins = "dp_hpd0_pcc6"; | |
1186 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1187 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1188 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1189 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1190 | }; | |
1191 | pcc7 { | |
1192 | nvidia,pins = "pcc7"; | |
1193 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1194 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1195 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1196 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1197 | nvidia,io-hv = <TEGRA_PIN_DISABLE>; | |
1198 | }; | |
1199 | spi2_cs1_pdd0 { | |
1200 | nvidia,pins = "spi2_cs1_pdd0"; | |
1201 | nvidia,function = "rsvd1"; | |
1202 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1203 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1204 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1205 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1206 | }; | |
1207 | qspi_sck_pee0 { | |
1208 | nvidia,pins = "qspi_sck_pee0"; | |
1209 | nvidia,function = "qspi"; | |
1210 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1211 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1212 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1213 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1214 | }; | |
1215 | qspi_cs_n_pee1 { | |
1216 | nvidia,pins = "qspi_cs_n_pee1"; | |
1217 | nvidia,function = "qspi"; | |
1218 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1219 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1220 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1221 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1222 | }; | |
1223 | qspi_io0_pee2 { | |
1224 | nvidia,pins = "qspi_io0_pee2"; | |
1225 | nvidia,function = "qspi"; | |
1226 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1227 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1228 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1229 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1230 | }; | |
1231 | qspi_io1_pee3 { | |
1232 | nvidia,pins = "qspi_io1_pee3"; | |
1233 | nvidia,function = "qspi"; | |
1234 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1235 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1236 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1237 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1238 | }; | |
1239 | qspi_io2_pee4 { | |
1240 | nvidia,pins = "qspi_io2_pee4"; | |
1241 | nvidia,function = "rsvd1"; | |
1242 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1243 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1244 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1245 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1246 | }; | |
1247 | qspi_io3_pee5 { | |
1248 | nvidia,pins = "qspi_io3_pee5"; | |
1249 | nvidia,function = "rsvd1"; | |
1250 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1251 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1252 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1253 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1254 | }; | |
1255 | core_pwr_req { | |
1256 | nvidia,pins = "core_pwr_req"; | |
1257 | nvidia,function = "core"; | |
1258 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1259 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1260 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1261 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1262 | }; | |
1263 | cpu_pwr_req { | |
1264 | nvidia,pins = "cpu_pwr_req"; | |
1265 | nvidia,function = "cpu"; | |
1266 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1267 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1268 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1269 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1270 | }; | |
1271 | pwr_int_n { | |
1272 | nvidia,pins = "pwr_int_n"; | |
1273 | nvidia,function = "pmi"; | |
1274 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1275 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1276 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1277 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1278 | }; | |
1279 | clk_32k_in { | |
1280 | nvidia,pins = "clk_32k_in"; | |
1281 | nvidia,function = "clk"; | |
1282 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1283 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1284 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
1285 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1286 | }; | |
1287 | jtag_rtck { | |
1288 | nvidia,pins = "jtag_rtck"; | |
1289 | nvidia,function = "jtag"; | |
1290 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
1291 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1292 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1293 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1294 | }; | |
1295 | clk_req { | |
1296 | nvidia,pins = "clk_req"; | |
1297 | nvidia,function = "rsvd1"; | |
1298 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; | |
1299 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
1300 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1301 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1302 | }; | |
1303 | shutdown { | |
1304 | nvidia,pins = "shutdown"; | |
1305 | nvidia,function = "shutdown"; | |
1306 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
1307 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
1308 | nvidia,enable-input = <TEGRA_PIN_DISABLE>; | |
1309 | nvidia,open-drain = <TEGRA_PIN_DISABLE>; | |
1310 | }; | |
1311 | }; | |
1312 | }; | |
1313 | ||
5d17ba6e | 1314 | serial@70006000 { |
6b53039e TR |
1315 | /delete-property/ dmas; |
1316 | /delete-property/ dma-names; | |
5d17ba6e JH |
1317 | status = "okay"; |
1318 | }; | |
1319 | ||
a63c0cd8 DI |
1320 | uartd: serial@70006300 { |
1321 | compatible = "nvidia,tegra30-hsuart"; | |
590bfe51 | 1322 | reset-names = "serial"; |
938745c5 | 1323 | /delete-property/ reg-shift; |
a63c0cd8 DI |
1324 | status = "okay"; |
1325 | ||
1326 | bluetooth { | |
1327 | compatible = "brcm,bcm43540-bt"; | |
1328 | max-speed = <4000000>; | |
1329 | brcm,bt-pcm-int-params = [01 02 00 01 01]; | |
1330 | device-wakeup-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>; | |
1331 | shutdown-gpios = <&gpio TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; | |
1332 | interrupt-parent = <&gpio>; | |
1333 | interrupts = <TEGRA_GPIO(H, 5) IRQ_TYPE_LEVEL_LOW>; | |
1334 | interrupt-names = "host-wakeup"; | |
1335 | }; | |
1336 | }; | |
1337 | ||
8d53957c RK |
1338 | i2c@7000c400 { |
1339 | status = "okay"; | |
1340 | clock-frequency = <1000000>; | |
1341 | ||
1342 | ec@1e { | |
1343 | compatible = "google,cros-ec-i2c"; | |
1344 | reg = <0x1e>; | |
1345 | interrupt-parent = <&gpio>; | |
1346 | interrupts = <TEGRA_GPIO(Z, 1) IRQ_TYPE_LEVEL_LOW>; | |
1347 | wakeup-source; | |
1348 | ||
1349 | ec_i2c_0: i2c-tunnel { | |
1350 | compatible = "google,cros-ec-i2c-tunnel"; | |
1351 | #address-cells = <1>; | |
1352 | #size-cells = <0>; | |
1353 | ||
1354 | google,remote-bus = <0>; | |
1355 | ||
1356 | battery: bq27742@55 { | |
1357 | compatible = "ti,bq27742"; | |
1358 | reg = <0x55>; | |
8d53957c RK |
1359 | }; |
1360 | }; | |
1361 | }; | |
1362 | }; | |
1363 | ||
1b4c8420 RK |
1364 | i2c@7000d000 { |
1365 | status = "okay"; | |
1366 | clock-frequency = <1000000>; | |
1367 | ||
f9c8bcc0 JL |
1368 | max77621_cpu: max77621@1b { |
1369 | compatible = "maxim,max77621"; | |
1370 | reg = <0x1b>; | |
1371 | interrupt-parent = <&gpio>; | |
1372 | interrupts = <TEGRA_GPIO(Y, 1) IRQ_TYPE_LEVEL_LOW>; | |
1373 | regulator-always-on; | |
1374 | regulator-boot-on; | |
1375 | regulator-min-microvolt = <800000>; | |
1376 | regulator-max-microvolt = <1231250>; | |
1377 | regulator-name = "PPVAR_CPU"; | |
1378 | regulator-ramp-delay = <12500>; | |
1379 | maxim,dvs-default-state = <1>; | |
1380 | maxim,enable-active-discharge; | |
1381 | maxim,enable-bias-control; | |
bb678298 | 1382 | maxim,enable-gpio = <&pmic 5 0>; |
f9c8bcc0 JL |
1383 | maxim,externally-enable; |
1384 | }; | |
1385 | ||
aa8ca24c DI |
1386 | max77621_gpu: regulator@1c { |
1387 | compatible = "maxim,max77621"; | |
1388 | reg = <0x1c>; | |
1389 | interrupt-parent = <&gpio>; | |
1390 | interrupts = <TEGRA_GPIO(A, 6) IRQ_TYPE_LEVEL_LOW>; | |
1391 | regulator-min-microvolt = <840000>; | |
1392 | regulator-max-microvolt = <1150000>; | |
1393 | regulator-name = "PPVAR_GPU"; | |
1394 | regulator-ramp-delay = <12500>; | |
1395 | maxim,dvs-default-state = <1>; | |
1396 | maxim,enable-active-discharge; | |
1397 | maxim,enable-bias-control; | |
1398 | maxim,disable-etr; | |
1399 | maxim,enable-gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; | |
1400 | maxim,externally-enable; | |
1401 | }; | |
1402 | ||
bb678298 | 1403 | pmic: pmic@3c { |
1b4c8420 RK |
1404 | compatible = "maxim,max77620"; |
1405 | reg = <0x3c>; | |
968ebd84 | 1406 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
1b4c8420 RK |
1407 | |
1408 | #interrupt-cells = <2>; | |
1409 | interrupt-controller; | |
1410 | ||
1411 | gpio-controller; | |
1412 | #gpio-cells = <2>; | |
1413 | ||
1414 | pinctrl-names = "default"; | |
1415 | pinctrl-0 = <&max77620_default>; | |
1416 | ||
79ed18d9 TR |
1417 | fps { |
1418 | fps0 { | |
1419 | maxim,shutdown-fps-time-period-us = <5120>; | |
1420 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; | |
1421 | }; | |
1422 | ||
1423 | fps1 { | |
1424 | maxim,shutdown-fps-time-period-us = <5120>; | |
1425 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN1>; | |
1426 | maxim,device-state-on-disabled-event = <MAX77620_FPS_INACTIVE_STATE_SLEEP>; | |
1427 | }; | |
1428 | ||
1429 | fps2 { | |
1430 | maxim,fps-event-source = <MAX77620_FPS_EVENT_SRC_EN0>; | |
1431 | }; | |
1432 | }; | |
1433 | ||
bb678298 TR |
1434 | max77620_default: pinmux { |
1435 | gpio0_1_2_7 { | |
1b4c8420 RK |
1436 | pins = "gpio0", "gpio1", "gpio2", "gpio7"; |
1437 | function = "gpio"; | |
1438 | }; | |
1439 | ||
1440 | /* | |
1441 | * GPIO3 is used to en_pp3300, and it is part of power | |
1442 | * sequence, So it must be sequenced up (automatically | |
1443 | * set by OTP) and down properly. | |
1444 | */ | |
bb678298 | 1445 | gpio3 { |
1b4c8420 RK |
1446 | pins = "gpio3"; |
1447 | function = "fps-out"; | |
2f477ee3 | 1448 | drive-open-drain = <1>; |
1b4c8420 RK |
1449 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; |
1450 | maxim,active-fps-power-up-slot = <4>; | |
1451 | maxim,active-fps-power-down-slot = <2>; | |
1452 | }; | |
1453 | ||
bb678298 | 1454 | gpio4 { |
1b4c8420 RK |
1455 | pins = "gpio4"; |
1456 | function = "32k-out1"; | |
1457 | }; | |
1b4c8420 | 1458 | |
79ed18d9 TR |
1459 | gpio5_6 { |
1460 | pins = "gpio5", "gpio6"; | |
1461 | function = "gpio"; | |
1462 | drive-push-pull = <1>; | |
1b4c8420 RK |
1463 | }; |
1464 | }; | |
1465 | ||
1466 | regulators { | |
1467 | in-ldo0-1-supply = <&pp1350>; | |
1468 | in-ldo2-supply = <&pp3300>; | |
1469 | in-ldo3-5-supply = <&pp3300>; | |
1470 | in-ldo7-8-supply = <&pp1350>; | |
1471 | ||
1472 | ppvar_soc: sd0 { | |
1473 | regulator-name = "PPVAR_SOC"; | |
1474 | regulator-min-microvolt = <825000>; | |
1475 | regulator-max-microvolt = <1125000>; | |
1476 | regulator-always-on; | |
1477 | regulator-boot-on; | |
1478 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; | |
1479 | maxim,active-fps-power-up-slot = <1>; | |
1480 | maxim,active-fps-power-down-slot = <7>; | |
1481 | }; | |
1482 | ||
1483 | pp1100_sd1: sd1 { | |
1484 | regulator-name = "PP1100"; | |
1485 | regulator-min-microvolt = <1125000>; | |
1486 | regulator-max-microvolt = <1125000>; | |
1487 | regulator-always-on; | |
1488 | regulator-boot-on; | |
1489 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; | |
1490 | maxim,active-fps-power-up-slot = <5>; | |
1491 | maxim,active-fps-power-down-slot = <1>; | |
1492 | }; | |
1493 | ||
1494 | pp1350: sd2 { | |
1495 | regulator-name = "PP1350"; | |
1496 | regulator-min-microvolt = <1350000>; | |
1497 | regulator-max-microvolt = <1350000>; | |
1498 | regulator-always-on; | |
1499 | regulator-boot-on; | |
1500 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; | |
1501 | maxim,active-fps-power-up-slot = <2>; | |
1502 | maxim,active-fps-power-down-slot = <5>; | |
1503 | }; | |
1504 | ||
1505 | pp1800: sd3 { | |
1506 | regulator-name = "PP1800"; | |
1507 | regulator-min-microvolt = <1800000>; | |
1508 | regulator-max-microvolt = <1800000>; | |
1509 | regulator-always-on; | |
1510 | regulator-boot-on; | |
1511 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; | |
1512 | maxim,active-fps-power-up-slot = <3>; | |
1513 | maxim,active-fps-power-down-slot = <3>; | |
1514 | }; | |
1515 | ||
1516 | pp1200_avdd: ldo0 { | |
1517 | regulator-name = "PP1200_AVDD"; | |
1518 | regulator-min-microvolt = <1200000>; | |
1519 | regulator-max-microvolt = <1200000>; | |
1520 | regulator-enable-ramp-delay = <26>; | |
1521 | regulator-ramp-delay = <100000>; | |
1522 | regulator-boot-on; | |
1523 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; | |
1524 | maxim,active-fps-power-up-slot = <0>; | |
1525 | maxim,active-fps-power-down-slot = <7>; | |
1526 | }; | |
1527 | ||
1528 | pp1200_rcam: ldo1 { | |
1529 | regulator-name = "PP1200_RCAM"; | |
1530 | regulator-min-microvolt = <1200000>; | |
1531 | regulator-max-microvolt = <1200000>; | |
1532 | regulator-enable-ramp-delay = <22>; | |
1533 | regulator-ramp-delay = <100000>; | |
1534 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; | |
1535 | maxim,active-fps-power-up-slot = <0>; | |
1536 | maxim,active-fps-power-down-slot = <7>; | |
1537 | }; | |
1538 | ||
1539 | pp_ldo2: ldo2 { | |
1540 | regulator-name = "PP_LDO2"; | |
1541 | regulator-min-microvolt = <1800000>; | |
1542 | regulator-max-microvolt = <1800000>; | |
1543 | regulator-enable-ramp-delay = <62>; | |
1544 | regulator-ramp-delay = <11000>; | |
1545 | regulator-always-on; | |
1546 | regulator-boot-on; | |
1547 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; | |
1548 | maxim,active-fps-power-up-slot = <0>; | |
1549 | maxim,active-fps-power-down-slot = <7>; | |
1550 | }; | |
1551 | ||
1552 | pp2800l_rcam: ldo3 { | |
1553 | regulator-name = "PP2800L_RCAM"; | |
1554 | regulator-min-microvolt = <2800000>; | |
1555 | regulator-max-microvolt = <2800000>; | |
1556 | regulator-enable-ramp-delay = <50>; | |
1557 | regulator-ramp-delay = <100000>; | |
1558 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; | |
1559 | maxim,active-fps-power-up-slot = <0>; | |
1560 | maxim,active-fps-power-down-slot = <7>; | |
1561 | }; | |
1562 | ||
1563 | pp100_soc_rtc: ldo4 { | |
1564 | regulator-name = "PP1100_SOC_RTC"; | |
1565 | regulator-min-microvolt = <850000>; | |
1566 | regulator-max-microvolt = <850000>; | |
1567 | regulator-enable-ramp-delay = <22>; | |
1568 | regulator-ramp-delay = <100000>; | |
1569 | regulator-always-on; /* Check this */ | |
1570 | regulator-boot-on; | |
1571 | maxim,active-fps-source = <MAX77620_FPS_SRC_0>; | |
1572 | maxim,active-fps-power-up-slot = <1>; | |
1573 | maxim,active-fps-power-down-slot = <7>; | |
1574 | }; | |
1575 | ||
1576 | pp2800l_fcam: ldo5 { | |
1577 | regulator-name = "PP2800L_FCAM"; | |
1578 | regulator-min-microvolt = <2800000>; | |
1579 | regulator-max-microvolt = <2800000>; | |
1580 | regulator-enable-ramp-delay = <62>; | |
1581 | regulator-ramp-delay = <100000>; | |
1582 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; | |
1583 | maxim,active-fps-power-up-slot = <0>; | |
1584 | maxim,active-fps-power-down-slot = <7>; | |
1585 | }; | |
1586 | ||
1587 | ldo6 { | |
1588 | /* Unused. */ | |
1589 | regulator-name = "PP_LDO6"; | |
1590 | regulator-min-microvolt = <1800000>; | |
1591 | regulator-max-microvolt = <1800000>; | |
1592 | regulator-enable-ramp-delay = <36>; | |
1593 | regulator-ramp-delay = <100000>; | |
1594 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; | |
1595 | maxim,active-fps-power-up-slot = <0>; | |
1596 | maxim,active-fps-power-down-slot = <7>; | |
1597 | }; | |
1598 | ||
1599 | pp1050_avdd: ldo7 { | |
1600 | regulator-name = "PP1050_AVDD"; | |
1601 | regulator-min-microvolt = <1050000>; | |
1602 | regulator-max-microvolt = <1050000>; | |
1603 | regulator-enable-ramp-delay = <24>; | |
1604 | regulator-ramp-delay = <100000>; | |
1605 | regulator-always-on; | |
1606 | regulator-boot-on; | |
1607 | maxim,active-fps-source = <MAX77620_FPS_SRC_1>; | |
1608 | maxim,active-fps-power-up-slot = <3>; | |
1609 | maxim,active-fps-power-down-slot = <4>; | |
1610 | }; | |
1611 | ||
1612 | avddio_1v05: ldo8 { | |
1613 | regulator-name = "AVDDIO_1V05"; | |
1614 | regulator-min-microvolt = <1050000>; | |
1615 | regulator-max-microvolt = <1050000>; | |
1616 | regulator-enable-ramp-delay = <22>; | |
1617 | regulator-ramp-delay = <100000>; | |
1618 | regulator-boot-on; | |
1619 | maxim,active-fps-source = <MAX77620_FPS_SRC_NONE>; | |
1620 | maxim,active-fps-power-up-slot = <0>; | |
1621 | maxim,active-fps-power-down-slot = <7>; | |
1622 | }; | |
1623 | }; | |
1624 | }; | |
1625 | }; | |
1626 | ||
3ce510a0 JH |
1627 | i2c@7000d100 { |
1628 | status = "okay"; | |
1629 | clock-frequency = <400000>; | |
1630 | ||
1631 | nau8825@1a { | |
1632 | compatible = "nuvoton,nau8825"; | |
1633 | reg = <0x1a>; | |
1634 | interrupt-parent = <&gpio>; | |
1635 | interrupts = <TEGRA_GPIO(E, 6) IRQ_TYPE_LEVEL_LOW>; | |
d90bd9b7 | 1636 | clocks = <&tegra_pmc TEGRA_PMC_CLK_OUT_2>; |
3ce510a0 JH |
1637 | clock-names = "mclk"; |
1638 | ||
1639 | nuvoton,jkdet-enable; | |
1640 | nuvoton,jkdet-polarity = <GPIO_ACTIVE_LOW>; | |
1641 | nuvoton,vref-impedance = <2>; | |
1642 | nuvoton,micbias-voltage = <6>; | |
1643 | nuvoton,sar-threshold-num = <4>; | |
1644 | nuvoton,sar-threshold = <0xc 0x1e 0x38 0x60>; | |
1645 | nuvoton,sar-hysteresis = <1>; | |
1646 | nuvoton,sar-voltage = <0>; | |
1647 | nuvoton,sar-compare-time = <0>; | |
1648 | nuvoton,sar-sampling-time = <0>; | |
1649 | nuvoton,short-key-debounce = <2>; | |
1650 | nuvoton,jack-insert-debounce = <7>; | |
1651 | nuvoton,jack-eject-debounce = <7>; | |
1652 | status = "okay"; | |
1653 | }; | |
1654 | ||
1655 | audio-codec@2d { | |
1656 | compatible = "realtek,rt5677"; | |
1657 | reg = <0x2d>; | |
1658 | interrupt-parent = <&gpio>; | |
1659 | interrupts = <TEGRA_GPIO(X, 0) IRQ_TYPE_LEVEL_HIGH>; | |
1660 | realtek,reset-gpio = <&gpio TEGRA_GPIO(BB, 3) GPIO_ACTIVE_LOW>; | |
1661 | gpio-controller; | |
1662 | #gpio-cells = <2>; | |
1663 | status = "okay"; | |
1664 | }; | |
1665 | }; | |
1666 | ||
5d17ba6e JH |
1667 | pmc@7000e400 { |
1668 | nvidia,invert-interrupt; | |
1669 | nvidia,suspend-mode = <0>; | |
1670 | nvidia,cpu-pwr-good-time = <0>; | |
1671 | nvidia,cpu-pwr-off-time = <0>; | |
1672 | nvidia,core-pwr-good-time = <12000 6000>; | |
1673 | nvidia,core-pwr-off-time = <39053>; | |
1674 | nvidia,core-power-req-active-high; | |
1675 | nvidia,sys-clock-req-active-high; | |
1676 | status = "okay"; | |
1677 | }; | |
1678 | ||
4d345782 JH |
1679 | usb@70090000 { |
1680 | phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>, | |
1681 | <&{/padctl@7009f000/pads/pcie/lanes/pcie-6}>; | |
1682 | phy-names = "usb2-0", "usb3-0"; | |
1683 | ||
1684 | dvddio-pex-supply = <&avddio_1v05>; | |
1685 | hvddio-pex-supply = <&pp1800>; | |
1686 | avdd-usb-supply = <&pp3300>; | |
4d345782 JH |
1687 | |
1688 | status = "okay"; | |
1689 | }; | |
1690 | ||
1691 | padctl@7009f000 { | |
1692 | status = "okay"; | |
1693 | ||
fa941e69 TR |
1694 | avdd-pll-utmip-supply = <&pp1800>; |
1695 | avdd-pll-uerefe-supply = <&pp1050_avdd>; | |
1696 | dvdd-pex-pll-supply = <&avddio_1v05>; | |
1697 | hvdd-pex-pll-e-supply = <&pp1800>; | |
1698 | ||
4d345782 JH |
1699 | pads { |
1700 | usb2 { | |
1701 | status = "okay"; | |
1702 | ||
1703 | lanes { | |
1704 | usb2-0 { | |
1705 | nvidia,function = "xusb"; | |
1706 | status = "okay"; | |
1707 | }; | |
1708 | }; | |
1709 | }; | |
1710 | ||
1711 | pcie { | |
1712 | status = "okay"; | |
1713 | ||
1714 | lanes { | |
1715 | pcie-6 { | |
1716 | nvidia,function = "usb3-ss"; | |
1717 | status = "okay"; | |
1718 | }; | |
1719 | }; | |
1720 | }; | |
1721 | }; | |
1722 | ||
1723 | ports { | |
1724 | usb2-0 { | |
1725 | status = "okay"; | |
1726 | vbus-supply = <&usbc_vbus>; | |
1727 | mode = "otg"; | |
1728 | }; | |
1729 | ||
1730 | usb3-0 { | |
1731 | nvidia,usb2-companion = <0>; | |
1732 | status = "okay"; | |
1733 | }; | |
1734 | }; | |
1735 | }; | |
1736 | ||
a1e3de6e DI |
1737 | mmc@700b0200 { |
1738 | power-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
1739 | bus-width = <4>; | |
1740 | non-removable; | |
1741 | vqmmc-supply = <&pp1800>; | |
1742 | vmmc-supply = <&pp3300>; | |
1743 | #address-cells = <1>; | |
1744 | #size-cells = <0>; | |
1745 | status = "okay"; | |
1746 | ||
1747 | wifi@1 { | |
1748 | compatible = "brcm,bcm4354-fmac", "brcm,bcm4329-fmac"; | |
1749 | reg = <1>; | |
1750 | interrupt-parent = <&gpio>; | |
1751 | interrupts = <TEGRA_GPIO(H, 2) IRQ_TYPE_LEVEL_HIGH>; | |
1752 | interrupt-names = "host-wake"; | |
1753 | }; | |
1754 | }; | |
1755 | ||
67bb17f6 | 1756 | mmc@700b0600 { |
5d17ba6e JH |
1757 | bus-width = <8>; |
1758 | non-removable; | |
1759 | status = "okay"; | |
1760 | }; | |
1761 | ||
d4eb7653 JL |
1762 | clock@70110000 { |
1763 | status = "okay"; | |
1764 | nvidia,cf = <6>; | |
1765 | nvidia,ci = <0>; | |
1766 | nvidia,cg = <2>; | |
1767 | nvidia,droop-ctrl = <0x00000f00>; | |
1768 | nvidia,force-mode = <1>; | |
1769 | nvidia,i2c-fs-rate = <400000>; | |
1770 | nvidia,sample-rate = <12500>; | |
1771 | vdd-cpu-supply = <&max77621_cpu>; | |
1772 | }; | |
1773 | ||
9fab004d JH |
1774 | aconnect@702c0000 { |
1775 | status = "okay"; | |
1776 | ||
b6e136c7 | 1777 | dma-controller@702e2000 { |
9fab004d JH |
1778 | status = "okay"; |
1779 | }; | |
1780 | ||
df93557b | 1781 | interrupt-controller@702f9000 { |
9fab004d JH |
1782 | status = "okay"; |
1783 | }; | |
1784 | }; | |
1785 | ||
4cc3e3e1 | 1786 | clk32k_in: clock-32k { |
393a403e TR |
1787 | compatible = "fixed-clock"; |
1788 | clock-frequency = <32768>; | |
1789 | #clock-cells = <0>; | |
5d17ba6e JH |
1790 | }; |
1791 | ||
1792 | cpus { | |
1793 | cpu@0 { | |
1794 | enable-method = "psci"; | |
1795 | }; | |
1796 | ||
1797 | cpu@1 { | |
1798 | enable-method = "psci"; | |
1799 | }; | |
1800 | ||
1801 | cpu@2 { | |
1802 | enable-method = "psci"; | |
1803 | }; | |
1804 | ||
1805 | cpu@3 { | |
1806 | enable-method = "psci"; | |
1807 | }; | |
15e66696 JL |
1808 | |
1809 | idle-states { | |
1810 | cpu-sleep { | |
1811 | arm,psci-suspend-param = <0x00010007>; | |
1812 | status = "okay"; | |
1813 | }; | |
1814 | }; | |
5d17ba6e JH |
1815 | }; |
1816 | ||
a26f3963 RK |
1817 | gpio-keys { |
1818 | compatible = "gpio-keys"; | |
a26f3963 | 1819 | |
012877d0 | 1820 | key-power { |
a26f3963 RK |
1821 | label = "Power"; |
1822 | gpios = <&gpio TEGRA_GPIO(X, 5) GPIO_ACTIVE_LOW>; | |
1823 | linux,code = <KEY_POWER>; | |
1824 | debounce-interval = <30>; | |
1825 | wakeup-source; | |
1826 | }; | |
1827 | ||
79ed18d9 TR |
1828 | key-volume-down { |
1829 | label = "Volume Down"; | |
1830 | gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; | |
1831 | linux,code = <KEY_VOLUMEDOWN>; | |
1832 | }; | |
1833 | ||
1834 | key-volume-up { | |
1835 | label = "Volume Up"; | |
1836 | gpios = <&gpio TEGRA_GPIO(M, 4) GPIO_ACTIVE_LOW>; | |
1837 | linux,code = <KEY_VOLUMEUP>; | |
1838 | }; | |
1839 | ||
012877d0 | 1840 | switch-lid { |
a26f3963 RK |
1841 | label = "Lid"; |
1842 | gpios = <&gpio TEGRA_GPIO(B, 4) GPIO_ACTIVE_LOW>; | |
1843 | linux,input-type = <EV_SW>; | |
1844 | linux,code = <SW_LID>; | |
1845 | wakeup-source; | |
1846 | }; | |
1847 | ||
012877d0 | 1848 | switch-tablet-mode { |
a26f3963 RK |
1849 | label = "Tablet Mode"; |
1850 | gpios = <&gpio TEGRA_GPIO(Z, 2) GPIO_ACTIVE_HIGH>; | |
1851 | linux,input-type = <EV_SW>; | |
1852 | linux,code = <SW_TABLET_MODE>; | |
1853 | wakeup-source; | |
1854 | }; | |
a26f3963 RK |
1855 | }; |
1856 | ||
3ce510a0 JH |
1857 | max98357a { |
1858 | compatible = "maxim,max98357a"; | |
1859 | status = "okay"; | |
1860 | }; | |
1861 | ||
5d17ba6e JH |
1862 | psci { |
1863 | compatible = "arm,psci-1.0"; | |
1864 | method = "smc"; | |
1865 | }; | |
1b4c8420 | 1866 | |
097e01c6 | 1867 | ppvar_sys: regulator-ppvar-sys { |
7517248a TR |
1868 | compatible = "regulator-fixed"; |
1869 | regulator-name = "PPVAR_SYS"; | |
1870 | regulator-min-microvolt = <4400000>; | |
1871 | regulator-max-microvolt = <4400000>; | |
1872 | regulator-always-on; | |
1873 | }; | |
1b4c8420 | 1874 | |
097e01c6 | 1875 | pplcd_vdd: regulator-pplcd-vdd { |
7517248a TR |
1876 | compatible = "regulator-fixed"; |
1877 | regulator-name = "PPLCD_VDD"; | |
1878 | regulator-min-microvolt = <4400000>; | |
1879 | regulator-max-microvolt = <4400000>; | |
1880 | gpio = <&gpio TEGRA_GPIO(V, 4) 0>; | |
1881 | enable-active-high; | |
1882 | regulator-boot-on; | |
1883 | }; | |
1b4c8420 | 1884 | |
097e01c6 | 1885 | pp3000_always: regulator-pp3000-always { |
7517248a TR |
1886 | compatible = "regulator-fixed"; |
1887 | regulator-name = "PP3000_ALWAYS"; | |
1888 | regulator-min-microvolt = <3000000>; | |
1889 | regulator-max-microvolt = <3000000>; | |
1890 | regulator-always-on; | |
1891 | }; | |
1b4c8420 | 1892 | |
097e01c6 | 1893 | pp3300: regulator-pp3000 { |
7517248a TR |
1894 | compatible = "regulator-fixed"; |
1895 | regulator-name = "PP3300"; | |
1896 | regulator-min-microvolt = <3300000>; | |
1897 | regulator-max-microvolt = <3300000>; | |
1898 | regulator-boot-on; | |
1899 | regulator-always-on; | |
1900 | enable-active-high; | |
1901 | }; | |
1b4c8420 | 1902 | |
097e01c6 | 1903 | pp5000: regulator-pp5000 { |
7517248a TR |
1904 | compatible = "regulator-fixed"; |
1905 | regulator-name = "PP5000"; | |
1906 | regulator-min-microvolt = <5000000>; | |
1907 | regulator-max-microvolt = <5000000>; | |
1908 | regulator-always-on; | |
1909 | }; | |
1b4c8420 | 1910 | |
097e01c6 | 1911 | pp1800_lcdio: regulator-pp1800-lcdio { |
7517248a TR |
1912 | compatible = "regulator-fixed"; |
1913 | regulator-name = "PP1800_LCDIO"; | |
1914 | regulator-min-microvolt = <1800000>; | |
1915 | regulator-max-microvolt = <1800000>; | |
1916 | gpio = <&gpio TEGRA_GPIO(V, 3) 0>; | |
1917 | enable-active-high; | |
1918 | regulator-boot-on; | |
1919 | }; | |
1b4c8420 | 1920 | |
097e01c6 | 1921 | pp1800_cam: regulator-pp1800-cam { |
7517248a TR |
1922 | compatible = "regulator-fixed"; |
1923 | regulator-name = "PP1800_CAM"; | |
1924 | regulator-min-microvolt = <1800000>; | |
1925 | regulator-max-microvolt = <1800000>; | |
1926 | gpio = <&gpio TEGRA_GPIO(K, 3) 0>; | |
1927 | enable-active-high; | |
1928 | }; | |
1b4c8420 | 1929 | |
097e01c6 | 1930 | usbc_vbus: regulator-usbc-vbus { |
7517248a TR |
1931 | compatible = "regulator-fixed"; |
1932 | regulator-name = "USBC_VBUS"; | |
1933 | regulator-min-microvolt = <5000000>; | |
1934 | regulator-max-microvolt = <5000000>; | |
1b4c8420 | 1935 | }; |
5d17ba6e | 1936 | }; |