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arm64: tegra: Remove unused property for I2C
[thirdparty/linux.git] / arch / arm64 / boot / dts / nvidia / tegra234.dtsi
CommitLineData
63944891
TR		 1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/clock/tegra234-clock.h>
699349e0 4#include <dt-bindings/gpio/tegra234-gpio.h>
63944891
TR		 5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/mailbox/tegra186-hsp.h>
eed280df 7#include <dt-bindings/memory/tegra234-mc.h>
dc94a94d 8#include <dt-bindings/power/tegra234-powergate.h>
63944891
TR		 9#include <dt-bindings/reset/tegra234-reset.h>
10
11/ {
12 compatible = "nvidia,tegra234";
13 interrupt-parent = <&gic>;
14 #address-cells = <2>;
15 #size-cells = <2>;
16
17 bus@0 {
18 compatible = "simple-bus";
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 ranges = <0x0 0x0 0x0 0x40000000>;
23
60d2016a 24 gpcdma: dma-controller@2600000 {
f7b93a08 25 compatible = "nvidia,tegra234-gpcdma",
f7b93a08 26 "nvidia,tegra186-gpcdma";
60d2016a
A		 27 reg = <0x2600000 0x210000>;
28 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
29 reset-names = "gpcdma";
30 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
31 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
33 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
35 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
61 #dma-cells = <1>;
62 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
63 dma-coherent;
64 };
65
dc94a94d
SP		 66 aconnect@2900000 {
67 compatible = "nvidia,tegra234-aconnect",
68 "nvidia,tegra210-aconnect";
69 clocks = <&bpmp TEGRA234_CLK_APE>,
70 <&bpmp TEGRA234_CLK_APB2APE>;
71 clock-names = "ape", "apb2ape";
72 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges = <0x02900000 0x02900000 0x200000>;
76 status = "disabled";
77
78 tegra_ahub: ahub@2900800 {
79 compatible = "nvidia,tegra234-ahub";
80 reg = <0x02900800 0x800>;
81 clocks = <&bpmp TEGRA234_CLK_AHUB>;
82 clock-names = "ahub";
83 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
84 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
85 #address-cells = <1>;
86 #size-cells = <1>;
87 ranges = <0x02900800 0x02900800 0x11800>;
88 status = "disabled";
89
90 tegra_i2s1: i2s@2901000 {
91 compatible = "nvidia,tegra234-i2s",
92 "nvidia,tegra210-i2s";
93 reg = <0x2901000 0x100>;
94 clocks = <&bpmp TEGRA234_CLK_I2S1>,
95 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
96 clock-names = "i2s", "sync_input";
97 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
98 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
99 assigned-clock-rates = <1536000>;
100 sound-name-prefix = "I2S1";
101 status = "disabled";
102 };
103
104 tegra_i2s2: i2s@2901100 {
105 compatible = "nvidia,tegra234-i2s",
106 "nvidia,tegra210-i2s";
107 reg = <0x2901100 0x100>;
108 clocks = <&bpmp TEGRA234_CLK_I2S2>,
109 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
110 clock-names = "i2s", "sync_input";
111 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
112 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
113 assigned-clock-rates = <1536000>;
114 sound-name-prefix = "I2S2";
115 status = "disabled";
116 };
117
118 tegra_i2s3: i2s@2901200 {
119 compatible = "nvidia,tegra234-i2s",
120 "nvidia,tegra210-i2s";
121 reg = <0x2901200 0x100>;
122 clocks = <&bpmp TEGRA234_CLK_I2S3>,
123 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
124 clock-names = "i2s", "sync_input";
125 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
126 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
127 assigned-clock-rates = <1536000>;
128 sound-name-prefix = "I2S3";
129 status = "disabled";
130 };
131
132 tegra_i2s4: i2s@2901300 {
133 compatible = "nvidia,tegra234-i2s",
134 "nvidia,tegra210-i2s";
135 reg = <0x2901300 0x100>;
136 clocks = <&bpmp TEGRA234_CLK_I2S4>,
137 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
138 clock-names = "i2s", "sync_input";
139 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
140 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
141 assigned-clock-rates = <1536000>;
142 sound-name-prefix = "I2S4";
143 status = "disabled";
144 };
145
146 tegra_i2s5: i2s@2901400 {
147 compatible = "nvidia,tegra234-i2s",
148 "nvidia,tegra210-i2s";
149 reg = <0x2901400 0x100>;
150 clocks = <&bpmp TEGRA234_CLK_I2S5>,
151 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
152 clock-names = "i2s", "sync_input";
153 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
154 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
155 assigned-clock-rates = <1536000>;
156 sound-name-prefix = "I2S5";
157 status = "disabled";
158 };
159
160 tegra_i2s6: i2s@2901500 {
161 compatible = "nvidia,tegra234-i2s",
162 "nvidia,tegra210-i2s";
163 reg = <0x2901500 0x100>;
164 clocks = <&bpmp TEGRA234_CLK_I2S6>,
165 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
166 clock-names = "i2s", "sync_input";
167 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
168 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
169 assigned-clock-rates = <1536000>;
170 sound-name-prefix = "I2S6";
171 status = "disabled";
172 };
173
174 tegra_sfc1: sfc@2902000 {
175 compatible = "nvidia,tegra234-sfc",
176 "nvidia,tegra210-sfc";
177 reg = <0x2902000 0x200>;
178 sound-name-prefix = "SFC1";
179 status = "disabled";
180 };
181
182 tegra_sfc2: sfc@2902200 {
183 compatible = "nvidia,tegra234-sfc",
184 "nvidia,tegra210-sfc";
185 reg = <0x2902200 0x200>;
186 sound-name-prefix = "SFC2";
187 status = "disabled";
188 };
189
190 tegra_sfc3: sfc@2902400 {
191 compatible = "nvidia,tegra234-sfc",
192 "nvidia,tegra210-sfc";
193 reg = <0x2902400 0x200>;
194 sound-name-prefix = "SFC3";
195 status = "disabled";
196 };
197
198 tegra_sfc4: sfc@2902600 {
199 compatible = "nvidia,tegra234-sfc",
200 "nvidia,tegra210-sfc";
201 reg = <0x2902600 0x200>;
202 sound-name-prefix = "SFC4";
203 status = "disabled";
204 };
205
206 tegra_amx1: amx@2903000 {
207 compatible = "nvidia,tegra234-amx",
208 "nvidia,tegra194-amx";
209 reg = <0x2903000 0x100>;
210 sound-name-prefix = "AMX1";
211 status = "disabled";
212 };
213
214 tegra_amx2: amx@2903100 {
215 compatible = "nvidia,tegra234-amx",
216 "nvidia,tegra194-amx";
217 reg = <0x2903100 0x100>;
218 sound-name-prefix = "AMX2";
219 status = "disabled";
220 };
221
222 tegra_amx3: amx@2903200 {
223 compatible = "nvidia,tegra234-amx",
224 "nvidia,tegra194-amx";
225 reg = <0x2903200 0x100>;
226 sound-name-prefix = "AMX3";
227 status = "disabled";
228 };
229
230 tegra_amx4: amx@2903300 {
231 compatible = "nvidia,tegra234-amx",
232 "nvidia,tegra194-amx";
233 reg = <0x2903300 0x100>;
234 sound-name-prefix = "AMX4";
235 status = "disabled";
236 };
237
238 tegra_adx1: adx@2903800 {
239 compatible = "nvidia,tegra234-adx",
240 "nvidia,tegra210-adx";
241 reg = <0x2903800 0x100>;
242 sound-name-prefix = "ADX1";
243 status = "disabled";
244 };
245
246 tegra_adx2: adx@2903900 {
247 compatible = "nvidia,tegra234-adx",
248 "nvidia,tegra210-adx";
249 reg = <0x2903900 0x100>;
250 sound-name-prefix = "ADX2";
251 status = "disabled";
252 };
253
254 tegra_adx3: adx@2903a00 {
255 compatible = "nvidia,tegra234-adx",
256 "nvidia,tegra210-adx";
257 reg = <0x2903a00 0x100>;
258 sound-name-prefix = "ADX3";
259 status = "disabled";
260 };
261
262 tegra_adx4: adx@2903b00 {
263 compatible = "nvidia,tegra234-adx",
264 "nvidia,tegra210-adx";
265 reg = <0x2903b00 0x100>;
266 sound-name-prefix = "ADX4";
267 status = "disabled";
268 };
269
270
271 tegra_dmic1: dmic@2904000 {
272 compatible = "nvidia,tegra234-dmic",
273 "nvidia,tegra210-dmic";
274 reg = <0x2904000 0x100>;
275 clocks = <&bpmp TEGRA234_CLK_DMIC1>;
276 clock-names = "dmic";
277 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
278 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
279 assigned-clock-rates = <3072000>;
280 sound-name-prefix = "DMIC1";
281 status = "disabled";
282 };
283
284 tegra_dmic2: dmic@2904100 {
285 compatible = "nvidia,tegra234-dmic",
286 "nvidia,tegra210-dmic";
287 reg = <0x2904100 0x100>;
288 clocks = <&bpmp TEGRA234_CLK_DMIC2>;
289 clock-names = "dmic";
290 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
291 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
292 assigned-clock-rates = <3072000>;
293 sound-name-prefix = "DMIC2";
294 status = "disabled";
295 };
296
297 tegra_dmic3: dmic@2904200 {
298 compatible = "nvidia,tegra234-dmic",
299 "nvidia,tegra210-dmic";
300 reg = <0x2904200 0x100>;
301 clocks = <&bpmp TEGRA234_CLK_DMIC3>;
302 clock-names = "dmic";
303 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
304 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
305 assigned-clock-rates = <3072000>;
306 sound-name-prefix = "DMIC3";
307 status = "disabled";
308 };
309
310 tegra_dmic4: dmic@2904300 {
311 compatible = "nvidia,tegra234-dmic",
312 "nvidia,tegra210-dmic";
313 reg = <0x2904300 0x100>;
314 clocks = <&bpmp TEGRA234_CLK_DMIC4>;
315 clock-names = "dmic";
316 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
317 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
318 assigned-clock-rates = <3072000>;
319 sound-name-prefix = "DMIC4";
320 status = "disabled";
321 };
322
323 tegra_dspk1: dspk@2905000 {
324 compatible = "nvidia,tegra234-dspk",
325 "nvidia,tegra186-dspk";
326 reg = <0x2905000 0x100>;
327 clocks = <&bpmp TEGRA234_CLK_DSPK1>;
328 clock-names = "dspk";
329 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
330 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
331 assigned-clock-rates = <12288000>;
332 sound-name-prefix = "DSPK1";
333 status = "disabled";
334 };
335
336 tegra_dspk2: dspk@2905100 {
337 compatible = "nvidia,tegra234-dspk",
338 "nvidia,tegra186-dspk";
339 reg = <0x2905100 0x100>;
340 clocks = <&bpmp TEGRA234_CLK_DSPK2>;
341 clock-names = "dspk";
342 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
343 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
344 assigned-clock-rates = <12288000>;
345 sound-name-prefix = "DSPK2";
346 status = "disabled";
347 };
348
4b6a1b7c
SP		 349 tegra_ope1: processing-engine@2908000 {
350 compatible = "nvidia,tegra234-ope",
351 "nvidia,tegra210-ope";
352 reg = <0x2908000 0x100>;
353 #address-cells = <1>;
354 #size-cells = <1>;
355 ranges;
356 sound-name-prefix = "OPE1";
357 status = "disabled";
358
359 equalizer@2908100 {
360 compatible = "nvidia,tegra234-peq",
361 "nvidia,tegra210-peq";
362 reg = <0x2908100 0x100>;
363 };
364
365 dynamic-range-compressor@2908200 {
366 compatible = "nvidia,tegra234-mbdrc",
367 "nvidia,tegra210-mbdrc";
368 reg = <0x2908200 0x200>;
369 };
370 };
371
dc94a94d
SP		 372 tegra_mvc1: mvc@290a000 {
373 compatible = "nvidia,tegra234-mvc",
374 "nvidia,tegra210-mvc";
375 reg = <0x290a000 0x200>;
376 sound-name-prefix = "MVC1";
377 status = "disabled";
378 };
379
380 tegra_mvc2: mvc@290a200 {
381 compatible = "nvidia,tegra234-mvc",
382 "nvidia,tegra210-mvc";
383 reg = <0x290a200 0x200>;
384 sound-name-prefix = "MVC2";
385 status = "disabled";
386 };
387
388 tegra_amixer: amixer@290bb00 {
389 compatible = "nvidia,tegra234-amixer",
390 "nvidia,tegra210-amixer";
391 reg = <0x290bb00 0x800>;
392 sound-name-prefix = "MIXER1";
393 status = "disabled";
394 };
395
396 tegra_admaif: admaif@290f000 {
397 compatible = "nvidia,tegra234-admaif",
398 "nvidia,tegra186-admaif";
399 reg = <0x0290f000 0x1000>;
400 dmas = <&adma 1>, <&adma 1>,
401 <&adma 2>, <&adma 2>,
402 <&adma 3>, <&adma 3>,
403 <&adma 4>, <&adma 4>,
404 <&adma 5>, <&adma 5>,
405 <&adma 6>, <&adma 6>,
406 <&adma 7>, <&adma 7>,
407 <&adma 8>, <&adma 8>,
408 <&adma 9>, <&adma 9>,
409 <&adma 10>, <&adma 10>,
410 <&adma 11>, <&adma 11>,
411 <&adma 12>, <&adma 12>,
412 <&adma 13>, <&adma 13>,
413 <&adma 14>, <&adma 14>,
414 <&adma 15>, <&adma 15>,
415 <&adma 16>, <&adma 16>,
416 <&adma 17>, <&adma 17>,
417 <&adma 18>, <&adma 18>,
418 <&adma 19>, <&adma 19>,
419 <&adma 20>, <&adma 20>;
420 dma-names = "rx1", "tx1",
421 "rx2", "tx2",
422 "rx3", "tx3",
423 "rx4", "tx4",
424 "rx5", "tx5",
425 "rx6", "tx6",
426 "rx7", "tx7",
427 "rx8", "tx8",
428 "rx9", "tx9",
429 "rx10", "tx10",
430 "rx11", "tx11",
431 "rx12", "tx12",
432 "rx13", "tx13",
433 "rx14", "tx14",
434 "rx15", "tx15",
435 "rx16", "tx16",
436 "rx17", "tx17",
437 "rx18", "tx18",
438 "rx19", "tx19",
439 "rx20", "tx20";
440 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
441 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
442 interconnect-names = "dma-mem", "write";
443 iommus = <&smmu_niso0 TEGRA234_SID_APE>;
444 status = "disabled";
445 };
47a08153
SP		 446
447 tegra_asrc: asrc@2910000 {
448 compatible = "nvidia,tegra234-asrc",
449 "nvidia,tegra186-asrc";
450 reg = <0x2910000 0x2000>;
451 sound-name-prefix = "ASRC1";
452 status = "disabled";
453 };
dc94a94d
SP		 454 };
455
456 adma: dma-controller@2930000 {
457 compatible = "nvidia,tegra234-adma",
458 "nvidia,tegra186-adma";
459 reg = <0x02930000 0x20000>;
460 interrupt-parent = <&agic>;
461 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
462 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
466 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
467 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
493 #dma-cells = <1>;
494 clocks = <&bpmp TEGRA234_CLK_AHUB>;
495 clock-names = "d_audio";
496 status = "disabled";
497 };
498
499 agic: interrupt-controller@2a40000 {
500 compatible = "nvidia,tegra234-agic",
501 "nvidia,tegra210-agic";
502 #interrupt-cells = <3>;
503 interrupt-controller;
504 reg = <0x02a41000 0x1000>,
505 <0x02a42000 0x2000>;
506 interrupts = <GIC_SPI 145
507 (GIC_CPU_MASK_SIMPLE(4) |
508 IRQ_TYPE_LEVEL_HIGH)>;
509 clocks = <&bpmp TEGRA234_CLK_APE>;
510 clock-names = "clk";
511 status = "disabled";
512 };
513 };
514
63944891
TR		 515 misc@100000 {
516 compatible = "nvidia,tegra234-misc";
517 reg = <0x00100000 0xf000>,
518 <0x0010f000 0x1000>;
519 status = "okay";
520 };
521
28d860ed
K		 522 timer@2080000 {
523 compatible = "nvidia,tegra234-timer";
524 reg = <0x02080000 0x00121000>;
525 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
526 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
527 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
531 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
541 status = "okay";
542 };
543
4bb39ca2
MP		 544 host1x@13e00000 {
545 compatible = "nvidia,tegra234-host1x";
546 reg = <0x13e00000 0x10000>,
547 <0x13e10000 0x10000>,
548 <0x13e40000 0x10000>;
549 reg-names = "common", "hypervisor", "vm";
550 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
551 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
552 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
553 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
559 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
560 "syncpt5", "syncpt6", "syncpt7", "host1x";
561 clocks = <&bpmp TEGRA234_CLK_HOST1X>;
562 clock-names = "host1x";
563
564 #address-cells = <1>;
565 #size-cells = <1>;
566
e25770fe 567 ranges = <0x14800000 0x14800000 0x02000000>;
4bb39ca2
MP		 568 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
569 interconnect-names = "dma-mem";
570 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
571
b35f5b53
MP		 572 /* Context isolation domains */
573 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
574 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
575 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
576 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
577 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
578 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
579 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
580 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
581 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
582 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
583 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
584 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
585 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
586 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
587 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
588 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
589
4bb39ca2
MP		 590 vic@15340000 {
591 compatible = "nvidia,tegra234-vic";
592 reg = <0x15340000 0x00040000>;
593 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&bpmp TEGRA234_CLK_VIC>;
595 clock-names = "vic";
596 resets = <&bpmp TEGRA234_RESET_VIC>;
597 reset-names = "vic";
598
599 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
600 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>,
601 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>;
602 interconnect-names = "dma-mem", "write";
603 iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
604 dma-coherent;
605 };
68c31ad0
MP		 606
607 nvdec@15480000 {
608 compatible = "nvidia,tegra234-nvdec";
609 reg = <0x15480000 0x00040000>;
610 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
611 <&bpmp TEGRA234_CLK_FUSE>,
612 <&bpmp TEGRA234_CLK_TSEC_PKA>;
613 clock-names = "nvdec", "fuse", "tsec_pka";
614 resets = <&bpmp TEGRA234_RESET_NVDEC>;
615 reset-names = "nvdec";
616 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
617 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
618 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
619 interconnect-names = "dma-mem", "write";
620 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
621 dma-coherent;
622
623 nvidia,memory-controller = <&mc>;
624
625 /*
626 * Placeholder values that firmware needs to update with the real
627 * offsets parsed from the microcode headers.
628 */
629 nvidia,bl-manifest-offset = <0>;
630 nvidia,bl-data-offset = <0>;
631 nvidia,bl-code-offset = <0>;
632 nvidia,os-manifest-offset = <0>;
633 nvidia,os-data-offset = <0>;
634 nvidia,os-code-offset = <0>;
635
636 /*
637 * Firmware needs to set this to "okay" once the above values have
638 * been updated.
639 */
640 status = "disabled";
641 };
4bb39ca2
MP		 642 };
643
f0e12668
TR		 644 gpio: gpio@2200000 {
645 compatible = "nvidia,tegra234-gpio";
646 reg-names = "security", "gpio";
647 reg = <0x02200000 0x10000>,
648 <0x02210000 0x10000>;
649 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
650 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
651 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
652 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
654 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
655 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
697 #interrupt-cells = <2>;
698 interrupt-controller;
699 #gpio-cells = <2>;
700 gpio-controller;
701 };
702
eed280df
TR		 703 mc: memory-controller@2c00000 {
704 compatible = "nvidia,tegra234-mc";
000b99e5
AM		 705 reg = <0x02c00000 0x10000>, /* MC-SID */
706 <0x02c10000 0x10000>, /* MC Broadcast*/
707 <0x02c20000 0x10000>, /* MC0 */
708 <0x02c30000 0x10000>, /* MC1 */
709 <0x02c40000 0x10000>, /* MC2 */
710 <0x02c50000 0x10000>, /* MC3 */
711 <0x02b80000 0x10000>, /* MC4 */
712 <0x02b90000 0x10000>, /* MC5 */
713 <0x02ba0000 0x10000>, /* MC6 */
714 <0x02bb0000 0x10000>, /* MC7 */
715 <0x01700000 0x10000>, /* MC8 */
716 <0x01710000 0x10000>, /* MC9 */
717 <0x01720000 0x10000>, /* MC10 */
718 <0x01730000 0x10000>, /* MC11 */
719 <0x01740000 0x10000>, /* MC12 */
720 <0x01750000 0x10000>, /* MC13 */
721 <0x01760000 0x10000>, /* MC14 */
722 <0x01770000 0x10000>; /* MC15 */
723 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
724 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
725 "ch11", "ch12", "ch13", "ch14", "ch15";
eed280df
TR		 726 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
727 #interconnect-cells = <1>;
728 status = "okay";
729
730 #address-cells = <2>;
731 #size-cells = <2>;
732
733 ranges = <0x01700000 0x0 0x01700000 0x0 0x100000>,
734 <0x02b80000 0x0 0x02b80000 0x0 0x040000>,
735 <0x02c00000 0x0 0x02c00000 0x0 0x100000>;
736
737 /*
738 * Bit 39 of addresses passing through the memory
739 * controller selects the XBAR format used when memory
740 * is accessed. This is used to transparently access
741 * memory in the XBAR format used by the discrete GPU
742 * (bit 39 set) or Tegra (bit 39 clear).
743 *
744 * As a consequence, the operating system must ensure
745 * that bit 39 is never used implicitly, for example
746 * via an I/O virtual address mapping of an IOMMU. If
747 * devices require access to the XBAR switch, their
748 * drivers must set this bit explicitly.
749 *
750 * Limit the DMA range for memory clients to [38:0].
751 */
752 dma-ranges = <0x0 0x0 0x0 0x80 0x0>;
753
754 emc: external-memory-controller@2c60000 {
755 compatible = "nvidia,tegra234-emc";
756 reg = <0x0 0x02c60000 0x0 0x90000>,
757 <0x0 0x01780000 0x0 0x80000>;
758 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&bpmp TEGRA234_CLK_EMC>;
760 clock-names = "emc";
761 status = "okay";
762
763 #interconnect-cells = <0>;
764
765 nvidia,bpmp = <&bpmp>;
766 };
767 };
768
63944891
TR		 769 uarta: serial@3100000 {
770 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
771 reg = <0x03100000 0x10000>;
772 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&bpmp TEGRA234_CLK_UARTA>;
774 clock-names = "serial";
775 resets = <&bpmp TEGRA234_RESET_UARTA>;
776 reset-names = "serial";
777 status = "disabled";
778 };
779
156af9de
A		 780 gen1_i2c: i2c@3160000 {
781 compatible = "nvidia,tegra194-i2c";
782 reg = <0x3160000 0x100>;
783 status = "disabled";
784 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
785 clock-frequency = <400000>;
786 clocks = <&bpmp TEGRA234_CLK_I2C1
787 &bpmp TEGRA234_CLK_PLLP_OUT0>;
788 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
789 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
790 clock-names = "div-clk", "parent";
791 resets = <&bpmp TEGRA234_RESET_I2C1>;
792 reset-names = "i2c";
8e442805
A		 793 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
794 dma-coherent;
795 dmas = <&gpcdma 21>, <&gpcdma 21>;
796 dma-names = "rx", "tx";
156af9de
A		 797 };
798
799 cam_i2c: i2c@3180000 {
800 compatible = "nvidia,tegra194-i2c";
801 reg = <0x3180000 0x100>;
802 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
803 status = "disabled";
804 clock-frequency = <400000>;
805 clocks = <&bpmp TEGRA234_CLK_I2C3
806 &bpmp TEGRA234_CLK_PLLP_OUT0>;
807 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
808 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
809 clock-names = "div-clk", "parent";
810 resets = <&bpmp TEGRA234_RESET_I2C3>;
811 reset-names = "i2c";
8e442805
A		 812 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
813 dma-coherent;
814 dmas = <&gpcdma 23>, <&gpcdma 23>;
815 dma-names = "rx", "tx";
156af9de
A		 816 };
817
818 dp_aux_ch1_i2c: i2c@3190000 {
819 compatible = "nvidia,tegra194-i2c";
820 reg = <0x3190000 0x100>;
821 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
822 status = "disabled";
823 clock-frequency = <100000>;
824 clocks = <&bpmp TEGRA234_CLK_I2C4
825 &bpmp TEGRA234_CLK_PLLP_OUT0>;
826 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
827 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
828 clock-names = "div-clk", "parent";
829 resets = <&bpmp TEGRA234_RESET_I2C4>;
830 reset-names = "i2c";
8e442805
A		 831 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
832 dma-coherent;
833 dmas = <&gpcdma 26>, <&gpcdma 26>;
834 dma-names = "rx", "tx";
156af9de
A		 835 };
836
837 dp_aux_ch0_i2c: i2c@31b0000 {
838 compatible = "nvidia,tegra194-i2c";
839 reg = <0x31b0000 0x100>;
840 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
841 status = "disabled";
842 clock-frequency = <100000>;
843 clocks = <&bpmp TEGRA234_CLK_I2C6
844 &bpmp TEGRA234_CLK_PLLP_OUT0>;
845 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
846 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
847 clock-names = "div-clk", "parent";
848 resets = <&bpmp TEGRA234_RESET_I2C6>;
849 reset-names = "i2c";
8e442805
A		 850 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
851 dma-coherent;
852 dmas = <&gpcdma 30>, <&gpcdma 30>;
853 dma-names = "rx", "tx";
156af9de
A		 854 };
855
856 dp_aux_ch2_i2c: i2c@31c0000 {
857 compatible = "nvidia,tegra194-i2c";
858 reg = <0x31c0000 0x100>;
859 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
860 status = "disabled";
861 clock-frequency = <100000>;
862 clocks = <&bpmp TEGRA234_CLK_I2C7
863 &bpmp TEGRA234_CLK_PLLP_OUT0>;
864 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
865 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
866 clock-names = "div-clk", "parent";
867 resets = <&bpmp TEGRA234_RESET_I2C7>;
868 reset-names = "i2c";
8e442805
A		 869 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
870 dma-coherent;
871 dmas = <&gpcdma 27>, <&gpcdma 27>;
872 dma-names = "rx", "tx";
156af9de
A		 873 };
874
875 dp_aux_ch3_i2c: i2c@31e0000 {
876 compatible = "nvidia,tegra194-i2c";
877 reg = <0x31e0000 0x100>;
878 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
879 status = "disabled";
880 clock-frequency = <100000>;
881 clocks = <&bpmp TEGRA234_CLK_I2C9
882 &bpmp TEGRA234_CLK_PLLP_OUT0>;
883 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
884 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
885 clock-names = "div-clk", "parent";
886 resets = <&bpmp TEGRA234_RESET_I2C9>;
887 reset-names = "i2c";
8e442805
A		 888 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
889 dma-coherent;
890 dmas = <&gpcdma 31>, <&gpcdma 31>;
891 dma-names = "rx", "tx";
156af9de
A		 892 };
893
71f69ffa
AS		 894 spi@3270000 {
895 compatible = "nvidia,tegra234-qspi";
896 reg = <0x3270000 0x1000>;
897 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
898 #address-cells = <1>;
899 #size-cells = <0>;
900 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
901 <&bpmp TEGRA234_CLK_QSPI0_PM>;
902 clock-names = "qspi", "qspi_out";
903 resets = <&bpmp TEGRA234_RESET_QSPI0>;
904 reset-names = "qspi";
905 status = "disabled";
906 };
907
5e69088d
A		 908 pwm1: pwm@3280000 {
909 compatible = "nvidia,tegra194-pwm",
910 "nvidia,tegra186-pwm";
911 reg = <0x3280000 0x10000>;
912 clocks = <&bpmp TEGRA234_CLK_PWM1>;
913 clock-names = "pwm";
914 resets = <&bpmp TEGRA234_RESET_PWM1>;
915 reset-names = "pwm";
916 status = "disabled";
917 #pwm-cells = <2>;
918 };
919
71f69ffa
AS		 920 spi@3300000 {
921 compatible = "nvidia,tegra234-qspi";
922 reg = <0x3300000 0x1000>;
923 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
924 #address-cells = <1>;
925 #size-cells = <0>;
926 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
927 <&bpmp TEGRA234_CLK_QSPI1_PM>;
928 clock-names = "qspi", "qspi_out";
929 resets = <&bpmp TEGRA234_RESET_QSPI1>;
930 reset-names = "qspi";
931 status = "disabled";
932 };
933
63944891
TR		 934 mmc@3460000 {
935 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
936 reg = <0x03460000 0x20000>;
937 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
e086d82d
MP		 938 clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
939 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
940 clock-names = "sdhci", "tmclk";
941 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
942 <&bpmp TEGRA234_CLK_PLLC4>;
943 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
63944891
TR		 944 resets = <&bpmp TEGRA234_RESET_SDMMC4>;
945 reset-names = "sdhci";
6de481e5
TR		 946 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
947 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
948 interconnect-names = "dma-mem", "write";
5710e16a 949 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
e086d82d
MP		 950 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
951 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
952 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
953 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
954 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
955 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
956 nvidia,default-tap = <0x8>;
957 nvidia,default-trim = <0x14>;
958 nvidia,dqs-trim = <40>;
959 supports-cqe;
63944891
TR		 960 status = "disabled";
961 };
962
621e12a1
MK		 963 hda@3510000 {
964 compatible = "nvidia,tegra234-hda", "nvidia,tegra30-hda";
965 reg = <0x3510000 0x10000>;
966 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
967 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
968 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
969 clock-names = "hda", "hda2codec_2x";
970 resets = <&bpmp TEGRA234_RESET_HDA>,
971 <&bpmp TEGRA234_RESET_HDACODEC>;
972 reset-names = "hda", "hda2codec_2x";
973 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
974 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
975 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
976 interconnect-names = "dma-mem", "write";
af4c2773 977 iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
621e12a1
MK		 978 status = "disabled";
979 };
980
63944891
TR		 981 fuse@3810000 {
982 compatible = "nvidia,tegra234-efuse";
983 reg = <0x03810000 0x10000>;
984 clocks = <&bpmp TEGRA234_CLK_FUSE>;
985 clock-names = "fuse";
986 };
987
988 hsp_top0: hsp@3c00000 {
989 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
990 reg = <0x03c00000 0xa0000>;
991 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
995 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
996 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
997 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
998 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
999 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1000 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1001 "shared3", "shared4", "shared5", "shared6",
1002 "shared7";
1003 #mbox-cells = <2>;
1004 };
1005
610cdf31
TR		 1006 ethernet@6800000 {
1007 compatible = "nvidia,tegra234-mgbe";
1008 reg = <0x06800000 0x10000>,
1009 <0x06810000 0x10000>,
1010 <0x068a0000 0x10000>;
1011 reg-names = "hypervisor", "mac", "xpcs";
1012 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
1013 interrupt-names = "common";
1014 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
1015 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
1016 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
1017 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
1018 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
1019 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
1020 <&bpmp TEGRA234_CLK_MGBE0_TX>,
1021 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
1022 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
1023 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
1024 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
1025 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
1026 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1027 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1028 "rx-pcs", "tx-pcs";
1029 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
1030 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
1031 reset-names = "mac", "pcs";
1032 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
1033 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
1034 interconnect-names = "dma-mem", "write";
1035 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
1036 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1037 status = "disabled";
1038 };
1039
1040 ethernet@6900000 {
1041 compatible = "nvidia,tegra234-mgbe";
1042 reg = <0x06900000 0x10000>,
1043 <0x06910000 0x10000>,
1044 <0x069a0000 0x10000>;
1045 reg-names = "hypervisor", "mac", "xpcs";
1046 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
1047 interrupt-names = "common";
1048 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1049 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1050 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1051 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1052 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1053 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1054 <&bpmp TEGRA234_CLK_MGBE1_TX>,
1055 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1056 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1057 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1058 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1059 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1060 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1061 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1062 "rx-pcs", "tx-pcs";
1063 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1064 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1065 reset-names = "mac", "pcs";
1066 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
1067 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
1068 interconnect-names = "dma-mem", "write";
1069 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
1070 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1071 status = "disabled";
1072 };
1073
1074 ethernet@6a00000 {
1075 compatible = "nvidia,tegra234-mgbe";
1076 reg = <0x06a00000 0x10000>,
1077 <0x06a10000 0x10000>,
1078 <0x06aa0000 0x10000>;
1079 reg-names = "hypervisor", "mac", "xpcs";
1080 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
1081 interrupt-names = "common";
1082 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1083 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1084 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1085 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1086 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1087 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1088 <&bpmp TEGRA234_CLK_MGBE2_TX>,
1089 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1090 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1091 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1092 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1093 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1094 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1095 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1096 "rx-pcs", "tx-pcs";
1097 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1098 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1099 reset-names = "mac", "pcs";
1100 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
1101 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
1102 interconnect-names = "dma-mem", "write";
1103 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
1104 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1105 status = "disabled";
1106 };
1107
1108 ethernet@6b00000 {
1109 compatible = "nvidia,tegra234-mgbe";
1110 reg = <0x06b00000 0x10000>,
1111 <0x06b10000 0x10000>,
1112 <0x06ba0000 0x10000>;
1113 reg-names = "hypervisor", "mac", "xpcs";
1114 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1115 interrupt-names = "common";
1116 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1117 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1118 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1119 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1120 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1121 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1122 <&bpmp TEGRA234_CLK_MGBE3_TX>,
1123 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1124 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1125 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1126 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1127 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1128 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1129 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1130 "rx-pcs", "tx-pcs";
1131 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1132 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1133 reset-names = "mac", "pcs";
1134 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
1135 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
1136 interconnect-names = "dma-mem", "write";
1137 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
1138 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1139 status = "disabled";
1140 };
1141
5710e16a
TR		 1142 smmu_niso1: iommu@8000000 {
1143 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1144 reg = <0x8000000 0x1000000>,
1145 <0x7000000 0x1000000>;
1146 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1147 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1148 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1149 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1150 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1151 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1152 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1153 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1154 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1155 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1156 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1157 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1158 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1159 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1160 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1161 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1162 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1163 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1164 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1165 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1166 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1167 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1168 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1169 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1170 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1172 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1173 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1174 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1175 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1176 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1177 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1178 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1180 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1181 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1185 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1194 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1195 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1196 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1197 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1198 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1199 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1200 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1201 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1202 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1203 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1204 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1205 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1206 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1207 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1208 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1209 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1210 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1211 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1212 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1213 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1214 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1215 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1216 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1217 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1218 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1219 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1220 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1221 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1222 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1223 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1224 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1225 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1226 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1227 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1228 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1229 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1230 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1231 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1232 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1233 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1234 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1235 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1236 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1237 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1238 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1239 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1240 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1241 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1242 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1243 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1244 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1245 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1246 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1247 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1248 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1249 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1250 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1251 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1252 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1253 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1254 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1255 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1256 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1257 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1258 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1259 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1260 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1261 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1262 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1263 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1264 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1265 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1266 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1267 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1268 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1269 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1270 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1271 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1272 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1273 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1274 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1275 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1276 stream-match-mask = <0x7f80>;
1277 #global-interrupts = <2>;
1278 #iommu-cells = <1>;
1279
1280 nvidia,memory-controller = <&mc>;
1281 status = "okay";
1282 };
1283
302e1540
SG		 1284 sce-fabric@b600000 {
1285 compatible = "nvidia,tegra234-sce-fabric";
1286 reg = <0xb600000 0x40000>;
1287 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
1288 status = "okay";
1289 };
1290
1291 rce-fabric@be00000 {
1292 compatible = "nvidia,tegra234-rce-fabric";
1293 reg = <0xbe00000 0x40000>;
1294 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1295 status = "okay";
1296 };
1297
ec142c44
VS		 1298 p2u_hsio_0: phy@3e00000 {
1299 compatible = "nvidia,tegra234-p2u";
1300 reg = <0x03e00000 0x10000>;
1301 reg-names = "ctl";
1302
1303 #phy-cells = <0>;
1304 };
1305
1306 p2u_hsio_1: phy@3e10000 {
1307 compatible = "nvidia,tegra234-p2u";
1308 reg = <0x03e10000 0x10000>;
1309 reg-names = "ctl";
1310
1311 #phy-cells = <0>;
1312 };
1313
1314 p2u_hsio_2: phy@3e20000 {
1315 compatible = "nvidia,tegra234-p2u";
1316 reg = <0x03e20000 0x10000>;
1317 reg-names = "ctl";
1318
1319 #phy-cells = <0>;
1320 };
1321
1322 p2u_hsio_3: phy@3e30000 {
1323 compatible = "nvidia,tegra234-p2u";
1324 reg = <0x03e30000 0x10000>;
1325 reg-names = "ctl";
1326
1327 #phy-cells = <0>;
1328 };
1329
1330 p2u_hsio_4: phy@3e40000 {
1331 compatible = "nvidia,tegra234-p2u";
1332 reg = <0x03e40000 0x10000>;
1333 reg-names = "ctl";
1334
1335 #phy-cells = <0>;
1336 };
1337
1338 p2u_hsio_5: phy@3e50000 {
1339 compatible = "nvidia,tegra234-p2u";
1340 reg = <0x03e50000 0x10000>;
1341 reg-names = "ctl";
1342
1343 #phy-cells = <0>;
1344 };
1345
1346 p2u_hsio_6: phy@3e60000 {
1347 compatible = "nvidia,tegra234-p2u";
1348 reg = <0x03e60000 0x10000>;
1349 reg-names = "ctl";
1350
1351 #phy-cells = <0>;
1352 };
1353
1354 p2u_hsio_7: phy@3e70000 {
1355 compatible = "nvidia,tegra234-p2u";
1356 reg = <0x03e70000 0x10000>;
1357 reg-names = "ctl";
1358
1359 #phy-cells = <0>;
1360 };
1361
1362 p2u_nvhs_0: phy@3e90000 {
1363 compatible = "nvidia,tegra234-p2u";
1364 reg = <0x03e90000 0x10000>;
1365 reg-names = "ctl";
1366
1367 #phy-cells = <0>;
1368 };
1369
1370 p2u_nvhs_1: phy@3ea0000 {
1371 compatible = "nvidia,tegra234-p2u";
1372 reg = <0x03ea0000 0x10000>;
1373 reg-names = "ctl";
1374
1375 #phy-cells = <0>;
1376 };
1377
1378 p2u_nvhs_2: phy@3eb0000 {
1379 compatible = "nvidia,tegra234-p2u";
1380 reg = <0x03eb0000 0x10000>;
1381 reg-names = "ctl";
1382
1383 #phy-cells = <0>;
1384 };
1385
1386 p2u_nvhs_3: phy@3ec0000 {
1387 compatible = "nvidia,tegra234-p2u";
1388 reg = <0x03ec0000 0x10000>;
1389 reg-names = "ctl";
1390
1391 #phy-cells = <0>;
1392 };
1393
1394 p2u_nvhs_4: phy@3ed0000 {
1395 compatible = "nvidia,tegra234-p2u";
1396 reg = <0x03ed0000 0x10000>;
1397 reg-names = "ctl";
1398
1399 #phy-cells = <0>;
1400 };
1401
1402 p2u_nvhs_5: phy@3ee0000 {
1403 compatible = "nvidia,tegra234-p2u";
1404 reg = <0x03ee0000 0x10000>;
1405 reg-names = "ctl";
1406
1407 #phy-cells = <0>;
1408 };
1409
1410 p2u_nvhs_6: phy@3ef0000 {
1411 compatible = "nvidia,tegra234-p2u";
1412 reg = <0x03ef0000 0x10000>;
1413 reg-names = "ctl";
1414
1415 #phy-cells = <0>;
1416 };
1417
1418 p2u_nvhs_7: phy@3f00000 {
1419 compatible = "nvidia,tegra234-p2u";
1420 reg = <0x03f00000 0x10000>;
1421 reg-names = "ctl";
1422
1423 #phy-cells = <0>;
1424 };
1425
1426 p2u_gbe_0: phy@3f20000 {
1427 compatible = "nvidia,tegra234-p2u";
1428 reg = <0x03f20000 0x10000>;
1429 reg-names = "ctl";
1430
1431 #phy-cells = <0>;
1432 };
1433
1434 p2u_gbe_1: phy@3f30000 {
1435 compatible = "nvidia,tegra234-p2u";
1436 reg = <0x03f30000 0x10000>;
1437 reg-names = "ctl";
1438
1439 #phy-cells = <0>;
1440 };
1441
1442 p2u_gbe_2: phy@3f40000 {
1443 compatible = "nvidia,tegra234-p2u";
1444 reg = <0x03f40000 0x10000>;
1445 reg-names = "ctl";
1446
1447 #phy-cells = <0>;
1448 };
1449
1450 p2u_gbe_3: phy@3f50000 {
1451 compatible = "nvidia,tegra234-p2u";
1452 reg = <0x03f50000 0x10000>;
1453 reg-names = "ctl";
1454
1455 #phy-cells = <0>;
1456 };
1457
1458 p2u_gbe_4: phy@3f60000 {
1459 compatible = "nvidia,tegra234-p2u";
1460 reg = <0x03f60000 0x10000>;
1461 reg-names = "ctl";
1462
1463 #phy-cells = <0>;
1464 };
1465
1466 p2u_gbe_5: phy@3f70000 {
1467 compatible = "nvidia,tegra234-p2u";
1468 reg = <0x03f70000 0x10000>;
1469 reg-names = "ctl";
1470
1471 #phy-cells = <0>;
1472 };
1473
1474 p2u_gbe_6: phy@3f80000 {
1475 compatible = "nvidia,tegra234-p2u";
1476 reg = <0x03f80000 0x10000>;
1477 reg-names = "ctl";
1478
1479 #phy-cells = <0>;
1480 };
1481
1482 p2u_gbe_7: phy@3f90000 {
1483 compatible = "nvidia,tegra234-p2u";
1484 reg = <0x03f90000 0x10000>;
1485 reg-names = "ctl";
1486
1487 #phy-cells = <0>;
1488 };
1489
63944891
TR		 1490 hsp_aon: hsp@c150000 {
1491 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
1492 reg = <0x0c150000 0x90000>;
1493 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1497 /*
1498 * Shared interrupt 0 is routed only to AON/SPE, so
1499 * we only have 4 shared interrupts for the CCPLEX.
1500 */
1501 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1502 #mbox-cells = <2>;
1503 };
1504
156af9de
A		 1505 gen2_i2c: i2c@c240000 {
1506 compatible = "nvidia,tegra194-i2c";
1507 reg = <0xc240000 0x100>;
1508 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1509 status = "disabled";
1510 clock-frequency = <100000>;
1511 clocks = <&bpmp TEGRA234_CLK_I2C2
1512 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1513 clock-names = "div-clk", "parent";
1514 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1515 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1516 resets = <&bpmp TEGRA234_RESET_I2C2>;
1517 reset-names = "i2c";
8e442805
A		 1518 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
1519 dma-coherent;
1520 dmas = <&gpcdma 22>, <&gpcdma 22>;
1521 dma-names = "rx", "tx";
156af9de
A		 1522 };
1523
1524 gen8_i2c: i2c@c250000 {
1525 compatible = "nvidia,tegra194-i2c";
1526 reg = <0xc250000 0x100>;
156af9de
A		 1527 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1528 status = "disabled";
1529 clock-frequency = <400000>;
1530 clocks = <&bpmp TEGRA234_CLK_I2C8
1531 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1532 clock-names = "div-clk", "parent";
1533 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1534 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1535 resets = <&bpmp TEGRA234_RESET_I2C8>;
1536 reset-names = "i2c";
8e442805
A		 1537 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
1538 dma-coherent;
1539 dmas = <&gpcdma 0>, <&gpcdma 0>;
1540 dma-names = "rx", "tx";
156af9de
A		 1541 };
1542
63944891
TR		 1543 rtc@c2a0000 {
1544 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
1545 reg = <0x0c2a0000 0x10000>;
1546 interrupt-parent = <&pmc>;
1547 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
e537adde
MP		 1548 clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1549 clock-names = "rtc";
63944891
TR		 1550 status = "disabled";
1551 };
1552
f0e12668
TR		 1553 gpio_aon: gpio@c2f0000 {
1554 compatible = "nvidia,tegra234-gpio-aon";
1555 reg-names = "security", "gpio";
1556 reg = <0x0c2f0000 0x1000>,
1557 <0x0c2f1000 0x1000>;
1558 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1562 #interrupt-cells = <2>;
1563 interrupt-controller;
1564 #gpio-cells = <2>;
1565 gpio-controller;
1566 };
1567
63944891
TR		 1568 pmc: pmc@c360000 {
1569 compatible = "nvidia,tegra234-pmc";
1570 reg = <0x0c360000 0x10000>,
1571 <0x0c370000 0x10000>,
1572 <0x0c380000 0x10000>,
1573 <0x0c390000 0x10000>,
1574 <0x0c3a0000 0x10000>;
1575 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1576
1577 #interrupt-cells = <2>;
1578 interrupt-controller;
1579 };
1580
302e1540
SG		 1581 aon-fabric@c600000 {
1582 compatible = "nvidia,tegra234-aon-fabric";
1583 reg = <0xc600000 0x40000>;
1584 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1585 status = "okay";
1586 };
1587
1588 bpmp-fabric@d600000 {
1589 compatible = "nvidia,tegra234-bpmp-fabric";
1590 reg = <0xd600000 0x40000>;
1591 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1592 status = "okay";
1593 };
1594
1595 dce-fabric@de00000 {
1596 compatible = "nvidia,tegra234-sce-fabric";
1597 reg = <0xde00000 0x40000>;
1598 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
1599 status = "okay";
1600 };
1601
63944891
TR		 1602 gic: interrupt-controller@f400000 {
1603 compatible = "arm,gic-v3";
1604 reg = <0x0f400000 0x010000>, /* GICD */
1605 <0x0f440000 0x200000>; /* GICR */
1606 interrupt-parent = <&gic>;
1607 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1608
1609 #redistributor-regions = <1>;
1610 #interrupt-cells = <3>;
1611 interrupt-controller;
1612 };
5710e16a
TR		 1613
1614 smmu_iso: iommu@10000000{
1615 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1616 reg = <0x10000000 0x1000000>;
1617 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1618 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1619 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1620 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1621 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1622 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1623 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1624 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1625 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1626 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1627 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1628 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1629 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1630 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1631 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1632 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1633 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1634 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1635 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1636 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1637 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1638 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1639 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1640 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1641 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1642 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1643 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1644 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1646 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1647 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1648 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1649 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1650 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1652 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1654 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1656 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1657 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1658 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1659 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1660 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1661 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1662 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1663 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1664 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1665 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1666 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1667 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1668 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1669 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1670 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1671 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1672 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1673 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1674 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1675 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1676 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1677 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1678 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1679 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1680 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1681 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1682 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1683 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1684 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1685 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1686 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1687 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1688 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1689 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1690 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1691 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1692 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1693 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1694 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1695 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1696 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1697 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1698 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1699 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1700 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1701 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1702 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1703 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1704 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1705 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1706 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1707 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1708 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1709 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1710 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1711 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1712 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1713 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1714 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1715 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1716 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1717 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1718 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1719 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1720 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1721 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1722 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1723 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1724 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1725 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1726 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1727 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1728 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1729 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1730 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1731 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1732 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1733 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1734 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1735 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1737 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1738 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1739 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1740 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1741 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1742 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1743 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1744 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1745 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1746 stream-match-mask = <0x7f80>;
1747 #global-interrupts = <1>;
1748 #iommu-cells = <1>;
1749
1750 nvidia,memory-controller = <&mc>;
1751 status = "okay";
1752 };
1753
1754 smmu_niso0: iommu@12000000 {
1755 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
1756 reg = <0x12000000 0x1000000>,
1757 <0x11000000 0x1000000>;
1758 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1769 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1771 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1772 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1773 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1774 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1775 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1776 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1777 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1778 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1779 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1780 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1781 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1782 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1783 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1791 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1797 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1801 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1802 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1803 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1804 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1805 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1806 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1807 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1808 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1809 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1810 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1811 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1839 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1840 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1843 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1846 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1847 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1856 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1857 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1858 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1860 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1861 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1862 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1863 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1864 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1865 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1866 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1867 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1874 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1875 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1879 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1880 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1882 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1885 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1886 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1887 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1888 stream-match-mask = <0x7f80>;
1889 #global-interrupts = <2>;
1890 #iommu-cells = <1>;
1891
1892 nvidia,memory-controller = <&mc>;
1893 status = "okay";
1894 };
302e1540
SG		 1895
1896 cbb-fabric@13a00000 {
1897 compatible = "nvidia,tegra234-cbb-fabric";
1898 reg = <0x13a00000 0x400000>;
1899 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
1900 status = "okay";
1901 };
63944891
TR		 1902 };
1903
962c400d
SG		 1904 ccplex@e000000 {
1905 compatible = "nvidia,tegra234-ccplex-cluster";
1906 reg = <0x0 0x0e000000 0x0 0x5ffff>;
1907 nvidia,bpmp = <&bpmp>;
1908 status = "okay";
1909 };
1910
ec142c44
VS		 1911 pcie@140a0000 {
1912 compatible = "nvidia,tegra234-pcie";
1913 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
1914 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
1915 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
1916 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1917 <0x00 0x2a080000 0x0 0x00040000>; /* DBI reg space (256K) */
1918 reg-names = "appl", "config", "atu_dma", "dbi";
1919
1920 #address-cells = <3>;
1921 #size-cells = <2>;
1922 device_type = "pci";
1923 num-lanes = <4>;
1924 num-viewport = <8>;
1925 linux,pci-domain = <8>;
1926
1927 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
1928 clock-names = "core";
1929
1930 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
1931 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
1932 reset-names = "apb", "core";
1933
1934 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1935 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1936 interrupt-names = "intr", "msi";
1937
1938 #interrupt-cells = <1>;
1939 interrupt-map-mask = <0 0 0 0>;
1940 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1941
1942 nvidia,bpmp = <&bpmp 8>;
1943
1944 nvidia,aspm-cmrt-us = <60>;
1945 nvidia,aspm-pwr-on-t-us = <20>;
1946 nvidia,aspm-l0s-entrance-latency-us = <3>;
1947
1948 bus-range = <0x0 0xff>;
1949
1950 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
1951 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
1952 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
1953
1954 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
1955 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
1956 interconnect-names = "dma-mem", "write";
1957 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
1958 iommu-map-mask = <0x0>;
1959 dma-coherent;
1960
1961 status = "disabled";
1962 };
1963
1964 pcie@140c0000 {
1965 compatible = "nvidia,tegra234-pcie";
1966 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
1967 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
1968 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
1969 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
1970 <0x00 0x2c080000 0x0 0x00040000>; /* DBI reg space (256K) */
1971 reg-names = "appl", "config", "atu_dma", "dbi";
1972
1973 #address-cells = <3>;
1974 #size-cells = <2>;
1975 device_type = "pci";
1976 num-lanes = <4>;
1977 num-viewport = <8>;
1978 linux,pci-domain = <9>;
1979
1980 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
1981 clock-names = "core";
1982
1983 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
1984 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
1985 reset-names = "apb", "core";
1986
1987 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
1988 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
1989 interrupt-names = "intr", "msi";
1990
1991 #interrupt-cells = <1>;
1992 interrupt-map-mask = <0 0 0 0>;
1993 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1994
1995 nvidia,bpmp = <&bpmp 9>;
1996
1997 nvidia,aspm-cmrt-us = <60>;
1998 nvidia,aspm-pwr-on-t-us = <20>;
1999 nvidia,aspm-l0s-entrance-latency-us = <3>;
2000
2001 bus-range = <0x0 0xff>;
2002
24840065 2003 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
ec142c44
VS		 2004 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2005 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2006
2007 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
2008 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
2009 interconnect-names = "dma-mem", "write";
2010 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2011 iommu-map-mask = <0x0>;
2012 dma-coherent;
2013
2014 status = "disabled";
2015 };
2016
2017 pcie@140e0000 {
2018 compatible = "nvidia,tegra234-pcie";
2019 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2020 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2021 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
2022 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2023 <0x00 0x2e080000 0x0 0x00040000>; /* DBI reg space (256K) */
2024 reg-names = "appl", "config", "atu_dma", "dbi";
2025
2026 #address-cells = <3>;
2027 #size-cells = <2>;
2028 device_type = "pci";
2029 num-lanes = <4>;
2030 num-viewport = <8>;
2031 linux,pci-domain = <10>;
2032
2033 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2034 clock-names = "core";
2035
2036 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2037 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2038 reset-names = "apb", "core";
2039
2040 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2041 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2042 interrupt-names = "intr", "msi";
2043
2044 #interrupt-cells = <1>;
2045 interrupt-map-mask = <0 0 0 0>;
2046 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2047
2048 nvidia,bpmp = <&bpmp 10>;
2049
2050 nvidia,aspm-cmrt-us = <60>;
2051 nvidia,aspm-pwr-on-t-us = <20>;
2052 nvidia,aspm-l0s-entrance-latency-us = <3>;
2053
2054 bus-range = <0x0 0xff>;
2055
2056 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2057 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2058 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2059
2060 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2061 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2062 interconnect-names = "dma-mem", "write";
2063 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2064 iommu-map-mask = <0x0>;
2065 dma-coherent;
2066
2067 status = "disabled";
2068 };
2069
2070 pcie@14100000 {
2071 compatible = "nvidia,tegra234-pcie";
2072 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2073 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2074 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2075 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2076 <0x00 0x30080000 0x0 0x00040000>; /* DBI reg space (256K) */
2077 reg-names = "appl", "config", "atu_dma", "dbi";
2078
2079 #address-cells = <3>;
2080 #size-cells = <2>;
2081 device_type = "pci";
2082 num-lanes = <1>;
2083 num-viewport = <8>;
2084 linux,pci-domain = <1>;
2085
2086 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2087 clock-names = "core";
2088
2089 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2090 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2091 reset-names = "apb", "core";
2092
2093 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2094 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2095 interrupt-names = "intr", "msi";
2096
2097 #interrupt-cells = <1>;
2098 interrupt-map-mask = <0 0 0 0>;
2099 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2100
2101 nvidia,bpmp = <&bpmp 1>;
2102
2103 nvidia,aspm-cmrt-us = <60>;
2104 nvidia,aspm-pwr-on-t-us = <20>;
2105 nvidia,aspm-l0s-entrance-latency-us = <3>;
2106
2107 bus-range = <0x0 0xff>;
2108
2109 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2110 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2111 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2112
2113 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
2114 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
2115 interconnect-names = "dma-mem", "write";
2116 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2117 iommu-map-mask = <0x0>;
2118 dma-coherent;
2119
2120 status = "disabled";
2121 };
2122
2123 pcie@14120000 {
2124 compatible = "nvidia,tegra234-pcie";
2125 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2126 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2127 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2128 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2129 <0x00 0x32080000 0x0 0x00040000>; /* DBI reg space (256K) */
2130 reg-names = "appl", "config", "atu_dma", "dbi";
2131
2132 #address-cells = <3>;
2133 #size-cells = <2>;
2134 device_type = "pci";
2135 num-lanes = <1>;
2136 num-viewport = <8>;
2137 linux,pci-domain = <2>;
2138
2139 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2140 clock-names = "core";
2141
2142 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2143 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2144 reset-names = "apb", "core";
2145
2146 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2147 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2148 interrupt-names = "intr", "msi";
2149
2150 #interrupt-cells = <1>;
2151 interrupt-map-mask = <0 0 0 0>;
2152 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2153
2154 nvidia,bpmp = <&bpmp 2>;
2155
2156 nvidia,aspm-cmrt-us = <60>;
2157 nvidia,aspm-pwr-on-t-us = <20>;
2158 nvidia,aspm-l0s-entrance-latency-us = <3>;
2159
2160 bus-range = <0x0 0xff>;
2161
2162 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2163 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2164 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2165
2166 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
2167 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
2168 interconnect-names = "dma-mem", "write";
2169 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2170 iommu-map-mask = <0x0>;
2171 dma-coherent;
2172
2173 status = "disabled";
2174 };
2175
2176 pcie@14140000 {
2177 compatible = "nvidia,tegra234-pcie";
2178 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2179 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2180 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2181 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2182 <0x00 0x34080000 0x0 0x00040000>; /* DBI reg space (256K) */
2183 reg-names = "appl", "config", "atu_dma", "dbi";
2184
2185 #address-cells = <3>;
2186 #size-cells = <2>;
2187 device_type = "pci";
2188 num-lanes = <1>;
2189 num-viewport = <8>;
2190 linux,pci-domain = <3>;
2191
2192 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2193 clock-names = "core";
2194
2195 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2196 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2197 reset-names = "apb", "core";
2198
2199 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2200 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2201 interrupt-names = "intr", "msi";
2202
2203 #interrupt-cells = <1>;
2204 interrupt-map-mask = <0 0 0 0>;
2205 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2206
2207 nvidia,bpmp = <&bpmp 3>;
2208
2209 nvidia,aspm-cmrt-us = <60>;
2210 nvidia,aspm-pwr-on-t-us = <20>;
2211 nvidia,aspm-l0s-entrance-latency-us = <3>;
2212
2213 bus-range = <0x0 0xff>;
2214
2215 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2216 <0x02000000 0x0 0x40000000 0x21 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2217 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2218
2219 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
2220 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
2221 interconnect-names = "dma-mem", "write";
2222 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2223 iommu-map-mask = <0x0>;
2224 dma-coherent;
2225
2226 status = "disabled";
2227 };
2228
2229 pcie@14160000 {
2230 compatible = "nvidia,tegra234-pcie";
2231 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2232 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2233 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2234 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2235 <0x00 0x36080000 0x0 0x00040000>; /* DBI reg space (256K) */
2236 reg-names = "appl", "config", "atu_dma", "dbi";
2237
2238 #address-cells = <3>;
2239 #size-cells = <2>;
2240 device_type = "pci";
2241 num-lanes = <4>;
2242 num-viewport = <8>;
2243 linux,pci-domain = <4>;
2244
2245 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2246 clock-names = "core";
2247
2248 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2249 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2250 reset-names = "apb", "core";
2251
2252 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2253 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2254 interrupt-names = "intr", "msi";
2255
2256 #interrupt-cells = <1>;
2257 interrupt-map-mask = <0 0 0 0>;
2258 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2259
2260 nvidia,bpmp = <&bpmp 4>;
2261
2262 nvidia,aspm-cmrt-us = <60>;
2263 nvidia,aspm-pwr-on-t-us = <20>;
2264 nvidia,aspm-l0s-entrance-latency-us = <3>;
2265
2266 bus-range = <0x0 0xff>;
2267
2268 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2269 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2270 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2271
2272 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
2273 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
2274 interconnect-names = "dma-mem", "write";
2275 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2276 iommu-map-mask = <0x0>;
2277 dma-coherent;
2278
2279 status = "disabled";
2280 };
2281
2282 pcie@14180000 {
2283 compatible = "nvidia,tegra234-pcie";
2284 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2285 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2286 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2287 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2288 <0x00 0x38080000 0x0 0x00040000>; /* DBI reg space (256K) */
2289 reg-names = "appl", "config", "atu_dma", "dbi";
2290
2291 #address-cells = <3>;
2292 #size-cells = <2>;
2293 device_type = "pci";
2294 num-lanes = <4>;
2295 num-viewport = <8>;
2296 linux,pci-domain = <0>;
2297
2298 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2299 clock-names = "core";
2300
2301 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2302 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2303 reset-names = "apb", "core";
2304
2305 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2306 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2307 interrupt-names = "intr", "msi";
2308
2309 #interrupt-cells = <1>;
2310 interrupt-map-mask = <0 0 0 0>;
2311 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2312
2313 nvidia,bpmp = <&bpmp 0>;
2314
2315 nvidia,aspm-cmrt-us = <60>;
2316 nvidia,aspm-pwr-on-t-us = <20>;
2317 nvidia,aspm-l0s-entrance-latency-us = <3>;
2318
2319 bus-range = <0x0 0xff>;
2320
2321 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2322 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2323 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2324
2325 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
2326 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
2327 interconnect-names = "dma-mem", "write";
2328 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2329 iommu-map-mask = <0x0>;
2330 dma-coherent;
2331
2332 status = "disabled";
2333 };
2334
2335 pcie@141a0000 {
2336 compatible = "nvidia,tegra234-pcie";
2337 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2338 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2339 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2340 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2341 <0x00 0x3a080000 0x0 0x00040000>; /* DBI reg space (256K) */
2342 reg-names = "appl", "config", "atu_dma", "dbi";
2343
2344 #address-cells = <3>;
2345 #size-cells = <2>;
2346 device_type = "pci";
2347 num-lanes = <8>;
2348 num-viewport = <8>;
2349 linux,pci-domain = <5>;
2350
2351 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2352 clock-names = "core";
2353
2354 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2355 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2356 reset-names = "apb", "core";
2357
2358 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2359 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2360 interrupt-names = "intr", "msi";
2361
2362 #interrupt-cells = <1>;
2363 interrupt-map-mask = <0 0 0 0>;
2364 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2365
2366 nvidia,bpmp = <&bpmp 5>;
2367
2368 nvidia,aspm-cmrt-us = <60>;
2369 nvidia,aspm-pwr-on-t-us = <20>;
2370 nvidia,aspm-l0s-entrance-latency-us = <3>;
2371
2372 bus-range = <0x0 0xff>;
2373
24840065 2374 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
ec142c44
VS		 2375 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2376 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2377
2378 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2379 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2380 interconnect-names = "dma-mem", "write";
2381 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2382 iommu-map-mask = <0x0>;
2383 dma-coherent;
2384
2385 status = "disabled";
2386 };
2387
2388 pcie@141c0000 {
2389 compatible = "nvidia,tegra234-pcie";
2390 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2391 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2392 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2393 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2394 <0x00 0x3c080000 0x0 0x00040000>; /* DBI reg space (256K) */
2395 reg-names = "appl", "config", "atu_dma", "dbi";
2396
2397 #address-cells = <3>;
2398 #size-cells = <2>;
2399 device_type = "pci";
2400 num-lanes = <4>;
2401 num-viewport = <8>;
2402 linux,pci-domain = <6>;
2403
2404 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2405 clock-names = "core";
2406
2407 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2408 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2409 reset-names = "apb", "core";
2410
2411 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2412 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2413 interrupt-names = "intr", "msi";
2414
2415 #interrupt-cells = <1>;
2416 interrupt-map-mask = <0 0 0 0>;
2417 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2418
2419 nvidia,bpmp = <&bpmp 6>;
2420
2421 nvidia,aspm-cmrt-us = <60>;
2422 nvidia,aspm-pwr-on-t-us = <20>;
2423 nvidia,aspm-l0s-entrance-latency-us = <3>;
2424
2425 bus-range = <0x0 0xff>;
2426
2427 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2428 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2429 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2430
2431 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2432 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2433 interconnect-names = "dma-mem", "write";
2434 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2435 iommu-map-mask = <0x0>;
2436 dma-coherent;
2437
2438 status = "disabled";
2439 };
2440
2441 pcie@141e0000 {
2442 compatible = "nvidia,tegra234-pcie";
2443 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2444 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2445 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2446 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2447 <0x00 0x3e080000 0x0 0x00040000>; /* DBI reg space (256K) */
2448 reg-names = "appl", "config", "atu_dma", "dbi";
2449
2450 #address-cells = <3>;
2451 #size-cells = <2>;
2452 device_type = "pci";
2453 num-lanes = <8>;
2454 num-viewport = <8>;
2455 linux,pci-domain = <7>;
2456
2457 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2458 clock-names = "core";
2459
2460 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2461 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2462 reset-names = "apb", "core";
2463
2464 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2465 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2466 interrupt-names = "intr", "msi";
2467
2468 #interrupt-cells = <1>;
2469 interrupt-map-mask = <0 0 0 0>;
2470 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2471
2472 nvidia,bpmp = <&bpmp 7>;
2473
2474 nvidia,aspm-cmrt-us = <60>;
2475 nvidia,aspm-pwr-on-t-us = <20>;
2476 nvidia,aspm-l0s-entrance-latency-us = <3>;
2477
2478 bus-range = <0x0 0xff>;
2479
24840065 2480 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
ec142c44
VS		 2481 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2482 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2483
2484 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2485 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2486 interconnect-names = "dma-mem", "write";
2487 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2488 iommu-map-mask = <0x0>;
2489 dma-coherent;
2490
2491 status = "disabled";
2492 };
2493
2494 pcie-ep@141a0000 {
2495 compatible = "nvidia,tegra234-pcie-ep";
2496 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2497 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2498 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2499 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2500 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2501 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2502
2503 num-lanes = <8>;
2504
2505 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2506 clock-names = "core";
2507
2508 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2509 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2510 reset-names = "apb", "core";
2511
2512 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2513 interrupt-names = "intr";
2514
2515 nvidia,bpmp = <&bpmp 5>;
2516
2517 nvidia,enable-ext-refclk;
2518 nvidia,aspm-cmrt-us = <60>;
2519 nvidia,aspm-pwr-on-t-us = <20>;
2520 nvidia,aspm-l0s-entrance-latency-us = <3>;
2521
2522 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2523 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2524 interconnect-names = "dma-mem", "write";
2525 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2526 iommu-map-mask = <0x0>;
2527 dma-coherent;
2528
2529 status = "disabled";
2530 };
2531
2532 pcie-ep@141c0000{
2533 compatible = "nvidia,tegra234-pcie-ep";
2534 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2535 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2536 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2537 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
2538 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2539 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2540
2541 num-lanes = <4>;
2542
2543 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2544 clock-names = "core";
2545
2546 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2547 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2548 reset-names = "apb", "core";
2549
2550 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2551 interrupt-names = "intr";
2552
2553 nvidia,bpmp = <&bpmp 6>;
2554
2555 nvidia,enable-ext-refclk;
2556 nvidia,aspm-cmrt-us = <60>;
2557 nvidia,aspm-pwr-on-t-us = <20>;
2558 nvidia,aspm-l0s-entrance-latency-us = <3>;
2559
2560 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2561 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2562 interconnect-names = "dma-mem", "write";
2563 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2564 iommu-map-mask = <0x0>;
2565 dma-coherent;
2566
2567 status = "disabled";
2568 };
2569
2570 pcie-ep@141e0000{
2571 compatible = "nvidia,tegra234-pcie-ep";
2572 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2573 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2574 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2575 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
2576 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2577 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2578
2579 num-lanes = <8>;
2580
2581 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2582 clock-names = "core";
2583
2584 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2585 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2586 reset-names = "apb", "core";
2587
2588 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2589 interrupt-names = "intr";
2590
2591 nvidia,bpmp = <&bpmp 7>;
2592
2593 nvidia,enable-ext-refclk;
2594 nvidia,aspm-cmrt-us = <60>;
2595 nvidia,aspm-pwr-on-t-us = <20>;
2596 nvidia,aspm-l0s-entrance-latency-us = <3>;
2597
2598 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2599 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2600 interconnect-names = "dma-mem", "write";
2601 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2602 iommu-map-mask = <0x0>;
2603 dma-coherent;
2604
2605 status = "disabled";
2606 };
2607
2608 pcie-ep@140e0000{
2609 compatible = "nvidia,tegra234-pcie-ep";
2610 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2611 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2612 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2613 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
2614 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2615 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2616
2617 num-lanes = <4>;
2618
2619 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2620 clock-names = "core";
2621
2622 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2623 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2624 reset-names = "apb", "core";
2625
2626 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2627 interrupt-names = "intr";
2628
2629 nvidia,bpmp = <&bpmp 10>;
2630
2631 nvidia,enable-ext-refclk;
2632 nvidia,aspm-cmrt-us = <60>;
2633 nvidia,aspm-pwr-on-t-us = <20>;
2634 nvidia,aspm-l0s-entrance-latency-us = <3>;
2635
2636 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2637 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2638 interconnect-names = "dma-mem", "write";
2639 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2640 iommu-map-mask = <0x0>;
2641 dma-coherent;
2642
2643 status = "disabled";
2644 };
2645
7fa30752 2646 sram@40000000 {
63944891 2647 compatible = "nvidia,tegra234-sysram", "mmio-sram";
98094be1 2648 reg = <0x0 0x40000000 0x0 0x80000>;
63944891
TR		 2649 #address-cells = <1>;
2650 #size-cells = <1>;
98094be1 2651 ranges = <0x0 0x0 0x40000000 0x80000>;
61192a9d 2652 no-memory-wc;
63944891 2653
98094be1
MP		 2654 cpu_bpmp_tx: sram@70000 {
2655 reg = <0x70000 0x1000>;
63944891
TR		 2656 label = "cpu-bpmp-tx";
2657 pool;
2658 };
2659
98094be1
MP		 2660 cpu_bpmp_rx: sram@71000 {
2661 reg = <0x71000 0x1000>;
63944891
TR		 2662 label = "cpu-bpmp-rx";
2663 pool;
2664 };
2665 };
2666
2667 bpmp: bpmp {
2668 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
2669 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2670 TEGRA_HSP_DB_MASTER_BPMP>;
7fa30752 2671 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
63944891
TR		 2672 #clock-cells = <1>;
2673 #reset-cells = <1>;
2674 #power-domain-cells = <1>;
6de481e5
TR		 2675 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
2676 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
2677 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
2678 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
2679 interconnect-names = "read", "write", "dma-mem", "dma-write";
5710e16a 2680 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
63944891
TR		 2681
2682 bpmp_i2c: i2c {
2683 compatible = "nvidia,tegra186-bpmp-i2c";
2684 nvidia,bpmp-bus-id = <5>;
2685 #address-cells = <1>;
2686 #size-cells = <0>;
2687 };
2688 };
2689
2690 cpus {
2691 #address-cells = <1>;
2692 #size-cells = <0>;
2693
a12cf5c3
TR		 2694 cpu0_0: cpu@0 {
2695 compatible = "arm,cortex-a78";
63944891 2696 device_type = "cpu";
a12cf5c3 2697 reg = <0x00000>;
63944891
TR		 2698
2699 enable-method = "psci";
a12cf5c3
TR		 2700
2701 i-cache-size = <65536>;
2702 i-cache-line-size = <64>;
2703 i-cache-sets = <256>;
2704 d-cache-size = <65536>;
2705 d-cache-line-size = <64>;
2706 d-cache-sets = <256>;
2707 next-level-cache = <&l2c0_0>;
2708 };
2709
2710 cpu0_1: cpu@100 {
2711 compatible = "arm,cortex-a78";
2712 device_type = "cpu";
2713 reg = <0x00100>;
2714
2715 enable-method = "psci";
2716
2717 i-cache-size = <65536>;
2718 i-cache-line-size = <64>;
2719 i-cache-sets = <256>;
2720 d-cache-size = <65536>;
2721 d-cache-line-size = <64>;
2722 d-cache-sets = <256>;
2723 next-level-cache = <&l2c0_1>;
63944891 2724 };
a12cf5c3
TR		 2725
2726 cpu0_2: cpu@200 {
2727 compatible = "arm,cortex-a78";
2728 device_type = "cpu";
2729 reg = <0x00200>;
2730
2731 enable-method = "psci";
2732
2733 i-cache-size = <65536>;
2734 i-cache-line-size = <64>;
2735 i-cache-sets = <256>;
2736 d-cache-size = <65536>;
2737 d-cache-line-size = <64>;
2738 d-cache-sets = <256>;
2739 next-level-cache = <&l2c0_2>;
2740 };
2741
2742 cpu0_3: cpu@300 {
2743 compatible = "arm,cortex-a78";
2744 device_type = "cpu";
2745 reg = <0x00300>;
2746
2747 enable-method = "psci";
2748
2749 i-cache-size = <65536>;
2750 i-cache-line-size = <64>;
2751 i-cache-sets = <256>;
2752 d-cache-size = <65536>;
2753 d-cache-line-size = <64>;
2754 d-cache-sets = <256>;
2755 next-level-cache = <&l2c0_3>;
2756 };
2757
2758 cpu1_0: cpu@10000 {
2759 compatible = "arm,cortex-a78";
2760 device_type = "cpu";
2761 reg = <0x10000>;
2762
2763 enable-method = "psci";
2764
2765 i-cache-size = <65536>;
2766 i-cache-line-size = <64>;
2767 i-cache-sets = <256>;
2768 d-cache-size = <65536>;
2769 d-cache-line-size = <64>;
2770 d-cache-sets = <256>;
2771 next-level-cache = <&l2c1_0>;
2772 };
2773
2774 cpu1_1: cpu@10100 {
2775 compatible = "arm,cortex-a78";
2776 device_type = "cpu";
2777 reg = <0x10100>;
2778
2779 enable-method = "psci";
2780
2781 i-cache-size = <65536>;
2782 i-cache-line-size = <64>;
2783 i-cache-sets = <256>;
2784 d-cache-size = <65536>;
2785 d-cache-line-size = <64>;
2786 d-cache-sets = <256>;
2787 next-level-cache = <&l2c1_1>;
2788 };
2789
2790 cpu1_2: cpu@10200 {
2791 compatible = "arm,cortex-a78";
2792 device_type = "cpu";
2793 reg = <0x10200>;
2794
2795 enable-method = "psci";
2796
2797 i-cache-size = <65536>;
2798 i-cache-line-size = <64>;
2799 i-cache-sets = <256>;
2800 d-cache-size = <65536>;
2801 d-cache-line-size = <64>;
2802 d-cache-sets = <256>;
2803 next-level-cache = <&l2c1_2>;
2804 };
2805
2806 cpu1_3: cpu@10300 {
2807 compatible = "arm,cortex-a78";
2808 device_type = "cpu";
2809 reg = <0x10300>;
2810
2811 enable-method = "psci";
2812
2813 i-cache-size = <65536>;
2814 i-cache-line-size = <64>;
2815 i-cache-sets = <256>;
2816 d-cache-size = <65536>;
2817 d-cache-line-size = <64>;
2818 d-cache-sets = <256>;
2819 next-level-cache = <&l2c1_3>;
2820 };
2821
2822 cpu2_0: cpu@20000 {
2823 compatible = "arm,cortex-a78";
2824 device_type = "cpu";
2825 reg = <0x20000>;
2826
2827 enable-method = "psci";
2828
2829 i-cache-size = <65536>;
2830 i-cache-line-size = <64>;
2831 i-cache-sets = <256>;
2832 d-cache-size = <65536>;
2833 d-cache-line-size = <64>;
2834 d-cache-sets = <256>;
2835 next-level-cache = <&l2c2_0>;
2836 };
2837
2838 cpu2_1: cpu@20100 {
2839 compatible = "arm,cortex-a78";
2840 device_type = "cpu";
2841 reg = <0x20100>;
2842
2843 enable-method = "psci";
2844
2845 i-cache-size = <65536>;
2846 i-cache-line-size = <64>;
2847 i-cache-sets = <256>;
2848 d-cache-size = <65536>;
2849 d-cache-line-size = <64>;
2850 d-cache-sets = <256>;
2851 next-level-cache = <&l2c2_1>;
2852 };
2853
2854 cpu2_2: cpu@20200 {
2855 compatible = "arm,cortex-a78";
2856 device_type = "cpu";
2857 reg = <0x20200>;
2858
2859 enable-method = "psci";
2860
2861 i-cache-size = <65536>;
2862 i-cache-line-size = <64>;
2863 i-cache-sets = <256>;
2864 d-cache-size = <65536>;
2865 d-cache-line-size = <64>;
2866 d-cache-sets = <256>;
2867 next-level-cache = <&l2c2_2>;
2868 };
2869
2870 cpu2_3: cpu@20300 {
2871 compatible = "arm,cortex-a78";
2872 device_type = "cpu";
2873 reg = <0x20300>;
2874
2875 enable-method = "psci";
2876
2877 i-cache-size = <65536>;
2878 i-cache-line-size = <64>;
2879 i-cache-sets = <256>;
2880 d-cache-size = <65536>;
2881 d-cache-line-size = <64>;
2882 d-cache-sets = <256>;
2883 next-level-cache = <&l2c2_3>;
2884 };
2885
2886 cpu-map {
2887 cluster0 {
2888 core0 {
2889 cpu = <&cpu0_0>;
2890 };
2891
2892 core1 {
2893 cpu = <&cpu0_1>;
2894 };
2895
2896 core2 {
2897 cpu = <&cpu0_2>;
2898 };
2899
2900 core3 {
2901 cpu = <&cpu0_3>;
2902 };
2903 };
2904
2905 cluster1 {
2906 core0 {
2907 cpu = <&cpu1_0>;
2908 };
2909
2910 core1 {
2911 cpu = <&cpu1_1>;
2912 };
2913
2914 core2 {
2915 cpu = <&cpu1_2>;
2916 };
2917
2918 core3 {
2919 cpu = <&cpu1_3>;
2920 };
2921 };
2922
2923 cluster2 {
2924 core0 {
2925 cpu = <&cpu2_0>;
2926 };
2927
2928 core1 {
2929 cpu = <&cpu2_1>;
2930 };
2931
2932 core2 {
2933 cpu = <&cpu2_2>;
2934 };
2935
2936 core3 {
2937 cpu = <&cpu2_3>;
2938 };
2939 };
2940 };
2941
2942 l2c0_0: l2-cache00 {
2943 cache-size = <262144>;
2944 cache-line-size = <64>;
2945 cache-sets = <512>;
2946 cache-unified;
2947 next-level-cache = <&l3c0>;
2948 };
2949
2950 l2c0_1: l2-cache01 {
2951 cache-size = <262144>;
2952 cache-line-size = <64>;
2953 cache-sets = <512>;
2954 cache-unified;
2955 next-level-cache = <&l3c0>;
2956 };
2957
2958 l2c0_2: l2-cache02 {
2959 cache-size = <262144>;
2960 cache-line-size = <64>;
2961 cache-sets = <512>;
2962 cache-unified;
2963 next-level-cache = <&l3c0>;
2964 };
2965
2966 l2c0_3: l2-cache03 {
2967 cache-size = <262144>;
2968 cache-line-size = <64>;
2969 cache-sets = <512>;
2970 cache-unified;
2971 next-level-cache = <&l3c0>;
2972 };
2973
2974 l2c1_0: l2-cache10 {
2975 cache-size = <262144>;
2976 cache-line-size = <64>;
2977 cache-sets = <512>;
2978 cache-unified;
2979 next-level-cache = <&l3c1>;
2980 };
2981
2982 l2c1_1: l2-cache11 {
2983 cache-size = <262144>;
2984 cache-line-size = <64>;
2985 cache-sets = <512>;
2986 cache-unified;
2987 next-level-cache = <&l3c1>;
2988 };
2989
2990 l2c1_2: l2-cache12 {
2991 cache-size = <262144>;
2992 cache-line-size = <64>;
2993 cache-sets = <512>;
2994 cache-unified;
2995 next-level-cache = <&l3c1>;
2996 };
2997
2998 l2c1_3: l2-cache13 {
2999 cache-size = <262144>;
3000 cache-line-size = <64>;
3001 cache-sets = <512>;
3002 cache-unified;
3003 next-level-cache = <&l3c1>;
3004 };
3005
3006 l2c2_0: l2-cache20 {
3007 cache-size = <262144>;
3008 cache-line-size = <64>;
3009 cache-sets = <512>;
3010 cache-unified;
3011 next-level-cache = <&l3c2>;
3012 };
3013
3014 l2c2_1: l2-cache21 {
3015 cache-size = <262144>;
3016 cache-line-size = <64>;
3017 cache-sets = <512>;
3018 cache-unified;
3019 next-level-cache = <&l3c2>;
3020 };
3021
3022 l2c2_2: l2-cache22 {
3023 cache-size = <262144>;
3024 cache-line-size = <64>;
3025 cache-sets = <512>;
3026 cache-unified;
3027 next-level-cache = <&l3c2>;
3028 };
3029
3030 l2c2_3: l2-cache23 {
3031 cache-size = <262144>;
3032 cache-line-size = <64>;
3033 cache-sets = <512>;
3034 cache-unified;
3035 next-level-cache = <&l3c2>;
3036 };
3037
3038 l3c0: l3-cache0 {
3039 cache-size = <2097152>;
3040 cache-line-size = <64>;
3041 cache-sets = <2048>;
3042 };
3043
3044 l3c1: l3-cache1 {
3045 cache-size = <2097152>;
3046 cache-line-size = <64>;
3047 cache-sets = <2048>;
3048 };
3049
3050 l3c2: l3-cache2 {
3051 cache-size = <2097152>;
3052 cache-line-size = <64>;
3053 cache-sets = <2048>;
3054 };
3055 };
3056
3057 pmu {
3058 compatible = "arm,cortex-a78-pmu";
3059 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
3060 status = "okay";
63944891
TR		 3061 };
3062
3063 psci {
3064 compatible = "arm,psci-1.0";
3065 status = "okay";
3066 method = "smc";
3067 };
3068
06ad2ec4
MP		 3069 tcu: serial {
3070 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3071 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3072 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3073 mbox-names = "rx", "tx";
3074 status = "disabled";
3075 };
3076
09614acd
SP		 3077 sound {
3078 status = "disabled";
3079
3080 clocks = <&bpmp TEGRA234_CLK_PLLA>,
3081 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3082 clock-names = "pll_a", "plla_out0";
3083 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3084 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3085 <&bpmp TEGRA234_CLK_AUD_MCLK>;
3086 assigned-clock-parents = <0>,
3087 <&bpmp TEGRA234_CLK_PLLA>,
3088 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3089 };
3090
63944891
TR		 3091 timer {
3092 compatible = "arm,armv8-timer";
3093 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3094 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3095 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3096 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3097 interrupt-parent = <&gic>;
3098 always-on;
3099 };
3100};
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