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arm64: tegra: Bump #address-cells and #size-cells
[thirdparty/linux.git] / arch / arm64 / boot / dts / nvidia / tegra234.dtsi
CommitLineData
63944891
TR		 1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/clock/tegra234-clock.h>
699349e0 4#include <dt-bindings/gpio/tegra234-gpio.h>
63944891
TR		 5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/mailbox/tegra186-hsp.h>
eed280df 7#include <dt-bindings/memory/tegra234-mc.h>
c71e1897 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
dc94a94d 9#include <dt-bindings/power/tegra234-powergate.h>
63944891
TR		 10#include <dt-bindings/reset/tegra234-reset.h>
11
12/ {
13 compatible = "nvidia,tegra234";
14 interrupt-parent = <&gic>;
15 #address-cells = <2>;
16 #size-cells = <2>;
17
18 bus@0 {
19 compatible = "simple-bus";
63944891 20
2838cfdd
TR		 21 #address-cells = <2>;
22 #size-cells = <2>;
23 ranges = <0x0 0x0 0x0 0x0 0x0 0x40000000>;
63944891 24
60d2016a 25 gpcdma: dma-controller@2600000 {
f7b93a08 26 compatible = "nvidia,tegra234-gpcdma",
f7b93a08 27 "nvidia,tegra186-gpcdma";
2838cfdd 28 reg = <0x0 0x2600000 0x0 0x210000>;
60d2016a
A		 29 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
30 reset-names = "gpcdma";
dd0be827
A		 31 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
32 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
60d2016a
A		 33 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
34 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
35 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
52 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
53 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
54 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
55 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
56 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
57 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
58 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
59 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
60 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
63 #dma-cells = <1>;
64 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dd0be827 65 dma-channel-mask = <0xfffffffe>;
60d2016a
A		 66 dma-coherent;
67 };
68
dc94a94d
SP		 69 aconnect@2900000 {
70 compatible = "nvidia,tegra234-aconnect",
71 "nvidia,tegra210-aconnect";
72 clocks = <&bpmp TEGRA234_CLK_APE>,
73 <&bpmp TEGRA234_CLK_APB2APE>;
74 clock-names = "ape", "apb2ape";
75 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
dc94a94d
SP		 76 status = "disabled";
77
2838cfdd
TR		 78 #address-cells = <2>;
79 #size-cells = <2>;
80 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
81
dc94a94d
SP		 82 tegra_ahub: ahub@2900800 {
83 compatible = "nvidia,tegra234-ahub";
2838cfdd 84 reg = <0x0 0x02900800 0x0 0x800>;
dc94a94d
SP		 85 clocks = <&bpmp TEGRA234_CLK_AHUB>;
86 clock-names = "ahub";
87 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
88 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
dc94a94d
SP		 89 status = "disabled";
90
2838cfdd
TR		 91 #address-cells = <2>;
92 #size-cells = <2>;
93 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
94
dc94a94d
SP		 95 tegra_i2s1: i2s@2901000 {
96 compatible = "nvidia,tegra234-i2s",
97 "nvidia,tegra210-i2s";
2838cfdd 98 reg = <0x0 0x2901000 0x0 0x100>;
dc94a94d
SP		 99 clocks = <&bpmp TEGRA234_CLK_I2S1>,
100 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
101 clock-names = "i2s", "sync_input";
102 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
103 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
104 assigned-clock-rates = <1536000>;
105 sound-name-prefix = "I2S1";
106 status = "disabled";
107 };
108
109 tegra_i2s2: i2s@2901100 {
110 compatible = "nvidia,tegra234-i2s",
111 "nvidia,tegra210-i2s";
2838cfdd 112 reg = <0x0 0x2901100 0x0 0x100>;
dc94a94d
SP		 113 clocks = <&bpmp TEGRA234_CLK_I2S2>,
114 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
115 clock-names = "i2s", "sync_input";
116 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
117 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
118 assigned-clock-rates = <1536000>;
119 sound-name-prefix = "I2S2";
120 status = "disabled";
121 };
122
123 tegra_i2s3: i2s@2901200 {
124 compatible = "nvidia,tegra234-i2s",
125 "nvidia,tegra210-i2s";
2838cfdd 126 reg = <0x0 0x2901200 0x0 0x100>;
dc94a94d
SP		 127 clocks = <&bpmp TEGRA234_CLK_I2S3>,
128 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
129 clock-names = "i2s", "sync_input";
130 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
131 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
132 assigned-clock-rates = <1536000>;
133 sound-name-prefix = "I2S3";
134 status = "disabled";
135 };
136
137 tegra_i2s4: i2s@2901300 {
138 compatible = "nvidia,tegra234-i2s",
139 "nvidia,tegra210-i2s";
2838cfdd 140 reg = <0x0 0x2901300 0x0 0x100>;
dc94a94d
SP		 141 clocks = <&bpmp TEGRA234_CLK_I2S4>,
142 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
143 clock-names = "i2s", "sync_input";
144 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
145 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
146 assigned-clock-rates = <1536000>;
147 sound-name-prefix = "I2S4";
148 status = "disabled";
149 };
150
151 tegra_i2s5: i2s@2901400 {
152 compatible = "nvidia,tegra234-i2s",
153 "nvidia,tegra210-i2s";
2838cfdd 154 reg = <0x0 0x2901400 0x0 0x100>;
dc94a94d
SP		 155 clocks = <&bpmp TEGRA234_CLK_I2S5>,
156 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
157 clock-names = "i2s", "sync_input";
158 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
159 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
160 assigned-clock-rates = <1536000>;
161 sound-name-prefix = "I2S5";
162 status = "disabled";
163 };
164
165 tegra_i2s6: i2s@2901500 {
166 compatible = "nvidia,tegra234-i2s",
167 "nvidia,tegra210-i2s";
2838cfdd 168 reg = <0x0 0x2901500 0x0 0x100>;
dc94a94d
SP		 169 clocks = <&bpmp TEGRA234_CLK_I2S6>,
170 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
171 clock-names = "i2s", "sync_input";
172 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
173 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
174 assigned-clock-rates = <1536000>;
175 sound-name-prefix = "I2S6";
176 status = "disabled";
177 };
178
179 tegra_sfc1: sfc@2902000 {
180 compatible = "nvidia,tegra234-sfc",
181 "nvidia,tegra210-sfc";
2838cfdd 182 reg = <0x0 0x2902000 0x0 0x200>;
dc94a94d
SP		 183 sound-name-prefix = "SFC1";
184 status = "disabled";
185 };
186
187 tegra_sfc2: sfc@2902200 {
188 compatible = "nvidia,tegra234-sfc",
189 "nvidia,tegra210-sfc";
2838cfdd 190 reg = <0x0 0x2902200 0x0 0x200>;
dc94a94d
SP		 191 sound-name-prefix = "SFC2";
192 status = "disabled";
193 };
194
195 tegra_sfc3: sfc@2902400 {
196 compatible = "nvidia,tegra234-sfc",
197 "nvidia,tegra210-sfc";
2838cfdd 198 reg = <0x0 0x2902400 0x0 0x200>;
dc94a94d
SP		 199 sound-name-prefix = "SFC3";
200 status = "disabled";
201 };
202
203 tegra_sfc4: sfc@2902600 {
204 compatible = "nvidia,tegra234-sfc",
205 "nvidia,tegra210-sfc";
2838cfdd 206 reg = <0x0 0x2902600 0x0 0x200>;
dc94a94d
SP		 207 sound-name-prefix = "SFC4";
208 status = "disabled";
209 };
210
211 tegra_amx1: amx@2903000 {
212 compatible = "nvidia,tegra234-amx",
213 "nvidia,tegra194-amx";
2838cfdd 214 reg = <0x0 0x2903000 0x0 0x100>;
dc94a94d
SP		 215 sound-name-prefix = "AMX1";
216 status = "disabled";
217 };
218
219 tegra_amx2: amx@2903100 {
220 compatible = "nvidia,tegra234-amx",
221 "nvidia,tegra194-amx";
2838cfdd 222 reg = <0x0 0x2903100 0x0 0x100>;
dc94a94d
SP		 223 sound-name-prefix = "AMX2";
224 status = "disabled";
225 };
226
227 tegra_amx3: amx@2903200 {
228 compatible = "nvidia,tegra234-amx",
229 "nvidia,tegra194-amx";
2838cfdd 230 reg = <0x0 0x2903200 0x0 0x100>;
dc94a94d
SP		 231 sound-name-prefix = "AMX3";
232 status = "disabled";
233 };
234
235 tegra_amx4: amx@2903300 {
236 compatible = "nvidia,tegra234-amx",
237 "nvidia,tegra194-amx";
2838cfdd 238 reg = <0x0 0x2903300 0x0 0x100>;
dc94a94d
SP		 239 sound-name-prefix = "AMX4";
240 status = "disabled";
241 };
242
243 tegra_adx1: adx@2903800 {
244 compatible = "nvidia,tegra234-adx",
245 "nvidia,tegra210-adx";
2838cfdd 246 reg = <0x0 0x2903800 0x0 0x100>;
dc94a94d
SP		 247 sound-name-prefix = "ADX1";
248 status = "disabled";
249 };
250
251 tegra_adx2: adx@2903900 {
252 compatible = "nvidia,tegra234-adx",
253 "nvidia,tegra210-adx";
2838cfdd 254 reg = <0x0 0x2903900 0x0 0x100>;
dc94a94d
SP		 255 sound-name-prefix = "ADX2";
256 status = "disabled";
257 };
258
259 tegra_adx3: adx@2903a00 {
260 compatible = "nvidia,tegra234-adx",
261 "nvidia,tegra210-adx";
2838cfdd 262 reg = <0x0 0x2903a00 0x0 0x100>;
dc94a94d
SP		 263 sound-name-prefix = "ADX3";
264 status = "disabled";
265 };
266
267 tegra_adx4: adx@2903b00 {
268 compatible = "nvidia,tegra234-adx",
269 "nvidia,tegra210-adx";
2838cfdd 270 reg = <0x0 0x2903b00 0x0 0x100>;
dc94a94d
SP		 271 sound-name-prefix = "ADX4";
272 status = "disabled";
273 };
274
275
276 tegra_dmic1: dmic@2904000 {
277 compatible = "nvidia,tegra234-dmic",
278 "nvidia,tegra210-dmic";
2838cfdd 279 reg = <0x0 0x2904000 0x0 0x100>;
dc94a94d
SP		 280 clocks = <&bpmp TEGRA234_CLK_DMIC1>;
281 clock-names = "dmic";
282 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
283 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
284 assigned-clock-rates = <3072000>;
285 sound-name-prefix = "DMIC1";
286 status = "disabled";
287 };
288
289 tegra_dmic2: dmic@2904100 {
290 compatible = "nvidia,tegra234-dmic",
291 "nvidia,tegra210-dmic";
2838cfdd 292 reg = <0x0 0x2904100 0x0 0x100>;
dc94a94d
SP		 293 clocks = <&bpmp TEGRA234_CLK_DMIC2>;
294 clock-names = "dmic";
295 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
296 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
297 assigned-clock-rates = <3072000>;
298 sound-name-prefix = "DMIC2";
299 status = "disabled";
300 };
301
302 tegra_dmic3: dmic@2904200 {
303 compatible = "nvidia,tegra234-dmic",
304 "nvidia,tegra210-dmic";
2838cfdd 305 reg = <0x0 0x2904200 0x0 0x100>;
dc94a94d
SP		 306 clocks = <&bpmp TEGRA234_CLK_DMIC3>;
307 clock-names = "dmic";
308 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
309 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
310 assigned-clock-rates = <3072000>;
311 sound-name-prefix = "DMIC3";
312 status = "disabled";
313 };
314
315 tegra_dmic4: dmic@2904300 {
316 compatible = "nvidia,tegra234-dmic",
317 "nvidia,tegra210-dmic";
2838cfdd 318 reg = <0x0 0x2904300 0x0 0x100>;
dc94a94d
SP		 319 clocks = <&bpmp TEGRA234_CLK_DMIC4>;
320 clock-names = "dmic";
321 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
322 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
323 assigned-clock-rates = <3072000>;
324 sound-name-prefix = "DMIC4";
325 status = "disabled";
326 };
327
328 tegra_dspk1: dspk@2905000 {
329 compatible = "nvidia,tegra234-dspk",
330 "nvidia,tegra186-dspk";
2838cfdd 331 reg = <0x0 0x2905000 0x0 0x100>;
dc94a94d
SP		 332 clocks = <&bpmp TEGRA234_CLK_DSPK1>;
333 clock-names = "dspk";
334 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
335 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
336 assigned-clock-rates = <12288000>;
337 sound-name-prefix = "DSPK1";
338 status = "disabled";
339 };
340
341 tegra_dspk2: dspk@2905100 {
342 compatible = "nvidia,tegra234-dspk",
343 "nvidia,tegra186-dspk";
2838cfdd 344 reg = <0x0 0x2905100 0x0 0x100>;
dc94a94d
SP		 345 clocks = <&bpmp TEGRA234_CLK_DSPK2>;
346 clock-names = "dspk";
347 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
348 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
349 assigned-clock-rates = <12288000>;
350 sound-name-prefix = "DSPK2";
351 status = "disabled";
352 };
353
4b6a1b7c
SP		 354 tegra_ope1: processing-engine@2908000 {
355 compatible = "nvidia,tegra234-ope",
356 "nvidia,tegra210-ope";
2838cfdd 357 reg = <0x0 0x2908000 0x0 0x100>;
4b6a1b7c
SP		 358 sound-name-prefix = "OPE1";
359 status = "disabled";
360
2838cfdd
TR		 361 #address-cells = <2>;
362 #size-cells = <2>;
363 ranges;
364
4b6a1b7c
SP		 365 equalizer@2908100 {
366 compatible = "nvidia,tegra234-peq",
367 "nvidia,tegra210-peq";
2838cfdd 368 reg = <0x0 0x2908100 0x0 0x100>;
4b6a1b7c
SP		 369 };
370
371 dynamic-range-compressor@2908200 {
372 compatible = "nvidia,tegra234-mbdrc",
373 "nvidia,tegra210-mbdrc";
2838cfdd 374 reg = <0x0 0x2908200 0x0 0x200>;
4b6a1b7c
SP		 375 };
376 };
377
dc94a94d
SP		 378 tegra_mvc1: mvc@290a000 {
379 compatible = "nvidia,tegra234-mvc",
380 "nvidia,tegra210-mvc";
2838cfdd 381 reg = <0x0 0x290a000 0x0 0x200>;
dc94a94d
SP		 382 sound-name-prefix = "MVC1";
383 status = "disabled";
384 };
385
386 tegra_mvc2: mvc@290a200 {
387 compatible = "nvidia,tegra234-mvc",
388 "nvidia,tegra210-mvc";
2838cfdd 389 reg = <0x0 0x290a200 0x0 0x200>;
dc94a94d
SP		 390 sound-name-prefix = "MVC2";
391 status = "disabled";
392 };
393
394 tegra_amixer: amixer@290bb00 {
395 compatible = "nvidia,tegra234-amixer",
396 "nvidia,tegra210-amixer";
2838cfdd 397 reg = <0x0 0x290bb00 0x0 0x800>;
dc94a94d
SP		 398 sound-name-prefix = "MIXER1";
399 status = "disabled";
400 };
401
402 tegra_admaif: admaif@290f000 {
403 compatible = "nvidia,tegra234-admaif",
404 "nvidia,tegra186-admaif";
2838cfdd 405 reg = <0x0 0x0290f000 0x0 0x1000>;
dc94a94d
SP		 406 dmas = <&adma 1>, <&adma 1>,
407 <&adma 2>, <&adma 2>,
408 <&adma 3>, <&adma 3>,
409 <&adma 4>, <&adma 4>,
410 <&adma 5>, <&adma 5>,
411 <&adma 6>, <&adma 6>,
412 <&adma 7>, <&adma 7>,
413 <&adma 8>, <&adma 8>,
414 <&adma 9>, <&adma 9>,
415 <&adma 10>, <&adma 10>,
416 <&adma 11>, <&adma 11>,
417 <&adma 12>, <&adma 12>,
418 <&adma 13>, <&adma 13>,
419 <&adma 14>, <&adma 14>,
420 <&adma 15>, <&adma 15>,
421 <&adma 16>, <&adma 16>,
422 <&adma 17>, <&adma 17>,
423 <&adma 18>, <&adma 18>,
424 <&adma 19>, <&adma 19>,
425 <&adma 20>, <&adma 20>;
426 dma-names = "rx1", "tx1",
427 "rx2", "tx2",
428 "rx3", "tx3",
429 "rx4", "tx4",
430 "rx5", "tx5",
431 "rx6", "tx6",
432 "rx7", "tx7",
433 "rx8", "tx8",
434 "rx9", "tx9",
435 "rx10", "tx10",
436 "rx11", "tx11",
437 "rx12", "tx12",
438 "rx13", "tx13",
439 "rx14", "tx14",
440 "rx15", "tx15",
441 "rx16", "tx16",
442 "rx17", "tx17",
443 "rx18", "tx18",
444 "rx19", "tx19",
445 "rx20", "tx20";
446 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
447 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
448 interconnect-names = "dma-mem", "write";
449 iommus = <&smmu_niso0 TEGRA234_SID_APE>;
450 status = "disabled";
451 };
47a08153
SP		 452
453 tegra_asrc: asrc@2910000 {
454 compatible = "nvidia,tegra234-asrc",
455 "nvidia,tegra186-asrc";
2838cfdd 456 reg = <0x0 0x2910000 0x0 0x2000>;
47a08153
SP		 457 sound-name-prefix = "ASRC1";
458 status = "disabled";
459 };
dc94a94d
SP		 460 };
461
462 adma: dma-controller@2930000 {
463 compatible = "nvidia,tegra234-adma",
464 "nvidia,tegra186-adma";
2838cfdd 465 reg = <0x0 0x02930000 0x0 0x20000>;
dc94a94d
SP		 466 interrupt-parent = <&agic>;
467 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
468 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
469 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
470 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
471 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
472 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
473 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
474 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
475 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
479 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
481 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
482 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
483 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
484 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
485 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
486 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
487 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
488 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
492 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
493 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
494 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
496 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
497 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
498 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
499 #dma-cells = <1>;
500 clocks = <&bpmp TEGRA234_CLK_AHUB>;
501 clock-names = "d_audio";
502 status = "disabled";
503 };
504
505 agic: interrupt-controller@2a40000 {
506 compatible = "nvidia,tegra234-agic",
507 "nvidia,tegra210-agic";
508 #interrupt-cells = <3>;
509 interrupt-controller;
2838cfdd
TR		 510 reg = <0x0 0x02a41000 0x0 0x1000>,
511 <0x0 0x02a42000 0x0 0x2000>;
dc94a94d
SP		 512 interrupts = <GIC_SPI 145
513 (GIC_CPU_MASK_SIMPLE(4) |
514 IRQ_TYPE_LEVEL_HIGH)>;
515 clocks = <&bpmp TEGRA234_CLK_APE>;
516 clock-names = "clk";
517 status = "disabled";
518 };
519 };
520
63944891
TR		 521 misc@100000 {
522 compatible = "nvidia,tegra234-misc";
2838cfdd
TR		 523 reg = <0x0 0x00100000 0x0 0xf000>,
524 <0x0 0x0010f000 0x0 0x1000>;
63944891
TR		 525 status = "okay";
526 };
527
28d860ed
K		 528 timer@2080000 {
529 compatible = "nvidia,tegra234-timer";
2838cfdd 530 reg = <0x0 0x02080000 0x0 0x00121000>;
28d860ed
K		 531 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
532 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
533 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
534 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
536 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
537 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
538 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
539 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
544 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
545 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
546 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
547 status = "okay";
548 };
549
4bb39ca2
MP		 550 host1x@13e00000 {
551 compatible = "nvidia,tegra234-host1x";
2838cfdd
TR		 552 reg = <0x0 0x13e00000 0x0 0x10000>,
553 <0x0 0x13e10000 0x0 0x10000>,
554 <0x0 0x13e40000 0x0 0x10000>;
4bb39ca2
MP		 555 reg-names = "common", "hypervisor", "vm";
556 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
557 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
558 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
559 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
560 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
561 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
562 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
563 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
565 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
566 "syncpt5", "syncpt6", "syncpt7", "host1x";
567 clocks = <&bpmp TEGRA234_CLK_HOST1X>;
568 clock-names = "host1x";
569
2838cfdd
TR		 570 #address-cells = <2>;
571 #size-cells = <2>;
572 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
4bb39ca2 573
4bb39ca2
MP		 574 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
575 interconnect-names = "dma-mem";
576 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
577
b35f5b53
MP		 578 /* Context isolation domains */
579 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
580 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
581 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
582 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
583 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
584 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
585 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
586 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
587 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
588 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
589 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
590 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
591 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
592 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
593 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
594 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
595
4bb39ca2
MP		 596 vic@15340000 {
597 compatible = "nvidia,tegra234-vic";
2838cfdd 598 reg = <0x0 0x15340000 0x0 0x00040000>;
4bb39ca2
MP		 599 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
600 clocks = <&bpmp TEGRA234_CLK_VIC>;
601 clock-names = "vic";
602 resets = <&bpmp TEGRA234_RESET_VIC>;
603 reset-names = "vic";
604
605 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
606 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>,
607 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>;
608 interconnect-names = "dma-mem", "write";
609 iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
610 dma-coherent;
611 };
68c31ad0
MP		 612
613 nvdec@15480000 {
614 compatible = "nvidia,tegra234-nvdec";
2838cfdd 615 reg = <0x0 0x15480000 0x0 0x00040000>;
68c31ad0
MP		 616 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
617 <&bpmp TEGRA234_CLK_FUSE>,
618 <&bpmp TEGRA234_CLK_TSEC_PKA>;
619 clock-names = "nvdec", "fuse", "tsec_pka";
620 resets = <&bpmp TEGRA234_RESET_NVDEC>;
621 reset-names = "nvdec";
622 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
623 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
624 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
625 interconnect-names = "dma-mem", "write";
626 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
627 dma-coherent;
628
629 nvidia,memory-controller = <&mc>;
630
631 /*
632 * Placeholder values that firmware needs to update with the real
633 * offsets parsed from the microcode headers.
634 */
635 nvidia,bl-manifest-offset = <0>;
636 nvidia,bl-data-offset = <0>;
637 nvidia,bl-code-offset = <0>;
638 nvidia,os-manifest-offset = <0>;
639 nvidia,os-data-offset = <0>;
640 nvidia,os-code-offset = <0>;
641
642 /*
643 * Firmware needs to set this to "okay" once the above values have
644 * been updated.
645 */
646 status = "disabled";
647 };
4bb39ca2
MP		 648 };
649
f0e12668
TR		 650 gpio: gpio@2200000 {
651 compatible = "nvidia,tegra234-gpio";
652 reg-names = "security", "gpio";
2838cfdd
TR		 653 reg = <0x0 0x02200000 0x0 0x10000>,
654 <0x0 0x02210000 0x0 0x10000>;
f0e12668
TR		 655 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
656 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
657 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
660 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
661 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
662 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
663 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
664 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
665 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
666 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
669 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
670 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
671 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
672 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
673 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
674 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
677 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
678 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
679 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
680 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
681 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
682 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
683 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
684 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
685 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
686 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
689 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
690 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
691 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
692 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
693 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
694 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
695 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
698 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
699 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
700 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
701 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
702 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
703 #interrupt-cells = <2>;
704 interrupt-controller;
705 #gpio-cells = <2>;
706 gpio-controller;
707 };
708
eed280df
TR		 709 mc: memory-controller@2c00000 {
710 compatible = "nvidia,tegra234-mc";
2838cfdd
TR		 711 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
712 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
713 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
714 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
715 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
716 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
717 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
718 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
719 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
720 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
721 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
722 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
723 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
724 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
725 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
726 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
727 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
728 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
000b99e5
AM		 729 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
730 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
731 "ch11", "ch12", "ch13", "ch14", "ch15";
eed280df
TR		 732 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
733 #interconnect-cells = <1>;
734 status = "okay";
735
736 #address-cells = <2>;
737 #size-cells = <2>;
2838cfdd
TR		 738 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
739 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
740 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
eed280df
TR		 741
742 /*
743 * Bit 39 of addresses passing through the memory
744 * controller selects the XBAR format used when memory
745 * is accessed. This is used to transparently access
746 * memory in the XBAR format used by the discrete GPU
747 * (bit 39 set) or Tegra (bit 39 clear).
748 *
749 * As a consequence, the operating system must ensure
750 * that bit 39 is never used implicitly, for example
751 * via an I/O virtual address mapping of an IOMMU. If
752 * devices require access to the XBAR switch, their
753 * drivers must set this bit explicitly.
754 *
755 * Limit the DMA range for memory clients to [38:0].
756 */
2838cfdd 757 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
eed280df
TR		 758
759 emc: external-memory-controller@2c60000 {
760 compatible = "nvidia,tegra234-emc";
761 reg = <0x0 0x02c60000 0x0 0x90000>,
762 <0x0 0x01780000 0x0 0x80000>;
763 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
764 clocks = <&bpmp TEGRA234_CLK_EMC>;
765 clock-names = "emc";
766 status = "okay";
767
768 #interconnect-cells = <0>;
769
770 nvidia,bpmp = <&bpmp>;
771 };
772 };
773
63944891
TR		 774 uarta: serial@3100000 {
775 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2838cfdd 776 reg = <0x0 0x03100000 0x0 0x10000>;
63944891
TR		 777 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
778 clocks = <&bpmp TEGRA234_CLK_UARTA>;
779 clock-names = "serial";
780 resets = <&bpmp TEGRA234_RESET_UARTA>;
781 reset-names = "serial";
782 status = "disabled";
783 };
784
156af9de
A		 785 gen1_i2c: i2c@3160000 {
786 compatible = "nvidia,tegra194-i2c";
2838cfdd 787 reg = <0x0 0x3160000 0x0 0x100>;
156af9de
A		 788 status = "disabled";
789 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
790 clock-frequency = <400000>;
791 clocks = <&bpmp TEGRA234_CLK_I2C1
792 &bpmp TEGRA234_CLK_PLLP_OUT0>;
793 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
794 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
795 clock-names = "div-clk", "parent";
796 resets = <&bpmp TEGRA234_RESET_I2C1>;
797 reset-names = "i2c";
8e442805
A		 798 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
799 dma-coherent;
800 dmas = <&gpcdma 21>, <&gpcdma 21>;
801 dma-names = "rx", "tx";
156af9de
A		 802 };
803
804 cam_i2c: i2c@3180000 {
805 compatible = "nvidia,tegra194-i2c";
2838cfdd 806 reg = <0x0 0x3180000 0x0 0x100>;
156af9de
A		 807 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
808 status = "disabled";
809 clock-frequency = <400000>;
810 clocks = <&bpmp TEGRA234_CLK_I2C3
811 &bpmp TEGRA234_CLK_PLLP_OUT0>;
812 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
813 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
814 clock-names = "div-clk", "parent";
815 resets = <&bpmp TEGRA234_RESET_I2C3>;
816 reset-names = "i2c";
8e442805
A		 817 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
818 dma-coherent;
819 dmas = <&gpcdma 23>, <&gpcdma 23>;
820 dma-names = "rx", "tx";
156af9de
A		 821 };
822
823 dp_aux_ch1_i2c: i2c@3190000 {
824 compatible = "nvidia,tegra194-i2c";
2838cfdd 825 reg = <0x0 0x3190000 0x0 0x100>;
156af9de
A		 826 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
827 status = "disabled";
828 clock-frequency = <100000>;
829 clocks = <&bpmp TEGRA234_CLK_I2C4
830 &bpmp TEGRA234_CLK_PLLP_OUT0>;
831 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
832 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
833 clock-names = "div-clk", "parent";
834 resets = <&bpmp TEGRA234_RESET_I2C4>;
835 reset-names = "i2c";
8e442805
A		 836 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
837 dma-coherent;
838 dmas = <&gpcdma 26>, <&gpcdma 26>;
839 dma-names = "rx", "tx";
156af9de
A		 840 };
841
842 dp_aux_ch0_i2c: i2c@31b0000 {
843 compatible = "nvidia,tegra194-i2c";
2838cfdd 844 reg = <0x0 0x31b0000 0x0 0x100>;
156af9de
A		 845 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
846 status = "disabled";
847 clock-frequency = <100000>;
848 clocks = <&bpmp TEGRA234_CLK_I2C6
849 &bpmp TEGRA234_CLK_PLLP_OUT0>;
850 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
851 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
852 clock-names = "div-clk", "parent";
853 resets = <&bpmp TEGRA234_RESET_I2C6>;
854 reset-names = "i2c";
8e442805
A		 855 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
856 dma-coherent;
857 dmas = <&gpcdma 30>, <&gpcdma 30>;
858 dma-names = "rx", "tx";
156af9de
A		 859 };
860
861 dp_aux_ch2_i2c: i2c@31c0000 {
862 compatible = "nvidia,tegra194-i2c";
2838cfdd 863 reg = <0x0 0x31c0000 0x0 0x100>;
156af9de
A		 864 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
865 status = "disabled";
866 clock-frequency = <100000>;
867 clocks = <&bpmp TEGRA234_CLK_I2C7
868 &bpmp TEGRA234_CLK_PLLP_OUT0>;
869 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
870 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
871 clock-names = "div-clk", "parent";
872 resets = <&bpmp TEGRA234_RESET_I2C7>;
873 reset-names = "i2c";
8e442805
A		 874 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
875 dma-coherent;
876 dmas = <&gpcdma 27>, <&gpcdma 27>;
877 dma-names = "rx", "tx";
156af9de
A		 878 };
879
1bbba854
JH		 880 uarti: serial@31d0000 {
881 compatible = "arm,sbsa-uart";
2838cfdd 882 reg = <0x0 0x31d0000 0x0 0x10000>;
1bbba854
JH		 883 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
884 status = "disabled";
885 };
886
156af9de
A		 887 dp_aux_ch3_i2c: i2c@31e0000 {
888 compatible = "nvidia,tegra194-i2c";
2838cfdd 889 reg = <0x0 0x31e0000 0x0 0x100>;
156af9de
A		 890 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
891 status = "disabled";
892 clock-frequency = <100000>;
893 clocks = <&bpmp TEGRA234_CLK_I2C9
894 &bpmp TEGRA234_CLK_PLLP_OUT0>;
895 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
896 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
897 clock-names = "div-clk", "parent";
898 resets = <&bpmp TEGRA234_RESET_I2C9>;
899 reset-names = "i2c";
8e442805
A		 900 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
901 dma-coherent;
902 dmas = <&gpcdma 31>, <&gpcdma 31>;
903 dma-names = "rx", "tx";
156af9de
A		 904 };
905
71f69ffa
AS		 906 spi@3270000 {
907 compatible = "nvidia,tegra234-qspi";
2838cfdd 908 reg = <0x0 0x3270000 0x0 0x1000>;
71f69ffa
AS		 909 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
910 #address-cells = <1>;
911 #size-cells = <0>;
912 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
913 <&bpmp TEGRA234_CLK_QSPI0_PM>;
914 clock-names = "qspi", "qspi_out";
915 resets = <&bpmp TEGRA234_RESET_QSPI0>;
71f69ffa
AS		 916 status = "disabled";
917 };
918
5e69088d 919 pwm1: pwm@3280000 {
2566d28c 920 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 921 reg = <0x0 0x3280000 0x0 0x10000>;
5e69088d 922 clocks = <&bpmp TEGRA234_CLK_PWM1>;
5e69088d
A		 923 resets = <&bpmp TEGRA234_RESET_PWM1>;
924 reset-names = "pwm";
925 status = "disabled";
926 #pwm-cells = <2>;
927 };
928
2566d28c
JH		 929 pwm2: pwm@3290000 {
930 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 931 reg = <0x0 0x3290000 0x0 0x10000>;
2566d28c 932 clocks = <&bpmp TEGRA234_CLK_PWM2>;
2566d28c
JH		 933 resets = <&bpmp TEGRA234_RESET_PWM2>;
934 reset-names = "pwm";
935 status = "disabled";
936 #pwm-cells = <2>;
937 };
938
939 pwm3: pwm@32a0000 {
940 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 941 reg = <0x0 0x32a0000 0x0 0x10000>;
2566d28c 942 clocks = <&bpmp TEGRA234_CLK_PWM3>;
2566d28c
JH		 943 resets = <&bpmp TEGRA234_RESET_PWM3>;
944 reset-names = "pwm";
945 status = "disabled";
946 #pwm-cells = <2>;
947 };
948
949 pwm5: pwm@32c0000 {
950 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 951 reg = <0x0 0x32c0000 0x0 0x10000>;
2566d28c 952 clocks = <&bpmp TEGRA234_CLK_PWM5>;
2566d28c
JH		 953 resets = <&bpmp TEGRA234_RESET_PWM5>;
954 reset-names = "pwm";
955 status = "disabled";
956 #pwm-cells = <2>;
957 };
958
959 pwm6: pwm@32d0000 {
960 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 961 reg = <0x0 0x32d0000 0x0 0x10000>;
2566d28c 962 clocks = <&bpmp TEGRA234_CLK_PWM6>;
2566d28c
JH		 963 resets = <&bpmp TEGRA234_RESET_PWM6>;
964 reset-names = "pwm";
965 status = "disabled";
966 #pwm-cells = <2>;
967 };
968
969 pwm7: pwm@32e0000 {
970 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 971 reg = <0x0 0x32e0000 0x0 0x10000>;
2566d28c 972 clocks = <&bpmp TEGRA234_CLK_PWM7>;
2566d28c
JH		 973 resets = <&bpmp TEGRA234_RESET_PWM7>;
974 reset-names = "pwm";
975 status = "disabled";
976 #pwm-cells = <2>;
977 };
978
979 pwm8: pwm@32f0000 {
980 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 981 reg = <0x0 0x32f0000 0x0 0x10000>;
2566d28c 982 clocks = <&bpmp TEGRA234_CLK_PWM8>;
2566d28c
JH		 983 resets = <&bpmp TEGRA234_RESET_PWM8>;
984 reset-names = "pwm";
985 status = "disabled";
986 #pwm-cells = <2>;
987 };
988
71f69ffa
AS		 989 spi@3300000 {
990 compatible = "nvidia,tegra234-qspi";
2838cfdd 991 reg = <0x0 0x3300000 0x0 0x1000>;
71f69ffa
AS		 992 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
993 #address-cells = <1>;
994 #size-cells = <0>;
995 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
996 <&bpmp TEGRA234_CLK_QSPI1_PM>;
997 clock-names = "qspi", "qspi_out";
998 resets = <&bpmp TEGRA234_RESET_QSPI1>;
71f69ffa
AS		 999 status = "disabled";
1000 };
1001
d71b893a 1002 mmc@3400000 {
132b552c 1003 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
2838cfdd 1004 reg = <0x0 0x03400000 0x0 0x20000>;
d71b893a
PS		 1005 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1006 clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
1007 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
1008 clock-names = "sdhci", "tmclk";
1009 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
1010 <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
1011 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
1012 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
1013 resets = <&bpmp TEGRA234_RESET_SDMMC1>;
1014 reset-names = "sdhci";
1015 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
1016 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
1017 interconnect-names = "dma-mem", "write";
1018 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
1019 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
1020 pinctrl-0 = <&sdmmc1_3v3>;
1021 pinctrl-1 = <&sdmmc1_1v8>;
1022 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
1023 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
1024 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
1025 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
1026 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
1027 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
1028 nvidia,default-tap = <14>;
1029 nvidia,default-trim = <0x8>;
1030 sd-uhs-sdr25;
1031 sd-uhs-sdr50;
1032 sd-uhs-ddr50;
1033 sd-uhs-sdr104;
1034 status = "disabled";
1035 };
1036
63944891
TR		 1037 mmc@3460000 {
1038 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
2838cfdd 1039 reg = <0x0 0x03460000 0x0 0x20000>;
63944891 1040 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
e086d82d
MP		 1041 clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
1042 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
1043 clock-names = "sdhci", "tmclk";
1044 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
1045 <&bpmp TEGRA234_CLK_PLLC4>;
1046 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
63944891
TR		 1047 resets = <&bpmp TEGRA234_RESET_SDMMC4>;
1048 reset-names = "sdhci";
6de481e5
TR		 1049 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
1050 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
1051 interconnect-names = "dma-mem", "write";
5710e16a 1052 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
e086d82d
MP		 1053 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1054 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1055 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1056 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1057 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1058 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
1059 nvidia,default-tap = <0x8>;
1060 nvidia,default-trim = <0x14>;
1061 nvidia,dqs-trim = <40>;
1062 supports-cqe;
63944891
TR		 1063 status = "disabled";
1064 };
1065
621e12a1 1066 hda@3510000 {
b2fbcbe1 1067 compatible = "nvidia,tegra234-hda";
2838cfdd 1068 reg = <0x0 0x3510000 0x0 0x10000>;
621e12a1
MK		 1069 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
1070 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
1071 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
1072 clock-names = "hda", "hda2codec_2x";
1073 resets = <&bpmp TEGRA234_RESET_HDA>,
1074 <&bpmp TEGRA234_RESET_HDACODEC>;
1075 reset-names = "hda", "hda2codec_2x";
1076 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
1077 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
1078 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
1079 interconnect-names = "dma-mem", "write";
af4c2773 1080 iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
621e12a1
MK		 1081 status = "disabled";
1082 };
1083
63944891
TR		 1084 fuse@3810000 {
1085 compatible = "nvidia,tegra234-efuse";
2838cfdd 1086 reg = <0x0 0x03810000 0x0 0x10000>;
63944891
TR		 1087 clocks = <&bpmp TEGRA234_CLK_FUSE>;
1088 clock-names = "fuse";
1089 };
1090
1091 hsp_top0: hsp@3c00000 {
1092 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
2838cfdd 1093 reg = <0x0 0x03c00000 0x0 0xa0000>;
63944891
TR		 1094 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1095 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1096 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1097 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1098 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1099 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1100 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1101 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1102 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1103 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1104 "shared3", "shared4", "shared5", "shared6",
1105 "shared7";
1106 #mbox-cells = <2>;
1107 };
1108
78159542
TR		 1109 p2u_hsio_0: phy@3e00000 {
1110 compatible = "nvidia,tegra234-p2u";
2838cfdd 1111 reg = <0x0 0x03e00000 0x0 0x10000>;
78159542
TR		 1112 reg-names = "ctl";
1113
1114 #phy-cells = <0>;
1115 };
1116
1117 p2u_hsio_1: phy@3e10000 {
1118 compatible = "nvidia,tegra234-p2u";
2838cfdd 1119 reg = <0x0 0x03e10000 0x0 0x10000>;
78159542
TR		 1120 reg-names = "ctl";
1121
1122 #phy-cells = <0>;
1123 };
1124
1125 p2u_hsio_2: phy@3e20000 {
1126 compatible = "nvidia,tegra234-p2u";
2838cfdd 1127 reg = <0x0 0x03e20000 0x0 0x10000>;
78159542
TR		 1128 reg-names = "ctl";
1129
1130 #phy-cells = <0>;
1131 };
1132
1133 p2u_hsio_3: phy@3e30000 {
1134 compatible = "nvidia,tegra234-p2u";
2838cfdd 1135 reg = <0x0 0x03e30000 0x0 0x10000>;
78159542
TR		 1136 reg-names = "ctl";
1137
1138 #phy-cells = <0>;
1139 };
1140
1141 p2u_hsio_4: phy@3e40000 {
1142 compatible = "nvidia,tegra234-p2u";
2838cfdd 1143 reg = <0x0 0x03e40000 0x0 0x10000>;
78159542
TR		 1144 reg-names = "ctl";
1145
1146 #phy-cells = <0>;
1147 };
1148
1149 p2u_hsio_5: phy@3e50000 {
1150 compatible = "nvidia,tegra234-p2u";
2838cfdd 1151 reg = <0x0 0x03e50000 0x0 0x10000>;
78159542
TR		 1152 reg-names = "ctl";
1153
1154 #phy-cells = <0>;
1155 };
1156
1157 p2u_hsio_6: phy@3e60000 {
1158 compatible = "nvidia,tegra234-p2u";
2838cfdd 1159 reg = <0x0 0x03e60000 0x0 0x10000>;
78159542
TR		 1160 reg-names = "ctl";
1161
1162 #phy-cells = <0>;
1163 };
1164
1165 p2u_hsio_7: phy@3e70000 {
1166 compatible = "nvidia,tegra234-p2u";
2838cfdd 1167 reg = <0x0 0x03e70000 0x0 0x10000>;
78159542
TR		 1168 reg-names = "ctl";
1169
1170 #phy-cells = <0>;
1171 };
1172
1173 p2u_nvhs_0: phy@3e90000 {
1174 compatible = "nvidia,tegra234-p2u";
2838cfdd 1175 reg = <0x0 0x03e90000 0x0 0x10000>;
78159542
TR		 1176 reg-names = "ctl";
1177
1178 #phy-cells = <0>;
1179 };
1180
1181 p2u_nvhs_1: phy@3ea0000 {
1182 compatible = "nvidia,tegra234-p2u";
2838cfdd 1183 reg = <0x0 0x03ea0000 0x0 0x10000>;
78159542
TR		 1184 reg-names = "ctl";
1185
1186 #phy-cells = <0>;
1187 };
1188
1189 p2u_nvhs_2: phy@3eb0000 {
1190 compatible = "nvidia,tegra234-p2u";
2838cfdd 1191 reg = <0x0 0x03eb0000 0x0 0x10000>;
78159542
TR		 1192 reg-names = "ctl";
1193
1194 #phy-cells = <0>;
1195 };
1196
1197 p2u_nvhs_3: phy@3ec0000 {
1198 compatible = "nvidia,tegra234-p2u";
2838cfdd 1199 reg = <0x0 0x03ec0000 0x0 0x10000>;
78159542
TR		 1200 reg-names = "ctl";
1201
1202 #phy-cells = <0>;
1203 };
1204
1205 p2u_nvhs_4: phy@3ed0000 {
1206 compatible = "nvidia,tegra234-p2u";
2838cfdd 1207 reg = <0x0 0x03ed0000 0x0 0x10000>;
78159542
TR		 1208 reg-names = "ctl";
1209
1210 #phy-cells = <0>;
1211 };
1212
1213 p2u_nvhs_5: phy@3ee0000 {
1214 compatible = "nvidia,tegra234-p2u";
2838cfdd 1215 reg = <0x0 0x03ee0000 0x0 0x10000>;
78159542
TR		 1216 reg-names = "ctl";
1217
1218 #phy-cells = <0>;
1219 };
1220
1221 p2u_nvhs_6: phy@3ef0000 {
1222 compatible = "nvidia,tegra234-p2u";
2838cfdd 1223 reg = <0x0 0x03ef0000 0x0 0x10000>;
78159542
TR		 1224 reg-names = "ctl";
1225
1226 #phy-cells = <0>;
1227 };
1228
1229 p2u_nvhs_7: phy@3f00000 {
1230 compatible = "nvidia,tegra234-p2u";
2838cfdd 1231 reg = <0x0 0x03f00000 0x0 0x10000>;
78159542
TR		 1232 reg-names = "ctl";
1233
1234 #phy-cells = <0>;
1235 };
1236
1237 p2u_gbe_0: phy@3f20000 {
1238 compatible = "nvidia,tegra234-p2u";
2838cfdd 1239 reg = <0x0 0x03f20000 0x0 0x10000>;
78159542
TR		 1240 reg-names = "ctl";
1241
1242 #phy-cells = <0>;
1243 };
1244
1245 p2u_gbe_1: phy@3f30000 {
1246 compatible = "nvidia,tegra234-p2u";
2838cfdd 1247 reg = <0x0 0x03f30000 0x0 0x10000>;
78159542
TR		 1248 reg-names = "ctl";
1249
1250 #phy-cells = <0>;
1251 };
1252
1253 p2u_gbe_2: phy@3f40000 {
1254 compatible = "nvidia,tegra234-p2u";
2838cfdd 1255 reg = <0x0 0x03f40000 0x0 0x10000>;
78159542
TR		 1256 reg-names = "ctl";
1257
1258 #phy-cells = <0>;
1259 };
1260
1261 p2u_gbe_3: phy@3f50000 {
1262 compatible = "nvidia,tegra234-p2u";
2838cfdd 1263 reg = <0x0 0x03f50000 0x0 0x10000>;
78159542
TR		 1264 reg-names = "ctl";
1265
1266 #phy-cells = <0>;
1267 };
1268
1269 p2u_gbe_4: phy@3f60000 {
1270 compatible = "nvidia,tegra234-p2u";
2838cfdd 1271 reg = <0x0 0x03f60000 0x0 0x10000>;
78159542
TR		 1272 reg-names = "ctl";
1273
1274 #phy-cells = <0>;
1275 };
1276
1277 p2u_gbe_5: phy@3f70000 {
1278 compatible = "nvidia,tegra234-p2u";
2838cfdd 1279 reg = <0x0 0x03f70000 0x0 0x10000>;
78159542
TR		 1280 reg-names = "ctl";
1281
1282 #phy-cells = <0>;
1283 };
1284
1285 p2u_gbe_6: phy@3f80000 {
1286 compatible = "nvidia,tegra234-p2u";
2838cfdd 1287 reg = <0x0 0x03f80000 0x0 0x10000>;
78159542
TR		 1288 reg-names = "ctl";
1289
1290 #phy-cells = <0>;
1291 };
1292
1293 p2u_gbe_7: phy@3f90000 {
1294 compatible = "nvidia,tegra234-p2u";
2838cfdd 1295 reg = <0x0 0x03f90000 0x0 0x10000>;
78159542
TR		 1296 reg-names = "ctl";
1297
1298 #phy-cells = <0>;
1299 };
1300
610cdf31
TR		 1301 ethernet@6800000 {
1302 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1303 reg = <0x0 0x06800000 0x0 0x10000>,
1304 <0x0 0x06810000 0x0 0x10000>,
1305 <0x0 0x068a0000 0x0 0x10000>;
610cdf31
TR		 1306 reg-names = "hypervisor", "mac", "xpcs";
1307 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
1308 interrupt-names = "common";
1309 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
1310 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
1311 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
1312 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
1313 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
1314 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
1315 <&bpmp TEGRA234_CLK_MGBE0_TX>,
1316 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
1317 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
1318 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
1319 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
1320 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
1321 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1322 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1323 "rx-pcs", "tx-pcs";
1324 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
1325 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
1326 reset-names = "mac", "pcs";
1327 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
1328 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
1329 interconnect-names = "dma-mem", "write";
1330 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
1331 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1332 status = "disabled";
1333 };
1334
1335 ethernet@6900000 {
1336 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1337 reg = <0x0 0x06900000 0x0 0x10000>,
1338 <0x0 0x06910000 0x0 0x10000>,
1339 <0x0 0x069a0000 0x0 0x10000>;
610cdf31
TR		 1340 reg-names = "hypervisor", "mac", "xpcs";
1341 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
1342 interrupt-names = "common";
1343 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1344 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1345 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1346 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1347 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1348 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1349 <&bpmp TEGRA234_CLK_MGBE1_TX>,
1350 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1351 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1352 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1353 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1354 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1355 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1356 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1357 "rx-pcs", "tx-pcs";
1358 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1359 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1360 reset-names = "mac", "pcs";
1361 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
1362 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
1363 interconnect-names = "dma-mem", "write";
1364 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
1365 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1366 status = "disabled";
1367 };
1368
1369 ethernet@6a00000 {
1370 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1371 reg = <0x0 0x06a00000 0x0 0x10000>,
1372 <0x0 0x06a10000 0x0 0x10000>,
1373 <0x0 0x06aa0000 0x0 0x10000>;
610cdf31
TR		 1374 reg-names = "hypervisor", "mac", "xpcs";
1375 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
1376 interrupt-names = "common";
1377 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1378 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1379 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1380 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1381 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1382 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1383 <&bpmp TEGRA234_CLK_MGBE2_TX>,
1384 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1385 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1386 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1387 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1388 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1389 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1390 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1391 "rx-pcs", "tx-pcs";
1392 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1393 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1394 reset-names = "mac", "pcs";
1395 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
1396 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
1397 interconnect-names = "dma-mem", "write";
1398 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
1399 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1400 status = "disabled";
1401 };
1402
1403 ethernet@6b00000 {
1404 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1405 reg = <0x0 0x06b00000 0x0 0x10000>,
1406 <0x0 0x06b10000 0x0 0x10000>,
1407 <0x0 0x06ba0000 0x0 0x10000>;
610cdf31
TR		 1408 reg-names = "hypervisor", "mac", "xpcs";
1409 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1410 interrupt-names = "common";
1411 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1412 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1413 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1414 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1415 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1416 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1417 <&bpmp TEGRA234_CLK_MGBE3_TX>,
1418 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1419 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1420 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1421 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1422 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1423 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1424 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1425 "rx-pcs", "tx-pcs";
1426 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1427 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1428 reset-names = "mac", "pcs";
1429 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
1430 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
1431 interconnect-names = "dma-mem", "write";
1432 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
1433 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1434 status = "disabled";
1435 };
1436
5710e16a
TR		 1437 smmu_niso1: iommu@8000000 {
1438 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd
TR		 1439 reg = <0x0 0x8000000 0x0 0x1000000>,
1440 <0x0 0x7000000 0x0 0x1000000>;
5710e16a
TR		 1441 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1442 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1443 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1444 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1445 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1446 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1447 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1448 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1449 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1450 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1451 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1452 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1453 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1454 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1455 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1456 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1457 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1458 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1459 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1460 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1461 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1462 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1463 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1464 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1465 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1466 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1467 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1468 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1469 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1470 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1471 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1472 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1473 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1474 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1475 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1476 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1477 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1478 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1479 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1480 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1481 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1482 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1483 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1484 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1485 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1486 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1487 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1488 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1489 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1490 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1491 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1492 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1493 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1494 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1495 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1496 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1497 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1498 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1499 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1500 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1501 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1502 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1503 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1504 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1505 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1506 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1507 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1508 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1509 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1510 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1511 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1512 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1513 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1514 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1515 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1516 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1517 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1518 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1519 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1520 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1521 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1522 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1523 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1524 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1571 stream-match-mask = <0x7f80>;
1572 #global-interrupts = <2>;
1573 #iommu-cells = <1>;
1574
1575 nvidia,memory-controller = <&mc>;
1576 status = "okay";
1577 };
1578
302e1540
SG		 1579 sce-fabric@b600000 {
1580 compatible = "nvidia,tegra234-sce-fabric";
2838cfdd 1581 reg = <0x0 0xb600000 0x0 0x40000>;
302e1540
SG		 1582 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
1583 status = "okay";
1584 };
1585
1586 rce-fabric@be00000 {
1587 compatible = "nvidia,tegra234-rce-fabric";
2838cfdd 1588 reg = <0x0 0xbe00000 0x0 0x40000>;
302e1540
SG		 1589 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1590 status = "okay";
1591 };
1592
63944891
TR		 1593 hsp_aon: hsp@c150000 {
1594 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
2838cfdd 1595 reg = <0x0 0x0c150000 0x0 0x90000>;
63944891
TR		 1596 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1597 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1598 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1599 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1600 /*
1601 * Shared interrupt 0 is routed only to AON/SPE, so
1602 * we only have 4 shared interrupts for the CCPLEX.
1603 */
1604 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1605 #mbox-cells = <2>;
1606 };
1607
156af9de
A		 1608 gen2_i2c: i2c@c240000 {
1609 compatible = "nvidia,tegra194-i2c";
2838cfdd 1610 reg = <0x0 0xc240000 0x0 0x100>;
156af9de
A		 1611 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1612 status = "disabled";
1613 clock-frequency = <100000>;
1614 clocks = <&bpmp TEGRA234_CLK_I2C2
1615 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1616 clock-names = "div-clk", "parent";
1617 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1618 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1619 resets = <&bpmp TEGRA234_RESET_I2C2>;
1620 reset-names = "i2c";
8e442805
A		 1621 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
1622 dma-coherent;
1623 dmas = <&gpcdma 22>, <&gpcdma 22>;
1624 dma-names = "rx", "tx";
156af9de
A		 1625 };
1626
1627 gen8_i2c: i2c@c250000 {
1628 compatible = "nvidia,tegra194-i2c";
2838cfdd 1629 reg = <0x0 0xc250000 0x0 0x100>;
156af9de
A		 1630 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1631 status = "disabled";
1632 clock-frequency = <400000>;
1633 clocks = <&bpmp TEGRA234_CLK_I2C8
1634 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1635 clock-names = "div-clk", "parent";
1636 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1637 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1638 resets = <&bpmp TEGRA234_RESET_I2C8>;
1639 reset-names = "i2c";
8e442805
A		 1640 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
1641 dma-coherent;
1642 dmas = <&gpcdma 0>, <&gpcdma 0>;
1643 dma-names = "rx", "tx";
156af9de
A		 1644 };
1645
63944891
TR		 1646 rtc@c2a0000 {
1647 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
2838cfdd 1648 reg = <0x0 0x0c2a0000 0x0 0x10000>;
63944891
TR		 1649 interrupt-parent = <&pmc>;
1650 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
e537adde
MP		 1651 clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1652 clock-names = "rtc";
63944891
TR		 1653 status = "disabled";
1654 };
1655
f0e12668
TR		 1656 gpio_aon: gpio@c2f0000 {
1657 compatible = "nvidia,tegra234-gpio-aon";
1658 reg-names = "security", "gpio";
2838cfdd
TR		 1659 reg = <0x0 0x0c2f0000 0x0 0x1000>,
1660 <0x0 0x0c2f1000 0x0 0x1000>;
f0e12668
TR		 1661 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1662 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1663 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1664 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1665 #interrupt-cells = <2>;
1666 interrupt-controller;
1667 #gpio-cells = <2>;
1668 gpio-controller;
1669 };
1670
2566d28c
JH		 1671 pwm4: pwm@c340000 {
1672 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 1673 reg = <0x0 0xc340000 0x0 0x10000>;
2566d28c 1674 clocks = <&bpmp TEGRA234_CLK_PWM4>;
2566d28c
JH		 1675 resets = <&bpmp TEGRA234_RESET_PWM4>;
1676 reset-names = "pwm";
1677 status = "disabled";
1678 #pwm-cells = <2>;
1679 };
1680
63944891
TR		 1681 pmc: pmc@c360000 {
1682 compatible = "nvidia,tegra234-pmc";
2838cfdd
TR		 1683 reg = <0x0 0x0c360000 0x0 0x10000>,
1684 <0x0 0x0c370000 0x0 0x10000>,
1685 <0x0 0x0c380000 0x0 0x10000>,
1686 <0x0 0x0c390000 0x0 0x10000>,
1687 <0x0 0x0c3a0000 0x0 0x10000>;
63944891
TR		 1688 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1689
1690 #interrupt-cells = <2>;
1691 interrupt-controller;
d71b893a
PS		 1692
1693 sdmmc1_3v3: sdmmc1-3v3 {
1694 pins = "sdmmc1-hv";
1695 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1696 };
1697
1698 sdmmc1_1v8: sdmmc1-1v8 {
1699 pins = "sdmmc1-hv";
1700 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1701 };
1702
1703 sdmmc3_3v3: sdmmc3-3v3 {
1704 pins = "sdmmc3-hv";
1705 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1706 };
1707
1708 sdmmc3_1v8: sdmmc3-1v8 {
1709 pins = "sdmmc3-hv";
1710 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1711 };
63944891
TR		 1712 };
1713
302e1540
SG		 1714 aon-fabric@c600000 {
1715 compatible = "nvidia,tegra234-aon-fabric";
2838cfdd 1716 reg = <0x0 0xc600000 0x0 0x40000>;
302e1540
SG		 1717 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1718 status = "okay";
1719 };
1720
1721 bpmp-fabric@d600000 {
1722 compatible = "nvidia,tegra234-bpmp-fabric";
2838cfdd 1723 reg = <0x0 0xd600000 0x0 0x40000>;
302e1540
SG		 1724 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1725 status = "okay";
1726 };
1727
1728 dce-fabric@de00000 {
1729 compatible = "nvidia,tegra234-sce-fabric";
2838cfdd 1730 reg = <0x0 0xde00000 0x0 0x40000>;
302e1540
SG		 1731 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
1732 status = "okay";
1733 };
1734
2838cfdd
TR		 1735 ccplex@e000000 {
1736 compatible = "nvidia,tegra234-ccplex-cluster";
1737 reg = <0x0 0x0e000000 0x0 0x5ffff>;
1738 nvidia,bpmp = <&bpmp>;
1739 status = "okay";
1740 };
1741
63944891
TR		 1742 gic: interrupt-controller@f400000 {
1743 compatible = "arm,gic-v3";
2838cfdd
TR		 1744 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
1745 <0x0 0x0f440000 0x0 0x200000>; /* GICR */
63944891
TR		 1746 interrupt-parent = <&gic>;
1747 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1748
1749 #redistributor-regions = <1>;
1750 #interrupt-cells = <3>;
1751 interrupt-controller;
1752 };
5710e16a 1753
58bf48a2 1754 smmu_iso: iommu@10000000 {
5710e16a 1755 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd 1756 reg = <0x0 0x10000000 0x0 0x1000000>;
5710e16a
TR		 1757 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1758 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1759 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1760 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1761 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1765 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1766 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1767 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1768 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1769 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1770 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1771 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1772 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1773 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1774 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1775 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1776 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1777 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1778 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1779 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1780 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1781 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1782 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1783 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1784 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1785 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1786 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1787 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1788 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1789 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1790 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1791 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1792 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1793 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1794 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1795 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1796 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1797 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1798 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1799 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1800 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1801 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1802 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1803 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1804 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1805 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1806 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1807 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1808 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1809 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1810 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1811 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1812 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1813 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1814 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1815 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1816 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1817 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1818 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1819 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1820 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1821 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1822 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1823 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1824 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1825 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1826 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1827 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1829 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1830 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1831 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1832 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1833 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1834 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1835 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1836 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1837 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1838 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1839 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1840 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1841 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1842 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1843 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1844 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1846 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1847 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1848 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1849 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1850 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1851 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1852 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1853 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1854 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1886 stream-match-mask = <0x7f80>;
1887 #global-interrupts = <1>;
1888 #iommu-cells = <1>;
1889
1890 nvidia,memory-controller = <&mc>;
1891 status = "okay";
1892 };
1893
1894 smmu_niso0: iommu@12000000 {
1895 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd
TR		 1896 reg = <0x0 0x12000000 0x0 0x1000000>,
1897 <0x0 0x11000000 0x0 0x1000000>;
5710e16a
TR		 1898 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1899 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1900 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1901 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1902 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1903 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1907 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1908 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1909 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1910 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1911 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1912 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1914 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1918 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1919 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1920 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1921 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1923 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1930 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1932 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1933 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1934 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1935 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1936 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1937 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1938 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1939 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1955 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1964 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1972 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1973 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1974 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1975 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1976 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1977 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1978 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1979 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1980 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1981 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1984 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1985 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1986 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1987 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1988 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1989 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1990 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1991 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1992 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1993 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1994 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1995 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1996 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1998 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2028 stream-match-mask = <0x7f80>;
2029 #global-interrupts = <2>;
2030 #iommu-cells = <1>;
2031
2032 nvidia,memory-controller = <&mc>;
2033 status = "okay";
2034 };
302e1540
SG		 2035
2036 cbb-fabric@13a00000 {
2037 compatible = "nvidia,tegra234-cbb-fabric";
2838cfdd 2038 reg = <0x0 0x13a00000 0x0 0x400000>;
302e1540
SG		 2039 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
2040 status = "okay";
2041 };
63944891 2042
2838cfdd
TR		 2043 pcie@140a0000 {
2044 compatible = "nvidia,tegra234-pcie";
2045 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2046 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
2047 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
2048 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2049 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2050 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2051 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
962c400d 2052
2838cfdd
TR		 2053 #address-cells = <3>;
2054 #size-cells = <2>;
2055 device_type = "pci";
2056 num-lanes = <4>;
2057 num-viewport = <8>;
2058 linux,pci-domain = <8>;
ec142c44 2059
2838cfdd
TR		 2060 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
2061 clock-names = "core";
ec142c44 2062
2838cfdd
TR		 2063 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
2064 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
2065 reset-names = "apb", "core";
ec142c44 2066
2838cfdd
TR		 2067 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2068 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2069 interrupt-names = "intr", "msi";
ec142c44 2070
2838cfdd
TR		 2071 #interrupt-cells = <1>;
2072 interrupt-map-mask = <0 0 0 0>;
2073 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2074
2838cfdd 2075 nvidia,bpmp = <&bpmp 8>;
ec142c44 2076
2838cfdd
TR		 2077 nvidia,aspm-cmrt-us = <60>;
2078 nvidia,aspm-pwr-on-t-us = <20>;
2079 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2080
2838cfdd 2081 bus-range = <0x0 0xff>;
ec142c44 2082
2838cfdd
TR		 2083 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2084 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2085 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2086
2838cfdd
TR		 2087 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
2088 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
2089 interconnect-names = "dma-mem", "write";
2090 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2091 iommu-map-mask = <0x0>;
2092 dma-coherent;
ec142c44 2093
2838cfdd
TR		 2094 status = "disabled";
2095 };
ec142c44 2096
2838cfdd
TR		 2097 pcie@140c0000 {
2098 compatible = "nvidia,tegra234-pcie";
2099 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2100 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
2101 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
2102 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2103 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2104 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2105 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2106
2838cfdd
TR		 2107 #address-cells = <3>;
2108 #size-cells = <2>;
2109 device_type = "pci";
2110 num-lanes = <4>;
2111 num-viewport = <8>;
2112 linux,pci-domain = <9>;
ec142c44 2113
2838cfdd
TR		 2114 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
2115 clock-names = "core";
ec142c44 2116
2838cfdd
TR		 2117 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
2118 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
2119 reset-names = "apb", "core";
ec142c44 2120
2838cfdd
TR		 2121 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2122 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2123 interrupt-names = "intr", "msi";
ec142c44 2124
2838cfdd
TR		 2125 #interrupt-cells = <1>;
2126 interrupt-map-mask = <0 0 0 0>;
2127 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2128
2838cfdd 2129 nvidia,bpmp = <&bpmp 9>;
ec142c44 2130
2838cfdd
TR		 2131 nvidia,aspm-cmrt-us = <60>;
2132 nvidia,aspm-pwr-on-t-us = <20>;
2133 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2134
2838cfdd 2135 bus-range = <0x0 0xff>;
ec142c44 2136
2838cfdd
TR		 2137 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
2138 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2139 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2140
2838cfdd
TR		 2141 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
2142 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
2143 interconnect-names = "dma-mem", "write";
2144 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2145 iommu-map-mask = <0x0>;
2146 dma-coherent;
ec142c44 2147
2838cfdd
TR		 2148 status = "disabled";
2149 };
ec142c44 2150
2838cfdd
TR		 2151 pcie@140e0000 {
2152 compatible = "nvidia,tegra234-pcie";
2153 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2154 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2155 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
2156 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2157 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2158 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2159 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2160
2838cfdd
TR		 2161 #address-cells = <3>;
2162 #size-cells = <2>;
2163 device_type = "pci";
2164 num-lanes = <4>;
2165 num-viewport = <8>;
2166 linux,pci-domain = <10>;
ec142c44 2167
2838cfdd
TR		 2168 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2169 clock-names = "core";
ec142c44 2170
2838cfdd
TR		 2171 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2172 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2173 reset-names = "apb", "core";
ec142c44 2174
2838cfdd
TR		 2175 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2176 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2177 interrupt-names = "intr", "msi";
ec142c44 2178
2838cfdd
TR		 2179 #interrupt-cells = <1>;
2180 interrupt-map-mask = <0 0 0 0>;
2181 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2182
2838cfdd 2183 nvidia,bpmp = <&bpmp 10>;
ec142c44 2184
2838cfdd
TR		 2185 nvidia,aspm-cmrt-us = <60>;
2186 nvidia,aspm-pwr-on-t-us = <20>;
2187 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2188
2838cfdd 2189 bus-range = <0x0 0xff>;
ec142c44 2190
2838cfdd
TR		 2191 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2192 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2193 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2194
2838cfdd
TR		 2195 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2196 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2197 interconnect-names = "dma-mem", "write";
2198 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2199 iommu-map-mask = <0x0>;
2200 dma-coherent;
ec142c44 2201
2838cfdd
TR		 2202 status = "disabled";
2203 };
ec142c44 2204
2838cfdd
TR		 2205 pcie-ep@140e0000 {
2206 compatible = "nvidia,tegra234-pcie-ep";
2207 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2208 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2209 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2210 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
2211 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2212 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2213
2838cfdd 2214 num-lanes = <4>;
ec142c44 2215
2838cfdd
TR		 2216 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2217 clock-names = "core";
ec142c44 2218
2838cfdd
TR		 2219 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2220 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2221 reset-names = "apb", "core";
ec142c44 2222
2838cfdd
TR		 2223 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2224 interrupt-names = "intr";
ec142c44 2225
2838cfdd 2226 nvidia,bpmp = <&bpmp 10>;
ec142c44 2227
2838cfdd
TR		 2228 nvidia,enable-ext-refclk;
2229 nvidia,aspm-cmrt-us = <60>;
2230 nvidia,aspm-pwr-on-t-us = <20>;
2231 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2232
2838cfdd
TR		 2233 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2234 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2235 interconnect-names = "dma-mem", "write";
2236 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2237 iommu-map-mask = <0x0>;
2238 dma-coherent;
ec142c44 2239
2838cfdd
TR		 2240 status = "disabled";
2241 };
ec142c44 2242
2838cfdd
TR		 2243 pcie@14100000 {
2244 compatible = "nvidia,tegra234-pcie";
2245 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2246 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2247 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2248 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2249 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
2250 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
2251 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2252
2838cfdd
TR		 2253 #address-cells = <3>;
2254 #size-cells = <2>;
2255 device_type = "pci";
2256 num-lanes = <1>;
2257 num-viewport = <8>;
2258 linux,pci-domain = <1>;
ec142c44 2259
2838cfdd
TR		 2260 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2261 clock-names = "core";
ec142c44 2262
2838cfdd
TR		 2263 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2264 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2265 reset-names = "apb", "core";
ec142c44 2266
2838cfdd
TR		 2267 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2268 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2269 interrupt-names = "intr", "msi";
ec142c44 2270
2838cfdd
TR		 2271 #interrupt-cells = <1>;
2272 interrupt-map-mask = <0 0 0 0>;
2273 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2274
2838cfdd 2275 nvidia,bpmp = <&bpmp 1>;
ec142c44 2276
2838cfdd
TR		 2277 nvidia,aspm-cmrt-us = <60>;
2278 nvidia,aspm-pwr-on-t-us = <20>;
2279 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2280
2838cfdd 2281 bus-range = <0x0 0xff>;
ec142c44 2282
2838cfdd
TR		 2283 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2284 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2285 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2286
2838cfdd
TR		 2287 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
2288 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
2289 interconnect-names = "dma-mem", "write";
2290 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2291 iommu-map-mask = <0x0>;
2292 dma-coherent;
ec142c44 2293
2838cfdd
TR		 2294 status = "disabled";
2295 };
ec142c44 2296
2838cfdd
TR		 2297 pcie@14120000 {
2298 compatible = "nvidia,tegra234-pcie";
2299 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2300 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2301 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2302 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2303 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
2304 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
2305 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2306
2838cfdd
TR		 2307 #address-cells = <3>;
2308 #size-cells = <2>;
2309 device_type = "pci";
2310 num-lanes = <1>;
2311 num-viewport = <8>;
2312 linux,pci-domain = <2>;
ec142c44 2313
2838cfdd
TR		 2314 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2315 clock-names = "core";
ec142c44 2316
2838cfdd
TR		 2317 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2318 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2319 reset-names = "apb", "core";
ec142c44 2320
2838cfdd
TR		 2321 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2322 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2323 interrupt-names = "intr", "msi";
ec142c44 2324
2838cfdd
TR		 2325 #interrupt-cells = <1>;
2326 interrupt-map-mask = <0 0 0 0>;
2327 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2328
2838cfdd 2329 nvidia,bpmp = <&bpmp 2>;
ec142c44 2330
2838cfdd
TR		 2331 nvidia,aspm-cmrt-us = <60>;
2332 nvidia,aspm-pwr-on-t-us = <20>;
2333 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2334
2838cfdd 2335 bus-range = <0x0 0xff>;
ec142c44 2336
2838cfdd
TR		 2337 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2338 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2339 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2340
2838cfdd
TR		 2341 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
2342 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
2343 interconnect-names = "dma-mem", "write";
2344 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2345 iommu-map-mask = <0x0>;
2346 dma-coherent;
ec142c44 2347
2838cfdd
TR		 2348 status = "disabled";
2349 };
ec142c44 2350
2838cfdd
TR		 2351 pcie@14140000 {
2352 compatible = "nvidia,tegra234-pcie";
2353 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2354 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2355 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2356 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2357 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
2358 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2359 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2360
2838cfdd
TR		 2361 #address-cells = <3>;
2362 #size-cells = <2>;
2363 device_type = "pci";
2364 num-lanes = <1>;
2365 num-viewport = <8>;
2366 linux,pci-domain = <3>;
ec142c44 2367
2838cfdd
TR		 2368 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2369 clock-names = "core";
ec142c44 2370
2838cfdd
TR		 2371 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2372 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2373 reset-names = "apb", "core";
ec142c44 2374
2838cfdd
TR		 2375 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2376 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2377 interrupt-names = "intr", "msi";
ec142c44 2378
2838cfdd
TR		 2379 #interrupt-cells = <1>;
2380 interrupt-map-mask = <0 0 0 0>;
2381 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2382
2838cfdd 2383 nvidia,bpmp = <&bpmp 3>;
ec142c44 2384
2838cfdd
TR		 2385 nvidia,aspm-cmrt-us = <60>;
2386 nvidia,aspm-pwr-on-t-us = <20>;
2387 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2388
2838cfdd 2389 bus-range = <0x0 0xff>;
ec142c44 2390
2838cfdd
TR		 2391 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2392 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2393 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2394
2838cfdd
TR		 2395 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
2396 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
2397 interconnect-names = "dma-mem", "write";
2398 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2399 iommu-map-mask = <0x0>;
2400 dma-coherent;
ec142c44 2401
2838cfdd
TR		 2402 status = "disabled";
2403 };
ec142c44 2404
2838cfdd
TR		 2405 pcie@14160000 {
2406 compatible = "nvidia,tegra234-pcie";
2407 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2408 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2409 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2410 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2411 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2412 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2413 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2414
2838cfdd
TR		 2415 #address-cells = <3>;
2416 #size-cells = <2>;
2417 device_type = "pci";
2418 num-lanes = <4>;
2419 num-viewport = <8>;
2420 linux,pci-domain = <4>;
ec142c44 2421
2838cfdd
TR		 2422 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2423 clock-names = "core";
ec142c44 2424
2838cfdd
TR		 2425 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2426 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2427 reset-names = "apb", "core";
ec142c44 2428
2838cfdd
TR		 2429 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2430 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2431 interrupt-names = "intr", "msi";
ec142c44 2432
2838cfdd
TR		 2433 #interrupt-cells = <1>;
2434 interrupt-map-mask = <0 0 0 0>;
2435 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2436
2838cfdd 2437 nvidia,bpmp = <&bpmp 4>;
ec142c44 2438
2838cfdd
TR		 2439 nvidia,aspm-cmrt-us = <60>;
2440 nvidia,aspm-pwr-on-t-us = <20>;
2441 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2442
2838cfdd 2443 bus-range = <0x0 0xff>;
ec142c44 2444
2838cfdd
TR		 2445 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2446 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2447 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2448
2838cfdd
TR		 2449 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
2450 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
2451 interconnect-names = "dma-mem", "write";
2452 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2453 iommu-map-mask = <0x0>;
2454 dma-coherent;
2455
2456 status = "disabled";
2457 };
ec142c44 2458
2838cfdd
TR		 2459 pcie@14180000 {
2460 compatible = "nvidia,tegra234-pcie";
2461 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2462 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2463 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2464 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2465 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2466 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2467 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2468
2838cfdd
TR		 2469 #address-cells = <3>;
2470 #size-cells = <2>;
2471 device_type = "pci";
2472 num-lanes = <4>;
2473 num-viewport = <8>;
2474 linux,pci-domain = <0>;
ec142c44 2475
2838cfdd
TR		 2476 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2477 clock-names = "core";
ec142c44 2478
2838cfdd
TR		 2479 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2480 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2481 reset-names = "apb", "core";
ec142c44 2482
2838cfdd
TR		 2483 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2484 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2485 interrupt-names = "intr", "msi";
ec142c44 2486
2838cfdd
TR		 2487 #interrupt-cells = <1>;
2488 interrupt-map-mask = <0 0 0 0>;
2489 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2490
2838cfdd 2491 nvidia,bpmp = <&bpmp 0>;
ec142c44 2492
2838cfdd
TR		 2493 nvidia,aspm-cmrt-us = <60>;
2494 nvidia,aspm-pwr-on-t-us = <20>;
2495 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2496
2838cfdd 2497 bus-range = <0x0 0xff>;
ec142c44 2498
2838cfdd
TR		 2499 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2500 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2501 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2502
2838cfdd
TR		 2503 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
2504 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
2505 interconnect-names = "dma-mem", "write";
2506 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2507 iommu-map-mask = <0x0>;
2508 dma-coherent;
2509
2510 status = "disabled";
2511 };
ec142c44 2512
2838cfdd
TR		 2513 pcie@141a0000 {
2514 compatible = "nvidia,tegra234-pcie";
2515 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2516 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2517 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2518 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2519 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2520 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2521 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2522
2838cfdd
TR		 2523 #address-cells = <3>;
2524 #size-cells = <2>;
2525 device_type = "pci";
2526 num-lanes = <8>;
2527 num-viewport = <8>;
2528 linux,pci-domain = <5>;
ec142c44 2529
2838cfdd
TR		 2530 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2531 clock-names = "core";
ec142c44 2532
2838cfdd
TR		 2533 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2534 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2535 reset-names = "apb", "core";
ec142c44 2536
2838cfdd
TR		 2537 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2538 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2539 interrupt-names = "intr", "msi";
ec142c44 2540
2838cfdd
TR		 2541 #interrupt-cells = <1>;
2542 interrupt-map-mask = <0 0 0 0>;
2543 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2544
2838cfdd 2545 nvidia,bpmp = <&bpmp 5>;
ec142c44 2546
2838cfdd
TR		 2547 nvidia,aspm-cmrt-us = <60>;
2548 nvidia,aspm-pwr-on-t-us = <20>;
2549 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2550
2838cfdd 2551 bus-range = <0x0 0xff>;
ec142c44 2552
2838cfdd
TR		 2553 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
2554 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2555 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2556
2838cfdd
TR		 2557 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2558 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2559 interconnect-names = "dma-mem", "write";
2560 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2561 iommu-map-mask = <0x0>;
2562 dma-coherent;
2563
2564 status = "disabled";
2565 };
ec142c44 2566
2838cfdd
TR		 2567 pcie-ep@141a0000 {
2568 compatible = "nvidia,tegra234-pcie-ep";
2569 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2570 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2571 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2572 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2573 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2574 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2575
2838cfdd 2576 num-lanes = <8>;
ec142c44 2577
2838cfdd
TR		 2578 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2579 clock-names = "core";
ec142c44 2580
2838cfdd
TR		 2581 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2582 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2583 reset-names = "apb", "core";
ec142c44 2584
2838cfdd
TR		 2585 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2586 interrupt-names = "intr";
ec142c44 2587
2838cfdd 2588 nvidia,bpmp = <&bpmp 5>;
ec142c44 2589
2838cfdd
TR		 2590 nvidia,enable-ext-refclk;
2591 nvidia,aspm-cmrt-us = <60>;
2592 nvidia,aspm-pwr-on-t-us = <20>;
2593 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2594
2838cfdd
TR		 2595 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2596 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2597 interconnect-names = "dma-mem", "write";
2598 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2599 iommu-map-mask = <0x0>;
2600 dma-coherent;
ec142c44 2601
2838cfdd
TR		 2602 status = "disabled";
2603 };
ec142c44 2604
2838cfdd
TR		 2605 pcie@141c0000 {
2606 compatible = "nvidia,tegra234-pcie";
2607 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2608 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2609 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2610 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2611 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2612 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2613 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2614
2838cfdd
TR		 2615 #address-cells = <3>;
2616 #size-cells = <2>;
2617 device_type = "pci";
2618 num-lanes = <4>;
2619 num-viewport = <8>;
2620 linux,pci-domain = <6>;
ec142c44 2621
2838cfdd
TR		 2622 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2623 clock-names = "core";
ec142c44 2624
2838cfdd
TR		 2625 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2626 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2627 reset-names = "apb", "core";
ec142c44 2628
2838cfdd
TR		 2629 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2630 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2631 interrupt-names = "intr", "msi";
ec142c44 2632
2838cfdd
TR		 2633 #interrupt-cells = <1>;
2634 interrupt-map-mask = <0 0 0 0>;
2635 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2636
2838cfdd 2637 nvidia,bpmp = <&bpmp 6>;
ec142c44 2638
2838cfdd
TR		 2639 nvidia,aspm-cmrt-us = <60>;
2640 nvidia,aspm-pwr-on-t-us = <20>;
2641 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2642
2838cfdd 2643 bus-range = <0x0 0xff>;
ec142c44 2644
2838cfdd
TR		 2645 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2646 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2647 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2648
2838cfdd
TR		 2649 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2650 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2651 interconnect-names = "dma-mem", "write";
2652 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2653 iommu-map-mask = <0x0>;
2654 dma-coherent;
2655
2656 status = "disabled";
2657 };
ec142c44 2658
2838cfdd
TR		 2659 pcie-ep@141c0000 {
2660 compatible = "nvidia,tegra234-pcie-ep";
2661 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2662 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2663 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2664 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
2665 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2666 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2667
2838cfdd 2668 num-lanes = <4>;
ec142c44 2669
2838cfdd
TR		 2670 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2671 clock-names = "core";
ec142c44 2672
2838cfdd
TR		 2673 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2674 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2675 reset-names = "apb", "core";
ec142c44 2676
2838cfdd
TR		 2677 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2678 interrupt-names = "intr";
ec142c44 2679
2838cfdd 2680 nvidia,bpmp = <&bpmp 6>;
ec142c44 2681
2838cfdd
TR		 2682 nvidia,enable-ext-refclk;
2683 nvidia,aspm-cmrt-us = <60>;
2684 nvidia,aspm-pwr-on-t-us = <20>;
2685 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2686
2838cfdd
TR		 2687 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2688 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2689 interconnect-names = "dma-mem", "write";
2690 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2691 iommu-map-mask = <0x0>;
2692 dma-coherent;
ec142c44 2693
2838cfdd
TR		 2694 status = "disabled";
2695 };
ec142c44 2696
2838cfdd
TR		 2697 pcie@141e0000 {
2698 compatible = "nvidia,tegra234-pcie";
2699 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2700 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2701 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2702 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2703 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2704 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2705 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2706
2838cfdd
TR		 2707 #address-cells = <3>;
2708 #size-cells = <2>;
2709 device_type = "pci";
2710 num-lanes = <8>;
2711 num-viewport = <8>;
2712 linux,pci-domain = <7>;
ec142c44 2713
2838cfdd
TR		 2714 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2715 clock-names = "core";
ec142c44 2716
2838cfdd
TR		 2717 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2718 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2719 reset-names = "apb", "core";
ec142c44 2720
2838cfdd
TR		 2721 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2722 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2723 interrupt-names = "intr", "msi";
ec142c44 2724
2838cfdd
TR		 2725 #interrupt-cells = <1>;
2726 interrupt-map-mask = <0 0 0 0>;
2727 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2728
2838cfdd 2729 nvidia,bpmp = <&bpmp 7>;
ec142c44 2730
2838cfdd
TR		 2731 nvidia,aspm-cmrt-us = <60>;
2732 nvidia,aspm-pwr-on-t-us = <20>;
2733 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2734
2838cfdd 2735 bus-range = <0x0 0xff>;
ec142c44 2736
2838cfdd
TR		 2737 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
2738 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2739 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2740
2838cfdd
TR		 2741 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2742 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2743 interconnect-names = "dma-mem", "write";
2744 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2745 iommu-map-mask = <0x0>;
2746 dma-coherent;
2747
2748 status = "disabled";
2749 };
2750
2751 pcie-ep@141e0000 {
2752 compatible = "nvidia,tegra234-pcie-ep";
2753 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2754 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2755 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2756 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
2757 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2758 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2759
2760 num-lanes = <8>;
2761
2762 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2763 clock-names = "core";
ec142c44 2764
2838cfdd
TR		 2765 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2766 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2767 reset-names = "apb", "core";
ec142c44 2768
2838cfdd
TR		 2769 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2770 interrupt-names = "intr";
ec142c44 2771
2838cfdd 2772 nvidia,bpmp = <&bpmp 7>;
ec142c44 2773
2838cfdd
TR		 2774 nvidia,enable-ext-refclk;
2775 nvidia,aspm-cmrt-us = <60>;
2776 nvidia,aspm-pwr-on-t-us = <20>;
2777 nvidia,aspm-l0s-entrance-latency-us = <3>;
2778
2779 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2780 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2781 interconnect-names = "dma-mem", "write";
2782 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2783 iommu-map-mask = <0x0>;
2784 dma-coherent;
2785
2786 status = "disabled";
2787 };
ec142c44
VS		 2788 };
2789
7fa30752 2790 sram@40000000 {
63944891 2791 compatible = "nvidia,tegra234-sysram", "mmio-sram";
98094be1 2792 reg = <0x0 0x40000000 0x0 0x80000>;
2838cfdd 2793
63944891
TR		 2794 #address-cells = <1>;
2795 #size-cells = <1>;
98094be1 2796 ranges = <0x0 0x0 0x40000000 0x80000>;
2838cfdd 2797
61192a9d 2798 no-memory-wc;
63944891 2799
98094be1
MP		 2800 cpu_bpmp_tx: sram@70000 {
2801 reg = <0x70000 0x1000>;
63944891
TR		 2802 label = "cpu-bpmp-tx";
2803 pool;
2804 };
2805
98094be1
MP		 2806 cpu_bpmp_rx: sram@71000 {
2807 reg = <0x71000 0x1000>;
63944891
TR		 2808 label = "cpu-bpmp-rx";
2809 pool;
2810 };
2811 };
2812
2813 bpmp: bpmp {
2814 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
2815 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
2816 TEGRA_HSP_DB_MASTER_BPMP>;
7fa30752 2817 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
63944891
TR		 2818 #clock-cells = <1>;
2819 #reset-cells = <1>;
2820 #power-domain-cells = <1>;
6de481e5
TR		 2821 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
2822 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
2823 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
2824 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
2825 interconnect-names = "read", "write", "dma-mem", "dma-write";
5710e16a 2826 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
63944891
TR		 2827
2828 bpmp_i2c: i2c {
2829 compatible = "nvidia,tegra186-bpmp-i2c";
2830 nvidia,bpmp-bus-id = <5>;
2831 #address-cells = <1>;
2832 #size-cells = <0>;
2833 };
2834 };
2835
2836 cpus {
2837 #address-cells = <1>;
2838 #size-cells = <0>;
2839
a12cf5c3
TR		 2840 cpu0_0: cpu@0 {
2841 compatible = "arm,cortex-a78";
63944891 2842 device_type = "cpu";
a12cf5c3 2843 reg = <0x00000>;
63944891
TR		 2844
2845 enable-method = "psci";
a12cf5c3
TR		 2846
2847 i-cache-size = <65536>;
2848 i-cache-line-size = <64>;
2849 i-cache-sets = <256>;
2850 d-cache-size = <65536>;
2851 d-cache-line-size = <64>;
2852 d-cache-sets = <256>;
2853 next-level-cache = <&l2c0_0>;
2854 };
2855
2856 cpu0_1: cpu@100 {
2857 compatible = "arm,cortex-a78";
2858 device_type = "cpu";
2859 reg = <0x00100>;
2860
2861 enable-method = "psci";
2862
2863 i-cache-size = <65536>;
2864 i-cache-line-size = <64>;
2865 i-cache-sets = <256>;
2866 d-cache-size = <65536>;
2867 d-cache-line-size = <64>;
2868 d-cache-sets = <256>;
2869 next-level-cache = <&l2c0_1>;
63944891 2870 };
a12cf5c3
TR		 2871
2872 cpu0_2: cpu@200 {
2873 compatible = "arm,cortex-a78";
2874 device_type = "cpu";
2875 reg = <0x00200>;
2876
2877 enable-method = "psci";
2878
2879 i-cache-size = <65536>;
2880 i-cache-line-size = <64>;
2881 i-cache-sets = <256>;
2882 d-cache-size = <65536>;
2883 d-cache-line-size = <64>;
2884 d-cache-sets = <256>;
2885 next-level-cache = <&l2c0_2>;
2886 };
2887
2888 cpu0_3: cpu@300 {
2889 compatible = "arm,cortex-a78";
2890 device_type = "cpu";
2891 reg = <0x00300>;
2892
2893 enable-method = "psci";
2894
2895 i-cache-size = <65536>;
2896 i-cache-line-size = <64>;
2897 i-cache-sets = <256>;
2898 d-cache-size = <65536>;
2899 d-cache-line-size = <64>;
2900 d-cache-sets = <256>;
2901 next-level-cache = <&l2c0_3>;
2902 };
2903
2904 cpu1_0: cpu@10000 {
2905 compatible = "arm,cortex-a78";
2906 device_type = "cpu";
2907 reg = <0x10000>;
2908
2909 enable-method = "psci";
2910
2911 i-cache-size = <65536>;
2912 i-cache-line-size = <64>;
2913 i-cache-sets = <256>;
2914 d-cache-size = <65536>;
2915 d-cache-line-size = <64>;
2916 d-cache-sets = <256>;
2917 next-level-cache = <&l2c1_0>;
2918 };
2919
2920 cpu1_1: cpu@10100 {
2921 compatible = "arm,cortex-a78";
2922 device_type = "cpu";
2923 reg = <0x10100>;
2924
2925 enable-method = "psci";
2926
2927 i-cache-size = <65536>;
2928 i-cache-line-size = <64>;
2929 i-cache-sets = <256>;
2930 d-cache-size = <65536>;
2931 d-cache-line-size = <64>;
2932 d-cache-sets = <256>;
2933 next-level-cache = <&l2c1_1>;
2934 };
2935
2936 cpu1_2: cpu@10200 {
2937 compatible = "arm,cortex-a78";
2938 device_type = "cpu";
2939 reg = <0x10200>;
2940
2941 enable-method = "psci";
2942
2943 i-cache-size = <65536>;
2944 i-cache-line-size = <64>;
2945 i-cache-sets = <256>;
2946 d-cache-size = <65536>;
2947 d-cache-line-size = <64>;
2948 d-cache-sets = <256>;
2949 next-level-cache = <&l2c1_2>;
2950 };
2951
2952 cpu1_3: cpu@10300 {
2953 compatible = "arm,cortex-a78";
2954 device_type = "cpu";
2955 reg = <0x10300>;
2956
2957 enable-method = "psci";
2958
2959 i-cache-size = <65536>;
2960 i-cache-line-size = <64>;
2961 i-cache-sets = <256>;
2962 d-cache-size = <65536>;
2963 d-cache-line-size = <64>;
2964 d-cache-sets = <256>;
2965 next-level-cache = <&l2c1_3>;
2966 };
2967
2968 cpu2_0: cpu@20000 {
2969 compatible = "arm,cortex-a78";
2970 device_type = "cpu";
2971 reg = <0x20000>;
2972
2973 enable-method = "psci";
2974
2975 i-cache-size = <65536>;
2976 i-cache-line-size = <64>;
2977 i-cache-sets = <256>;
2978 d-cache-size = <65536>;
2979 d-cache-line-size = <64>;
2980 d-cache-sets = <256>;
2981 next-level-cache = <&l2c2_0>;
2982 };
2983
2984 cpu2_1: cpu@20100 {
2985 compatible = "arm,cortex-a78";
2986 device_type = "cpu";
2987 reg = <0x20100>;
2988
2989 enable-method = "psci";
2990
2991 i-cache-size = <65536>;
2992 i-cache-line-size = <64>;
2993 i-cache-sets = <256>;
2994 d-cache-size = <65536>;
2995 d-cache-line-size = <64>;
2996 d-cache-sets = <256>;
2997 next-level-cache = <&l2c2_1>;
2998 };
2999
3000 cpu2_2: cpu@20200 {
3001 compatible = "arm,cortex-a78";
3002 device_type = "cpu";
3003 reg = <0x20200>;
3004
3005 enable-method = "psci";
3006
3007 i-cache-size = <65536>;
3008 i-cache-line-size = <64>;
3009 i-cache-sets = <256>;
3010 d-cache-size = <65536>;
3011 d-cache-line-size = <64>;
3012 d-cache-sets = <256>;
3013 next-level-cache = <&l2c2_2>;
3014 };
3015
3016 cpu2_3: cpu@20300 {
3017 compatible = "arm,cortex-a78";
3018 device_type = "cpu";
3019 reg = <0x20300>;
3020
3021 enable-method = "psci";
3022
3023 i-cache-size = <65536>;
3024 i-cache-line-size = <64>;
3025 i-cache-sets = <256>;
3026 d-cache-size = <65536>;
3027 d-cache-line-size = <64>;
3028 d-cache-sets = <256>;
3029 next-level-cache = <&l2c2_3>;
3030 };
3031
3032 cpu-map {
3033 cluster0 {
3034 core0 {
3035 cpu = <&cpu0_0>;
3036 };
3037
3038 core1 {
3039 cpu = <&cpu0_1>;
3040 };
3041
3042 core2 {
3043 cpu = <&cpu0_2>;
3044 };
3045
3046 core3 {
3047 cpu = <&cpu0_3>;
3048 };
3049 };
3050
3051 cluster1 {
3052 core0 {
3053 cpu = <&cpu1_0>;
3054 };
3055
3056 core1 {
3057 cpu = <&cpu1_1>;
3058 };
3059
3060 core2 {
3061 cpu = <&cpu1_2>;
3062 };
3063
3064 core3 {
3065 cpu = <&cpu1_3>;
3066 };
3067 };
3068
3069 cluster2 {
3070 core0 {
3071 cpu = <&cpu2_0>;
3072 };
3073
3074 core1 {
3075 cpu = <&cpu2_1>;
3076 };
3077
3078 core2 {
3079 cpu = <&cpu2_2>;
3080 };
3081
3082 core3 {
3083 cpu = <&cpu2_3>;
3084 };
3085 };
3086 };
3087
3088 l2c0_0: l2-cache00 {
27f1568b 3089 compatible = "cache";
a12cf5c3
TR		 3090 cache-size = <262144>;
3091 cache-line-size = <64>;
3092 cache-sets = <512>;
3093 cache-unified;
27f1568b 3094 cache-level = <2>;
a12cf5c3
TR		 3095 next-level-cache = <&l3c0>;
3096 };
3097
3098 l2c0_1: l2-cache01 {
27f1568b 3099 compatible = "cache";
a12cf5c3
TR		 3100 cache-size = <262144>;
3101 cache-line-size = <64>;
3102 cache-sets = <512>;
3103 cache-unified;
27f1568b 3104 cache-level = <2>;
a12cf5c3
TR		 3105 next-level-cache = <&l3c0>;
3106 };
3107
3108 l2c0_2: l2-cache02 {
27f1568b 3109 compatible = "cache";
a12cf5c3
TR		 3110 cache-size = <262144>;
3111 cache-line-size = <64>;
3112 cache-sets = <512>;
3113 cache-unified;
27f1568b 3114 cache-level = <2>;
a12cf5c3
TR		 3115 next-level-cache = <&l3c0>;
3116 };
3117
3118 l2c0_3: l2-cache03 {
27f1568b 3119 compatible = "cache";
a12cf5c3
TR		 3120 cache-size = <262144>;
3121 cache-line-size = <64>;
3122 cache-sets = <512>;
3123 cache-unified;
27f1568b 3124 cache-level = <2>;
a12cf5c3
TR		 3125 next-level-cache = <&l3c0>;
3126 };
3127
3128 l2c1_0: l2-cache10 {
27f1568b 3129 compatible = "cache";
a12cf5c3
TR		 3130 cache-size = <262144>;
3131 cache-line-size = <64>;
3132 cache-sets = <512>;
3133 cache-unified;
27f1568b 3134 cache-level = <2>;
a12cf5c3
TR		 3135 next-level-cache = <&l3c1>;
3136 };
3137
3138 l2c1_1: l2-cache11 {
27f1568b 3139 compatible = "cache";
a12cf5c3
TR		 3140 cache-size = <262144>;
3141 cache-line-size = <64>;
3142 cache-sets = <512>;
3143 cache-unified;
27f1568b 3144 cache-level = <2>;
a12cf5c3
TR		 3145 next-level-cache = <&l3c1>;
3146 };
3147
3148 l2c1_2: l2-cache12 {
27f1568b 3149 compatible = "cache";
a12cf5c3
TR		 3150 cache-size = <262144>;
3151 cache-line-size = <64>;
3152 cache-sets = <512>;
3153 cache-unified;
27f1568b 3154 cache-level = <2>;
a12cf5c3
TR		 3155 next-level-cache = <&l3c1>;
3156 };
3157
3158 l2c1_3: l2-cache13 {
27f1568b 3159 compatible = "cache";
a12cf5c3
TR		 3160 cache-size = <262144>;
3161 cache-line-size = <64>;
3162 cache-sets = <512>;
3163 cache-unified;
27f1568b 3164 cache-level = <2>;
a12cf5c3
TR		 3165 next-level-cache = <&l3c1>;
3166 };
3167
3168 l2c2_0: l2-cache20 {
27f1568b 3169 compatible = "cache";
a12cf5c3
TR		 3170 cache-size = <262144>;
3171 cache-line-size = <64>;
3172 cache-sets = <512>;
3173 cache-unified;
27f1568b 3174 cache-level = <2>;
a12cf5c3
TR		 3175 next-level-cache = <&l3c2>;
3176 };
3177
3178 l2c2_1: l2-cache21 {
27f1568b 3179 compatible = "cache";
a12cf5c3
TR		 3180 cache-size = <262144>;
3181 cache-line-size = <64>;
3182 cache-sets = <512>;
3183 cache-unified;
27f1568b 3184 cache-level = <2>;
a12cf5c3
TR		 3185 next-level-cache = <&l3c2>;
3186 };
3187
3188 l2c2_2: l2-cache22 {
27f1568b 3189 compatible = "cache";
a12cf5c3
TR		 3190 cache-size = <262144>;
3191 cache-line-size = <64>;
3192 cache-sets = <512>;
3193 cache-unified;
27f1568b 3194 cache-level = <2>;
a12cf5c3
TR		 3195 next-level-cache = <&l3c2>;
3196 };
3197
3198 l2c2_3: l2-cache23 {
27f1568b 3199 compatible = "cache";
a12cf5c3
TR		 3200 cache-size = <262144>;
3201 cache-line-size = <64>;
3202 cache-sets = <512>;
3203 cache-unified;
27f1568b 3204 cache-level = <2>;
a12cf5c3
TR		 3205 next-level-cache = <&l3c2>;
3206 };
3207
3208 l3c0: l3-cache0 {
27f1568b
PG		 3209 compatible = "cache";
3210 cache-unified;
a12cf5c3
TR		 3211 cache-size = <2097152>;
3212 cache-line-size = <64>;
3213 cache-sets = <2048>;
27f1568b 3214 cache-level = <3>;
a12cf5c3
TR		 3215 };
3216
3217 l3c1: l3-cache1 {
27f1568b
PG		 3218 compatible = "cache";
3219 cache-unified;
a12cf5c3
TR		 3220 cache-size = <2097152>;
3221 cache-line-size = <64>;
3222 cache-sets = <2048>;
27f1568b 3223 cache-level = <3>;
a12cf5c3
TR		 3224 };
3225
3226 l3c2: l3-cache2 {
27f1568b
PG		 3227 compatible = "cache";
3228 cache-unified;
a12cf5c3
TR		 3229 cache-size = <2097152>;
3230 cache-line-size = <64>;
3231 cache-sets = <2048>;
27f1568b 3232 cache-level = <3>;
a12cf5c3
TR		 3233 };
3234 };
3235
3236 pmu {
3237 compatible = "arm,cortex-a78-pmu";
3238 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
3239 status = "okay";
63944891
TR		 3240 };
3241
3242 psci {
3243 compatible = "arm,psci-1.0";
3244 status = "okay";
3245 method = "smc";
3246 };
3247
06ad2ec4
MP		 3248 tcu: serial {
3249 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3250 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3251 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3252 mbox-names = "rx", "tx";
3253 status = "disabled";
3254 };
3255
09614acd
SP		 3256 sound {
3257 status = "disabled";
3258
3259 clocks = <&bpmp TEGRA234_CLK_PLLA>,
3260 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3261 clock-names = "pll_a", "plla_out0";
3262 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3263 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3264 <&bpmp TEGRA234_CLK_AUD_MCLK>;
3265 assigned-clock-parents = <0>,
3266 <&bpmp TEGRA234_CLK_PLLA>,
3267 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3268 };
3269
63944891
TR		 3270 timer {
3271 compatible = "arm,armv8-timer";
3272 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3273 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3274 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3275 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3276 interrupt-parent = <&gic>;
3277 always-on;
3278 };
3279};
A mirror of Linus' kernel repository