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arm64: tegra: Enable UARTA and UARTE for Orin Nano
[thirdparty/linux.git] / arch / arm64 / boot / dts / nvidia / tegra234.dtsi
CommitLineData
63944891
TR		 1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/clock/tegra234-clock.h>
699349e0 4#include <dt-bindings/gpio/tegra234-gpio.h>
63944891
TR		 5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/mailbox/tegra186-hsp.h>
eed280df 7#include <dt-bindings/memory/tegra234-mc.h>
c71e1897 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
dc94a94d 9#include <dt-bindings/power/tegra234-powergate.h>
63944891 10#include <dt-bindings/reset/tegra234-reset.h>
09d99078 11#include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
63944891
TR		 12
13/ {
14 compatible = "nvidia,tegra234";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 bus@0 {
20 compatible = "simple-bus";
63944891 21
2838cfdd
TR		 22 #address-cells = <2>;
23 #size-cells = <2>;
4bb54c2c 24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
63944891 25
79ed18d9
TR		 26 misc@100000 {
27 compatible = "nvidia,tegra234-misc";
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
30 status = "okay";
31 };
32
33 timer@2080000 {
34 compatible = "nvidia,tegra234-timer";
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
52 status = "okay";
53 };
54
55 gpio: gpio@2200000 {
56 compatible = "nvidia,tegra234-gpio";
57 reg-names = "security", "gpio";
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
60 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 #gpio-cells = <2>;
111 gpio-controller;
282fde00
PS		 112 gpio-ranges = <&pinmux 0 0 164>;
113 };
114
115 pinmux: pinmux@2430000 {
116 compatible = "nvidia,tegra234-pinmux";
117 reg = <0x0 0x2430000 0x0 0x19100>;
79ed18d9
TR		 118 };
119
60d2016a 120 gpcdma: dma-controller@2600000 {
f7b93a08 121 compatible = "nvidia,tegra234-gpcdma",
f7b93a08 122 "nvidia,tegra186-gpcdma";
2838cfdd 123 reg = <0x0 0x2600000 0x0 0x210000>;
60d2016a
A		 124 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
125 reset-names = "gpcdma";
dd0be827
A		 126 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
60d2016a
A		 128 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
158 #dma-cells = <1>;
159 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dd0be827 160 dma-channel-mask = <0xfffffffe>;
60d2016a
A		 161 dma-coherent;
162 };
163
dc94a94d
SP		 164 aconnect@2900000 {
165 compatible = "nvidia,tegra234-aconnect",
166 "nvidia,tegra210-aconnect";
167 clocks = <&bpmp TEGRA234_CLK_APE>,
168 <&bpmp TEGRA234_CLK_APB2APE>;
169 clock-names = "ape", "apb2ape";
170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
dc94a94d
SP		 171 status = "disabled";
172
2838cfdd
TR		 173 #address-cells = <2>;
174 #size-cells = <2>;
175 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
176
dc94a94d
SP		 177 tegra_ahub: ahub@2900800 {
178 compatible = "nvidia,tegra234-ahub";
2838cfdd 179 reg = <0x0 0x02900800 0x0 0x800>;
dc94a94d
SP		 180 clocks = <&bpmp TEGRA234_CLK_AHUB>;
181 clock-names = "ahub";
182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
e483fe34
S		 183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
184 assigned-clock-rates = <81600000>;
dc94a94d
SP		 185 status = "disabled";
186
2838cfdd
TR		 187 #address-cells = <2>;
188 #size-cells = <2>;
189 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
190
dc94a94d
SP		 191 tegra_i2s1: i2s@2901000 {
192 compatible = "nvidia,tegra234-i2s",
193 "nvidia,tegra210-i2s";
2838cfdd 194 reg = <0x0 0x2901000 0x0 0x100>;
dc94a94d
SP		 195 clocks = <&bpmp TEGRA234_CLK_I2S1>,
196 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
197 clock-names = "i2s", "sync_input";
198 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
200 assigned-clock-rates = <1536000>;
201 sound-name-prefix = "I2S1";
202 status = "disabled";
203 };
204
205 tegra_i2s2: i2s@2901100 {
206 compatible = "nvidia,tegra234-i2s",
207 "nvidia,tegra210-i2s";
2838cfdd 208 reg = <0x0 0x2901100 0x0 0x100>;
dc94a94d
SP		 209 clocks = <&bpmp TEGRA234_CLK_I2S2>,
210 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
211 clock-names = "i2s", "sync_input";
212 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
213 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
214 assigned-clock-rates = <1536000>;
215 sound-name-prefix = "I2S2";
216 status = "disabled";
217 };
218
219 tegra_i2s3: i2s@2901200 {
220 compatible = "nvidia,tegra234-i2s",
221 "nvidia,tegra210-i2s";
2838cfdd 222 reg = <0x0 0x2901200 0x0 0x100>;
dc94a94d
SP		 223 clocks = <&bpmp TEGRA234_CLK_I2S3>,
224 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
225 clock-names = "i2s", "sync_input";
226 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
227 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
228 assigned-clock-rates = <1536000>;
229 sound-name-prefix = "I2S3";
230 status = "disabled";
231 };
232
233 tegra_i2s4: i2s@2901300 {
234 compatible = "nvidia,tegra234-i2s",
235 "nvidia,tegra210-i2s";
2838cfdd 236 reg = <0x0 0x2901300 0x0 0x100>;
dc94a94d
SP		 237 clocks = <&bpmp TEGRA234_CLK_I2S4>,
238 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
239 clock-names = "i2s", "sync_input";
240 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
241 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
242 assigned-clock-rates = <1536000>;
243 sound-name-prefix = "I2S4";
244 status = "disabled";
245 };
246
247 tegra_i2s5: i2s@2901400 {
248 compatible = "nvidia,tegra234-i2s",
249 "nvidia,tegra210-i2s";
2838cfdd 250 reg = <0x0 0x2901400 0x0 0x100>;
dc94a94d
SP		 251 clocks = <&bpmp TEGRA234_CLK_I2S5>,
252 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
253 clock-names = "i2s", "sync_input";
254 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
255 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
256 assigned-clock-rates = <1536000>;
257 sound-name-prefix = "I2S5";
258 status = "disabled";
259 };
260
261 tegra_i2s6: i2s@2901500 {
262 compatible = "nvidia,tegra234-i2s",
263 "nvidia,tegra210-i2s";
2838cfdd 264 reg = <0x0 0x2901500 0x0 0x100>;
dc94a94d
SP		 265 clocks = <&bpmp TEGRA234_CLK_I2S6>,
266 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
267 clock-names = "i2s", "sync_input";
268 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
269 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
270 assigned-clock-rates = <1536000>;
271 sound-name-prefix = "I2S6";
272 status = "disabled";
273 };
274
275 tegra_sfc1: sfc@2902000 {
276 compatible = "nvidia,tegra234-sfc",
277 "nvidia,tegra210-sfc";
2838cfdd 278 reg = <0x0 0x2902000 0x0 0x200>;
dc94a94d
SP		 279 sound-name-prefix = "SFC1";
280 status = "disabled";
281 };
282
283 tegra_sfc2: sfc@2902200 {
284 compatible = "nvidia,tegra234-sfc",
285 "nvidia,tegra210-sfc";
2838cfdd 286 reg = <0x0 0x2902200 0x0 0x200>;
dc94a94d
SP		 287 sound-name-prefix = "SFC2";
288 status = "disabled";
289 };
290
291 tegra_sfc3: sfc@2902400 {
292 compatible = "nvidia,tegra234-sfc",
293 "nvidia,tegra210-sfc";
2838cfdd 294 reg = <0x0 0x2902400 0x0 0x200>;
dc94a94d
SP		 295 sound-name-prefix = "SFC3";
296 status = "disabled";
297 };
298
299 tegra_sfc4: sfc@2902600 {
300 compatible = "nvidia,tegra234-sfc",
301 "nvidia,tegra210-sfc";
2838cfdd 302 reg = <0x0 0x2902600 0x0 0x200>;
dc94a94d
SP		 303 sound-name-prefix = "SFC4";
304 status = "disabled";
305 };
306
307 tegra_amx1: amx@2903000 {
308 compatible = "nvidia,tegra234-amx",
309 "nvidia,tegra194-amx";
2838cfdd 310 reg = <0x0 0x2903000 0x0 0x100>;
dc94a94d
SP		 311 sound-name-prefix = "AMX1";
312 status = "disabled";
313 };
314
315 tegra_amx2: amx@2903100 {
316 compatible = "nvidia,tegra234-amx",
317 "nvidia,tegra194-amx";
2838cfdd 318 reg = <0x0 0x2903100 0x0 0x100>;
dc94a94d
SP		 319 sound-name-prefix = "AMX2";
320 status = "disabled";
321 };
322
323 tegra_amx3: amx@2903200 {
324 compatible = "nvidia,tegra234-amx",
325 "nvidia,tegra194-amx";
2838cfdd 326 reg = <0x0 0x2903200 0x0 0x100>;
dc94a94d
SP		 327 sound-name-prefix = "AMX3";
328 status = "disabled";
329 };
330
331 tegra_amx4: amx@2903300 {
332 compatible = "nvidia,tegra234-amx",
333 "nvidia,tegra194-amx";
2838cfdd 334 reg = <0x0 0x2903300 0x0 0x100>;
dc94a94d
SP		 335 sound-name-prefix = "AMX4";
336 status = "disabled";
337 };
338
339 tegra_adx1: adx@2903800 {
340 compatible = "nvidia,tegra234-adx",
341 "nvidia,tegra210-adx";
2838cfdd 342 reg = <0x0 0x2903800 0x0 0x100>;
dc94a94d
SP		 343 sound-name-prefix = "ADX1";
344 status = "disabled";
345 };
346
347 tegra_adx2: adx@2903900 {
348 compatible = "nvidia,tegra234-adx",
349 "nvidia,tegra210-adx";
2838cfdd 350 reg = <0x0 0x2903900 0x0 0x100>;
dc94a94d
SP		 351 sound-name-prefix = "ADX2";
352 status = "disabled";
353 };
354
355 tegra_adx3: adx@2903a00 {
356 compatible = "nvidia,tegra234-adx",
357 "nvidia,tegra210-adx";
2838cfdd 358 reg = <0x0 0x2903a00 0x0 0x100>;
dc94a94d
SP		 359 sound-name-prefix = "ADX3";
360 status = "disabled";
361 };
362
363 tegra_adx4: adx@2903b00 {
364 compatible = "nvidia,tegra234-adx",
365 "nvidia,tegra210-adx";
2838cfdd 366 reg = <0x0 0x2903b00 0x0 0x100>;
dc94a94d
SP		 367 sound-name-prefix = "ADX4";
368 status = "disabled";
369 };
370
371
372 tegra_dmic1: dmic@2904000 {
373 compatible = "nvidia,tegra234-dmic",
374 "nvidia,tegra210-dmic";
2838cfdd 375 reg = <0x0 0x2904000 0x0 0x100>;
dc94a94d
SP		 376 clocks = <&bpmp TEGRA234_CLK_DMIC1>;
377 clock-names = "dmic";
378 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
380 assigned-clock-rates = <3072000>;
381 sound-name-prefix = "DMIC1";
382 status = "disabled";
383 };
384
385 tegra_dmic2: dmic@2904100 {
386 compatible = "nvidia,tegra234-dmic",
387 "nvidia,tegra210-dmic";
2838cfdd 388 reg = <0x0 0x2904100 0x0 0x100>;
dc94a94d
SP		 389 clocks = <&bpmp TEGRA234_CLK_DMIC2>;
390 clock-names = "dmic";
391 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
392 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
393 assigned-clock-rates = <3072000>;
394 sound-name-prefix = "DMIC2";
395 status = "disabled";
396 };
397
398 tegra_dmic3: dmic@2904200 {
399 compatible = "nvidia,tegra234-dmic",
400 "nvidia,tegra210-dmic";
2838cfdd 401 reg = <0x0 0x2904200 0x0 0x100>;
dc94a94d
SP		 402 clocks = <&bpmp TEGRA234_CLK_DMIC3>;
403 clock-names = "dmic";
404 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
405 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
406 assigned-clock-rates = <3072000>;
407 sound-name-prefix = "DMIC3";
408 status = "disabled";
409 };
410
411 tegra_dmic4: dmic@2904300 {
412 compatible = "nvidia,tegra234-dmic",
413 "nvidia,tegra210-dmic";
2838cfdd 414 reg = <0x0 0x2904300 0x0 0x100>;
dc94a94d
SP		 415 clocks = <&bpmp TEGRA234_CLK_DMIC4>;
416 clock-names = "dmic";
417 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
418 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
419 assigned-clock-rates = <3072000>;
420 sound-name-prefix = "DMIC4";
421 status = "disabled";
422 };
423
424 tegra_dspk1: dspk@2905000 {
425 compatible = "nvidia,tegra234-dspk",
426 "nvidia,tegra186-dspk";
2838cfdd 427 reg = <0x0 0x2905000 0x0 0x100>;
dc94a94d
SP		 428 clocks = <&bpmp TEGRA234_CLK_DSPK1>;
429 clock-names = "dspk";
430 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
431 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
432 assigned-clock-rates = <12288000>;
433 sound-name-prefix = "DSPK1";
434 status = "disabled";
435 };
436
437 tegra_dspk2: dspk@2905100 {
438 compatible = "nvidia,tegra234-dspk",
439 "nvidia,tegra186-dspk";
2838cfdd 440 reg = <0x0 0x2905100 0x0 0x100>;
dc94a94d
SP		 441 clocks = <&bpmp TEGRA234_CLK_DSPK2>;
442 clock-names = "dspk";
443 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
444 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
445 assigned-clock-rates = <12288000>;
446 sound-name-prefix = "DSPK2";
447 status = "disabled";
448 };
449
4b6a1b7c
SP		 450 tegra_ope1: processing-engine@2908000 {
451 compatible = "nvidia,tegra234-ope",
452 "nvidia,tegra210-ope";
2838cfdd 453 reg = <0x0 0x2908000 0x0 0x100>;
4b6a1b7c
SP		 454 sound-name-prefix = "OPE1";
455 status = "disabled";
456
2838cfdd
TR		 457 #address-cells = <2>;
458 #size-cells = <2>;
459 ranges;
460
4b6a1b7c
SP		 461 equalizer@2908100 {
462 compatible = "nvidia,tegra234-peq",
463 "nvidia,tegra210-peq";
2838cfdd 464 reg = <0x0 0x2908100 0x0 0x100>;
4b6a1b7c
SP		 465 };
466
467 dynamic-range-compressor@2908200 {
468 compatible = "nvidia,tegra234-mbdrc",
469 "nvidia,tegra210-mbdrc";
2838cfdd 470 reg = <0x0 0x2908200 0x0 0x200>;
4b6a1b7c
SP		 471 };
472 };
473
dc94a94d
SP		 474 tegra_mvc1: mvc@290a000 {
475 compatible = "nvidia,tegra234-mvc",
476 "nvidia,tegra210-mvc";
2838cfdd 477 reg = <0x0 0x290a000 0x0 0x200>;
dc94a94d
SP		 478 sound-name-prefix = "MVC1";
479 status = "disabled";
480 };
481
482 tegra_mvc2: mvc@290a200 {
483 compatible = "nvidia,tegra234-mvc",
484 "nvidia,tegra210-mvc";
2838cfdd 485 reg = <0x0 0x290a200 0x0 0x200>;
dc94a94d
SP		 486 sound-name-prefix = "MVC2";
487 status = "disabled";
488 };
489
490 tegra_amixer: amixer@290bb00 {
491 compatible = "nvidia,tegra234-amixer",
492 "nvidia,tegra210-amixer";
2838cfdd 493 reg = <0x0 0x290bb00 0x0 0x800>;
dc94a94d
SP		 494 sound-name-prefix = "MIXER1";
495 status = "disabled";
496 };
497
498 tegra_admaif: admaif@290f000 {
499 compatible = "nvidia,tegra234-admaif",
500 "nvidia,tegra186-admaif";
2838cfdd 501 reg = <0x0 0x0290f000 0x0 0x1000>;
dc94a94d
SP		 502 dmas = <&adma 1>, <&adma 1>,
503 <&adma 2>, <&adma 2>,
504 <&adma 3>, <&adma 3>,
505 <&adma 4>, <&adma 4>,
506 <&adma 5>, <&adma 5>,
507 <&adma 6>, <&adma 6>,
508 <&adma 7>, <&adma 7>,
509 <&adma 8>, <&adma 8>,
510 <&adma 9>, <&adma 9>,
511 <&adma 10>, <&adma 10>,
512 <&adma 11>, <&adma 11>,
513 <&adma 12>, <&adma 12>,
514 <&adma 13>, <&adma 13>,
515 <&adma 14>, <&adma 14>,
516 <&adma 15>, <&adma 15>,
517 <&adma 16>, <&adma 16>,
518 <&adma 17>, <&adma 17>,
519 <&adma 18>, <&adma 18>,
520 <&adma 19>, <&adma 19>,
521 <&adma 20>, <&adma 20>;
522 dma-names = "rx1", "tx1",
523 "rx2", "tx2",
524 "rx3", "tx3",
525 "rx4", "tx4",
526 "rx5", "tx5",
527 "rx6", "tx6",
528 "rx7", "tx7",
529 "rx8", "tx8",
530 "rx9", "tx9",
531 "rx10", "tx10",
532 "rx11", "tx11",
533 "rx12", "tx12",
534 "rx13", "tx13",
535 "rx14", "tx14",
536 "rx15", "tx15",
537 "rx16", "tx16",
538 "rx17", "tx17",
539 "rx18", "tx18",
540 "rx19", "tx19",
541 "rx20", "tx20";
542 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
543 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
544 interconnect-names = "dma-mem", "write";
545 iommus = <&smmu_niso0 TEGRA234_SID_APE>;
546 status = "disabled";
547 };
47a08153
SP		 548
549 tegra_asrc: asrc@2910000 {
550 compatible = "nvidia,tegra234-asrc",
551 "nvidia,tegra186-asrc";
2838cfdd 552 reg = <0x0 0x2910000 0x0 0x2000>;
47a08153
SP		 553 sound-name-prefix = "ASRC1";
554 status = "disabled";
555 };
dc94a94d
SP		 556 };
557
558 adma: dma-controller@2930000 {
559 compatible = "nvidia,tegra234-adma",
560 "nvidia,tegra186-adma";
2838cfdd 561 reg = <0x0 0x02930000 0x0 0x20000>;
dc94a94d
SP		 562 interrupt-parent = <&agic>;
563 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
595 #dma-cells = <1>;
596 clocks = <&bpmp TEGRA234_CLK_AHUB>;
597 clock-names = "d_audio";
598 status = "disabled";
599 };
600
601 agic: interrupt-controller@2a40000 {
602 compatible = "nvidia,tegra234-agic",
603 "nvidia,tegra210-agic";
604 #interrupt-cells = <3>;
605 interrupt-controller;
2838cfdd
TR		 606 reg = <0x0 0x02a41000 0x0 0x1000>,
607 <0x0 0x02a42000 0x0 0x2000>;
dc94a94d
SP		 608 interrupts = <GIC_SPI 145
609 (GIC_CPU_MASK_SIMPLE(4) |
610 IRQ_TYPE_LEVEL_HIGH)>;
611 clocks = <&bpmp TEGRA234_CLK_APE>;
612 clock-names = "clk";
613 status = "disabled";
614 };
615 };
616
eed280df
TR		 617 mc: memory-controller@2c00000 {
618 compatible = "nvidia,tegra234-mc";
2838cfdd
TR		 619 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
620 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
621 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
622 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
623 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
624 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
625 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
626 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
627 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
628 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
629 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
630 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
631 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
632 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
633 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
634 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
635 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
636 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
000b99e5
AM		 637 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
638 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
639 "ch11", "ch12", "ch13", "ch14", "ch15";
eed280df
TR		 640 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
641 #interconnect-cells = <1>;
642 status = "okay";
643
644 #address-cells = <2>;
645 #size-cells = <2>;
2838cfdd
TR		 646 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
647 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
648 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
eed280df
TR		 649
650 /*
651 * Bit 39 of addresses passing through the memory
652 * controller selects the XBAR format used when memory
653 * is accessed. This is used to transparently access
654 * memory in the XBAR format used by the discrete GPU
655 * (bit 39 set) or Tegra (bit 39 clear).
656 *
657 * As a consequence, the operating system must ensure
658 * that bit 39 is never used implicitly, for example
659 * via an I/O virtual address mapping of an IOMMU. If
660 * devices require access to the XBAR switch, their
661 * drivers must set this bit explicitly.
662 *
663 * Limit the DMA range for memory clients to [38:0].
664 */
2838cfdd 665 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
eed280df
TR		 666
667 emc: external-memory-controller@2c60000 {
668 compatible = "nvidia,tegra234-emc";
669 reg = <0x0 0x02c60000 0x0 0x90000>,
670 <0x0 0x01780000 0x0 0x80000>;
671 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&bpmp TEGRA234_CLK_EMC>;
673 clock-names = "emc";
674 status = "okay";
675
676 #interconnect-cells = <0>;
677
678 nvidia,bpmp = <&bpmp>;
679 };
680 };
681
63944891
TR		 682 uarta: serial@3100000 {
683 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2838cfdd 684 reg = <0x0 0x03100000 0x0 0x10000>;
63944891
TR		 685 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&bpmp TEGRA234_CLK_UARTA>;
63944891 687 resets = <&bpmp TEGRA234_RESET_UARTA>;
63944891
TR		 688 status = "disabled";
689 };
690
940acdac
GS		 691 uarte: serial@3140000 {
692 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
693 reg = <0x0 0x03140000 0x0 0x10000>;
694 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&bpmp TEGRA234_CLK_UARTE>;
696 resets = <&bpmp TEGRA234_RESET_UARTE>;
697 status = "disabled";
698 };
699
156af9de
A		 700 gen1_i2c: i2c@3160000 {
701 compatible = "nvidia,tegra194-i2c";
2838cfdd 702 reg = <0x0 0x3160000 0x0 0x100>;
156af9de
A		 703 status = "disabled";
704 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 705 #address-cells = <1>;
706 #size-cells = <0>;
156af9de
A		 707 clock-frequency = <400000>;
708 clocks = <&bpmp TEGRA234_CLK_I2C1
709 &bpmp TEGRA234_CLK_PLLP_OUT0>;
710 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
711 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
712 clock-names = "div-clk", "parent";
713 resets = <&bpmp TEGRA234_RESET_I2C1>;
714 reset-names = "i2c";
8e442805
A		 715 dmas = <&gpcdma 21>, <&gpcdma 21>;
716 dma-names = "rx", "tx";
156af9de
A		 717 };
718
719 cam_i2c: i2c@3180000 {
720 compatible = "nvidia,tegra194-i2c";
2838cfdd 721 reg = <0x0 0x3180000 0x0 0x100>;
156af9de 722 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 723 #address-cells = <1>;
724 #size-cells = <0>;
156af9de
A		 725 status = "disabled";
726 clock-frequency = <400000>;
727 clocks = <&bpmp TEGRA234_CLK_I2C3
728 &bpmp TEGRA234_CLK_PLLP_OUT0>;
729 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
730 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
731 clock-names = "div-clk", "parent";
732 resets = <&bpmp TEGRA234_RESET_I2C3>;
733 reset-names = "i2c";
8e442805
A		 734 dmas = <&gpcdma 23>, <&gpcdma 23>;
735 dma-names = "rx", "tx";
156af9de
A		 736 };
737
738 dp_aux_ch1_i2c: i2c@3190000 {
739 compatible = "nvidia,tegra194-i2c";
2838cfdd 740 reg = <0x0 0x3190000 0x0 0x100>;
156af9de 741 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 742 #address-cells = <1>;
743 #size-cells = <0>;
156af9de
A		 744 status = "disabled";
745 clock-frequency = <100000>;
746 clocks = <&bpmp TEGRA234_CLK_I2C4
747 &bpmp TEGRA234_CLK_PLLP_OUT0>;
748 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
749 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
750 clock-names = "div-clk", "parent";
751 resets = <&bpmp TEGRA234_RESET_I2C4>;
752 reset-names = "i2c";
8e442805
A		 753 dmas = <&gpcdma 26>, <&gpcdma 26>;
754 dma-names = "rx", "tx";
156af9de
A		 755 };
756
757 dp_aux_ch0_i2c: i2c@31b0000 {
758 compatible = "nvidia,tegra194-i2c";
2838cfdd 759 reg = <0x0 0x31b0000 0x0 0x100>;
156af9de 760 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 761 #address-cells = <1>;
762 #size-cells = <0>;
156af9de
A		 763 status = "disabled";
764 clock-frequency = <100000>;
765 clocks = <&bpmp TEGRA234_CLK_I2C6
766 &bpmp TEGRA234_CLK_PLLP_OUT0>;
767 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
768 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
769 clock-names = "div-clk", "parent";
770 resets = <&bpmp TEGRA234_RESET_I2C6>;
771 reset-names = "i2c";
8e442805
A		 772 dmas = <&gpcdma 30>, <&gpcdma 30>;
773 dma-names = "rx", "tx";
156af9de
A		 774 };
775
776 dp_aux_ch2_i2c: i2c@31c0000 {
777 compatible = "nvidia,tegra194-i2c";
2838cfdd 778 reg = <0x0 0x31c0000 0x0 0x100>;
156af9de 779 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 780 #address-cells = <1>;
781 #size-cells = <0>;
156af9de
A		 782 status = "disabled";
783 clock-frequency = <100000>;
784 clocks = <&bpmp TEGRA234_CLK_I2C7
785 &bpmp TEGRA234_CLK_PLLP_OUT0>;
786 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
787 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
788 clock-names = "div-clk", "parent";
789 resets = <&bpmp TEGRA234_RESET_I2C7>;
790 reset-names = "i2c";
8e442805
A		 791 dmas = <&gpcdma 27>, <&gpcdma 27>;
792 dma-names = "rx", "tx";
156af9de
A		 793 };
794
1bbba854
JH		 795 uarti: serial@31d0000 {
796 compatible = "arm,sbsa-uart";
2838cfdd 797 reg = <0x0 0x31d0000 0x0 0x10000>;
1bbba854
JH		 798 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
799 status = "disabled";
800 };
801
156af9de
A		 802 dp_aux_ch3_i2c: i2c@31e0000 {
803 compatible = "nvidia,tegra194-i2c";
2838cfdd 804 reg = <0x0 0x31e0000 0x0 0x100>;
156af9de 805 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 806 #address-cells = <1>;
807 #size-cells = <0>;
156af9de
A		 808 status = "disabled";
809 clock-frequency = <100000>;
810 clocks = <&bpmp TEGRA234_CLK_I2C9
811 &bpmp TEGRA234_CLK_PLLP_OUT0>;
812 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
813 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
814 clock-names = "div-clk", "parent";
815 resets = <&bpmp TEGRA234_RESET_I2C9>;
816 reset-names = "i2c";
8e442805
A		 817 dmas = <&gpcdma 31>, <&gpcdma 31>;
818 dma-names = "rx", "tx";
156af9de
A		 819 };
820
71f69ffa
AS		 821 spi@3270000 {
822 compatible = "nvidia,tegra234-qspi";
2838cfdd 823 reg = <0x0 0x3270000 0x0 0x1000>;
71f69ffa
AS		 824 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
825 #address-cells = <1>;
826 #size-cells = <0>;
827 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
828 <&bpmp TEGRA234_CLK_QSPI0_PM>;
829 clock-names = "qspi", "qspi_out";
830 resets = <&bpmp TEGRA234_RESET_QSPI0>;
71f69ffa
AS		 831 status = "disabled";
832 };
833
5e69088d 834 pwm1: pwm@3280000 {
2566d28c 835 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 836 reg = <0x0 0x3280000 0x0 0x10000>;
5e69088d 837 clocks = <&bpmp TEGRA234_CLK_PWM1>;
5e69088d
A		 838 resets = <&bpmp TEGRA234_RESET_PWM1>;
839 reset-names = "pwm";
840 status = "disabled";
841 #pwm-cells = <2>;
842 };
843
2566d28c
JH		 844 pwm2: pwm@3290000 {
845 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 846 reg = <0x0 0x3290000 0x0 0x10000>;
2566d28c 847 clocks = <&bpmp TEGRA234_CLK_PWM2>;
2566d28c
JH		 848 resets = <&bpmp TEGRA234_RESET_PWM2>;
849 reset-names = "pwm";
850 status = "disabled";
851 #pwm-cells = <2>;
852 };
853
854 pwm3: pwm@32a0000 {
855 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 856 reg = <0x0 0x32a0000 0x0 0x10000>;
2566d28c 857 clocks = <&bpmp TEGRA234_CLK_PWM3>;
2566d28c
JH		 858 resets = <&bpmp TEGRA234_RESET_PWM3>;
859 reset-names = "pwm";
860 status = "disabled";
861 #pwm-cells = <2>;
862 };
863
864 pwm5: pwm@32c0000 {
865 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 866 reg = <0x0 0x32c0000 0x0 0x10000>;
2566d28c 867 clocks = <&bpmp TEGRA234_CLK_PWM5>;
2566d28c
JH		 868 resets = <&bpmp TEGRA234_RESET_PWM5>;
869 reset-names = "pwm";
870 status = "disabled";
871 #pwm-cells = <2>;
872 };
873
874 pwm6: pwm@32d0000 {
875 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 876 reg = <0x0 0x32d0000 0x0 0x10000>;
2566d28c 877 clocks = <&bpmp TEGRA234_CLK_PWM6>;
2566d28c
JH		 878 resets = <&bpmp TEGRA234_RESET_PWM6>;
879 reset-names = "pwm";
880 status = "disabled";
881 #pwm-cells = <2>;
882 };
883
884 pwm7: pwm@32e0000 {
885 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 886 reg = <0x0 0x32e0000 0x0 0x10000>;
2566d28c 887 clocks = <&bpmp TEGRA234_CLK_PWM7>;
2566d28c
JH		 888 resets = <&bpmp TEGRA234_RESET_PWM7>;
889 reset-names = "pwm";
890 status = "disabled";
891 #pwm-cells = <2>;
892 };
893
894 pwm8: pwm@32f0000 {
895 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 896 reg = <0x0 0x32f0000 0x0 0x10000>;
2566d28c 897 clocks = <&bpmp TEGRA234_CLK_PWM8>;
2566d28c
JH		 898 resets = <&bpmp TEGRA234_RESET_PWM8>;
899 reset-names = "pwm";
900 status = "disabled";
901 #pwm-cells = <2>;
902 };
903
71f69ffa
AS		 904 spi@3300000 {
905 compatible = "nvidia,tegra234-qspi";
2838cfdd 906 reg = <0x0 0x3300000 0x0 0x1000>;
71f69ffa
AS		 907 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
908 #address-cells = <1>;
909 #size-cells = <0>;
910 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
911 <&bpmp TEGRA234_CLK_QSPI1_PM>;
912 clock-names = "qspi", "qspi_out";
913 resets = <&bpmp TEGRA234_RESET_QSPI1>;
71f69ffa
AS		 914 status = "disabled";
915 };
916
d71b893a 917 mmc@3400000 {
132b552c 918 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
2838cfdd 919 reg = <0x0 0x03400000 0x0 0x20000>;
d71b893a
PS		 920 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
922 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
923 clock-names = "sdhci", "tmclk";
924 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
925 <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
926 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
927 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
928 resets = <&bpmp TEGRA234_RESET_SDMMC1>;
929 reset-names = "sdhci";
930 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
931 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
932 interconnect-names = "dma-mem", "write";
933 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
934 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
935 pinctrl-0 = <&sdmmc1_3v3>;
936 pinctrl-1 = <&sdmmc1_1v8>;
937 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
938 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
939 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
940 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
941 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
942 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
943 nvidia,default-tap = <14>;
944 nvidia,default-trim = <0x8>;
945 sd-uhs-sdr25;
946 sd-uhs-sdr50;
947 sd-uhs-ddr50;
948 sd-uhs-sdr104;
949 status = "disabled";
950 };
951
63944891
TR		 952 mmc@3460000 {
953 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
2838cfdd 954 reg = <0x0 0x03460000 0x0 0x20000>;
63944891 955 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
e086d82d
MP		 956 clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
957 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
958 clock-names = "sdhci", "tmclk";
959 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
960 <&bpmp TEGRA234_CLK_PLLC4>;
961 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
63944891
TR		 962 resets = <&bpmp TEGRA234_RESET_SDMMC4>;
963 reset-names = "sdhci";
6de481e5
TR		 964 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
965 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
966 interconnect-names = "dma-mem", "write";
5710e16a 967 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
e086d82d
MP		 968 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
969 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
970 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
971 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
972 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
973 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
974 nvidia,default-tap = <0x8>;
975 nvidia,default-trim = <0x14>;
976 nvidia,dqs-trim = <40>;
977 supports-cqe;
63944891
TR		 978 status = "disabled";
979 };
980
621e12a1 981 hda@3510000 {
b2fbcbe1 982 compatible = "nvidia,tegra234-hda";
2838cfdd 983 reg = <0x0 0x3510000 0x0 0x10000>;
621e12a1
MK		 984 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
985 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
986 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
987 clock-names = "hda", "hda2codec_2x";
988 resets = <&bpmp TEGRA234_RESET_HDA>,
989 <&bpmp TEGRA234_RESET_HDACODEC>;
990 reset-names = "hda", "hda2codec_2x";
991 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
992 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
993 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
994 interconnect-names = "dma-mem", "write";
af4c2773 995 iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
621e12a1
MK		 996 status = "disabled";
997 };
998
6e505dd6
WC		 999 xusb_padctl: padctl@3520000 {
1000 compatible = "nvidia,tegra234-xusb-padctl";
1001 reg = <0x0 0x03520000 0x0 0x20000>,
1002 <0x0 0x03540000 0x0 0x10000>;
1003 reg-names = "padctl", "ao";
1004 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
1005
1006 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
1007 reset-names = "padctl";
1008
1009 status = "disabled";
1010
1011 pads {
1012 usb2 {
1013 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
1014 clock-names = "trk";
1015
1016 lanes {
1017 usb2-0 {
1018 nvidia,function = "xusb";
1019 status = "disabled";
1020 #phy-cells = <0>;
1021 };
1022
1023 usb2-1 {
1024 nvidia,function = "xusb";
1025 status = "disabled";
1026 #phy-cells = <0>;
1027 };
1028
1029 usb2-2 {
1030 nvidia,function = "xusb";
1031 status = "disabled";
1032 #phy-cells = <0>;
1033 };
1034
1035 usb2-3 {
1036 nvidia,function = "xusb";
1037 status = "disabled";
1038 #phy-cells = <0>;
1039 };
1040 };
1041 };
1042
1043 usb3 {
1044 lanes {
1045 usb3-0 {
1046 nvidia,function = "xusb";
1047 status = "disabled";
1048 #phy-cells = <0>;
1049 };
1050
1051 usb3-1 {
1052 nvidia,function = "xusb";
1053 status = "disabled";
1054 #phy-cells = <0>;
1055 };
1056
1057 usb3-2 {
1058 nvidia,function = "xusb";
1059 status = "disabled";
1060 #phy-cells = <0>;
1061 };
1062
1063 usb3-3 {
1064 nvidia,function = "xusb";
1065 status = "disabled";
1066 #phy-cells = <0>;
1067 };
1068 };
1069 };
1070 };
1071
1072 ports {
1073 usb2-0 {
1074 status = "disabled";
1075 };
1076
1077 usb2-1 {
1078 status = "disabled";
1079 };
1080
1081 usb2-2 {
1082 status = "disabled";
1083 };
1084
1085 usb2-3 {
1086 status = "disabled";
1087 };
1088
1089 usb3-0 {
1090 status = "disabled";
1091 };
1092
1093 usb3-1 {
1094 status = "disabled";
1095 };
1096
1097 usb3-2 {
1098 status = "disabled";
1099 };
1100
1101 usb3-3 {
1102 status = "disabled";
1103 };
1104 };
1105 };
1106
320e0a70
JH		 1107 usb@3550000 {
1108 compatible = "nvidia,tegra234-xudc";
1109 reg = <0x0 0x03550000 0x0 0x8000>,
1110 <0x0 0x03558000 0x0 0x8000>;
1111 reg-names = "base", "fpci";
1112 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1113 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
1114 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1115 <&bpmp TEGRA234_CLK_XUSB_SS>,
1116 <&bpmp TEGRA234_CLK_XUSB_FS>;
1117 clock-names = "dev", "ss", "ss_src", "fs_src";
1118 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>,
1119 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>;
1120 interconnect-names = "dma-mem", "write";
1121 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>;
1122 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
1123 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1124 power-domain-names = "dev", "ss";
1125 nvidia,xusb-padctl = <&xusb_padctl>;
1126 dma-coherent;
1127 status = "disabled";
1128 };
1129
6e505dd6
WC		 1130 usb@3610000 {
1131 compatible = "nvidia,tegra234-xusb";
1132 reg = <0x0 0x03610000 0x0 0x40000>,
1133 <0x0 0x03600000 0x0 0x10000>,
1134 <0x0 0x03650000 0x0 0x10000>;
1135 reg-names = "hcd", "fpci", "bar2";
1136
1137 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1138 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1139
1140 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
1141 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
1142 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1143 <&bpmp TEGRA234_CLK_XUSB_SS>,
1144 <&bpmp TEGRA234_CLK_CLK_M>,
1145 <&bpmp TEGRA234_CLK_XUSB_FS>,
1146 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
1147 <&bpmp TEGRA234_CLK_CLK_M>,
1148 <&bpmp TEGRA234_CLK_PLLE>;
1149 clock-names = "xusb_host", "xusb_falcon_src",
1150 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1151 "xusb_fs_src", "pll_u_480m", "clk_m",
1152 "pll_e";
1153 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1154 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1155 interconnect-names = "dma-mem", "write";
1156 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>;
1157
1158 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
1159 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1160 power-domain-names = "xusb_host", "xusb_ss";
1161
1162 nvidia,xusb-padctl = <&xusb_padctl>;
1163 dma-coherent;
1164 status = "disabled";
1165 };
1166
63944891
TR		 1167 fuse@3810000 {
1168 compatible = "nvidia,tegra234-efuse";
2838cfdd 1169 reg = <0x0 0x03810000 0x0 0x10000>;
63944891
TR		 1170 clocks = <&bpmp TEGRA234_CLK_FUSE>;
1171 clock-names = "fuse";
1172 };
1173
29662d62
DP		 1174 hte_lic: hardware-timestamp@3aa0000 {
1175 compatible = "nvidia,tegra234-gte-lic";
1176 reg = <0x0 0x3aa0000 0x0 0x10000>;
1177 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1178 nvidia,int-threshold = <1>;
1179 #timestamp-cells = <1>;
1180 };
1181
63944891
TR		 1182 hsp_top0: hsp@3c00000 {
1183 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
2838cfdd 1184 reg = <0x0 0x03c00000 0x0 0xa0000>;
63944891
TR		 1185 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1186 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1187 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1188 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1189 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1190 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1191 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1192 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1193 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1194 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1195 "shared3", "shared4", "shared5", "shared6",
1196 "shared7";
1197 #mbox-cells = <2>;
1198 };
1199
78159542
TR		 1200 p2u_hsio_0: phy@3e00000 {
1201 compatible = "nvidia,tegra234-p2u";
2838cfdd 1202 reg = <0x0 0x03e00000 0x0 0x10000>;
78159542
TR		 1203 reg-names = "ctl";
1204
1205 #phy-cells = <0>;
1206 };
1207
1208 p2u_hsio_1: phy@3e10000 {
1209 compatible = "nvidia,tegra234-p2u";
2838cfdd 1210 reg = <0x0 0x03e10000 0x0 0x10000>;
78159542
TR		 1211 reg-names = "ctl";
1212
1213 #phy-cells = <0>;
1214 };
1215
1216 p2u_hsio_2: phy@3e20000 {
1217 compatible = "nvidia,tegra234-p2u";
2838cfdd 1218 reg = <0x0 0x03e20000 0x0 0x10000>;
78159542
TR		 1219 reg-names = "ctl";
1220
1221 #phy-cells = <0>;
1222 };
1223
1224 p2u_hsio_3: phy@3e30000 {
1225 compatible = "nvidia,tegra234-p2u";
2838cfdd 1226 reg = <0x0 0x03e30000 0x0 0x10000>;
78159542
TR		 1227 reg-names = "ctl";
1228
1229 #phy-cells = <0>;
1230 };
1231
1232 p2u_hsio_4: phy@3e40000 {
1233 compatible = "nvidia,tegra234-p2u";
2838cfdd 1234 reg = <0x0 0x03e40000 0x0 0x10000>;
78159542
TR		 1235 reg-names = "ctl";
1236
1237 #phy-cells = <0>;
1238 };
1239
1240 p2u_hsio_5: phy@3e50000 {
1241 compatible = "nvidia,tegra234-p2u";
2838cfdd 1242 reg = <0x0 0x03e50000 0x0 0x10000>;
78159542
TR		 1243 reg-names = "ctl";
1244
1245 #phy-cells = <0>;
1246 };
1247
1248 p2u_hsio_6: phy@3e60000 {
1249 compatible = "nvidia,tegra234-p2u";
2838cfdd 1250 reg = <0x0 0x03e60000 0x0 0x10000>;
78159542
TR		 1251 reg-names = "ctl";
1252
1253 #phy-cells = <0>;
1254 };
1255
1256 p2u_hsio_7: phy@3e70000 {
1257 compatible = "nvidia,tegra234-p2u";
2838cfdd 1258 reg = <0x0 0x03e70000 0x0 0x10000>;
78159542
TR		 1259 reg-names = "ctl";
1260
1261 #phy-cells = <0>;
1262 };
1263
1264 p2u_nvhs_0: phy@3e90000 {
1265 compatible = "nvidia,tegra234-p2u";
2838cfdd 1266 reg = <0x0 0x03e90000 0x0 0x10000>;
78159542
TR		 1267 reg-names = "ctl";
1268
1269 #phy-cells = <0>;
1270 };
1271
1272 p2u_nvhs_1: phy@3ea0000 {
1273 compatible = "nvidia,tegra234-p2u";
2838cfdd 1274 reg = <0x0 0x03ea0000 0x0 0x10000>;
78159542
TR		 1275 reg-names = "ctl";
1276
1277 #phy-cells = <0>;
1278 };
1279
1280 p2u_nvhs_2: phy@3eb0000 {
1281 compatible = "nvidia,tegra234-p2u";
2838cfdd 1282 reg = <0x0 0x03eb0000 0x0 0x10000>;
78159542
TR		 1283 reg-names = "ctl";
1284
1285 #phy-cells = <0>;
1286 };
1287
1288 p2u_nvhs_3: phy@3ec0000 {
1289 compatible = "nvidia,tegra234-p2u";
2838cfdd 1290 reg = <0x0 0x03ec0000 0x0 0x10000>;
78159542
TR		 1291 reg-names = "ctl";
1292
1293 #phy-cells = <0>;
1294 };
1295
1296 p2u_nvhs_4: phy@3ed0000 {
1297 compatible = "nvidia,tegra234-p2u";
2838cfdd 1298 reg = <0x0 0x03ed0000 0x0 0x10000>;
78159542
TR		 1299 reg-names = "ctl";
1300
1301 #phy-cells = <0>;
1302 };
1303
1304 p2u_nvhs_5: phy@3ee0000 {
1305 compatible = "nvidia,tegra234-p2u";
2838cfdd 1306 reg = <0x0 0x03ee0000 0x0 0x10000>;
78159542
TR		 1307 reg-names = "ctl";
1308
1309 #phy-cells = <0>;
1310 };
1311
1312 p2u_nvhs_6: phy@3ef0000 {
1313 compatible = "nvidia,tegra234-p2u";
2838cfdd 1314 reg = <0x0 0x03ef0000 0x0 0x10000>;
78159542
TR		 1315 reg-names = "ctl";
1316
1317 #phy-cells = <0>;
1318 };
1319
1320 p2u_nvhs_7: phy@3f00000 {
1321 compatible = "nvidia,tegra234-p2u";
2838cfdd 1322 reg = <0x0 0x03f00000 0x0 0x10000>;
78159542
TR		 1323 reg-names = "ctl";
1324
1325 #phy-cells = <0>;
1326 };
1327
1328 p2u_gbe_0: phy@3f20000 {
1329 compatible = "nvidia,tegra234-p2u";
2838cfdd 1330 reg = <0x0 0x03f20000 0x0 0x10000>;
78159542
TR		 1331 reg-names = "ctl";
1332
1333 #phy-cells = <0>;
1334 };
1335
1336 p2u_gbe_1: phy@3f30000 {
1337 compatible = "nvidia,tegra234-p2u";
2838cfdd 1338 reg = <0x0 0x03f30000 0x0 0x10000>;
78159542
TR		 1339 reg-names = "ctl";
1340
1341 #phy-cells = <0>;
1342 };
1343
1344 p2u_gbe_2: phy@3f40000 {
1345 compatible = "nvidia,tegra234-p2u";
2838cfdd 1346 reg = <0x0 0x03f40000 0x0 0x10000>;
78159542
TR		 1347 reg-names = "ctl";
1348
1349 #phy-cells = <0>;
1350 };
1351
1352 p2u_gbe_3: phy@3f50000 {
1353 compatible = "nvidia,tegra234-p2u";
2838cfdd 1354 reg = <0x0 0x03f50000 0x0 0x10000>;
78159542
TR		 1355 reg-names = "ctl";
1356
1357 #phy-cells = <0>;
1358 };
1359
1360 p2u_gbe_4: phy@3f60000 {
1361 compatible = "nvidia,tegra234-p2u";
2838cfdd 1362 reg = <0x0 0x03f60000 0x0 0x10000>;
78159542
TR		 1363 reg-names = "ctl";
1364
1365 #phy-cells = <0>;
1366 };
1367
1368 p2u_gbe_5: phy@3f70000 {
1369 compatible = "nvidia,tegra234-p2u";
2838cfdd 1370 reg = <0x0 0x03f70000 0x0 0x10000>;
78159542
TR		 1371 reg-names = "ctl";
1372
1373 #phy-cells = <0>;
1374 };
1375
1376 p2u_gbe_6: phy@3f80000 {
1377 compatible = "nvidia,tegra234-p2u";
2838cfdd 1378 reg = <0x0 0x03f80000 0x0 0x10000>;
78159542
TR		 1379 reg-names = "ctl";
1380
1381 #phy-cells = <0>;
1382 };
1383
1384 p2u_gbe_7: phy@3f90000 {
1385 compatible = "nvidia,tegra234-p2u";
2838cfdd 1386 reg = <0x0 0x03f90000 0x0 0x10000>;
78159542
TR		 1387 reg-names = "ctl";
1388
1389 #phy-cells = <0>;
1390 };
1391
610cdf31
TR		 1392 ethernet@6800000 {
1393 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1394 reg = <0x0 0x06800000 0x0 0x10000>,
1395 <0x0 0x06810000 0x0 0x10000>,
1396 <0x0 0x068a0000 0x0 0x10000>;
610cdf31
TR		 1397 reg-names = "hypervisor", "mac", "xpcs";
1398 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
1399 interrupt-names = "common";
1400 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
1401 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
1402 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
1403 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
1404 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
1405 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
1406 <&bpmp TEGRA234_CLK_MGBE0_TX>,
1407 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
1408 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
1409 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
1410 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
1411 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
1412 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1413 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1414 "rx-pcs", "tx-pcs";
1415 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
1416 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
1417 reset-names = "mac", "pcs";
1418 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
1419 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
1420 interconnect-names = "dma-mem", "write";
1421 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
1422 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1423 status = "disabled";
1424 };
1425
1426 ethernet@6900000 {
1427 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1428 reg = <0x0 0x06900000 0x0 0x10000>,
1429 <0x0 0x06910000 0x0 0x10000>,
1430 <0x0 0x069a0000 0x0 0x10000>;
610cdf31
TR		 1431 reg-names = "hypervisor", "mac", "xpcs";
1432 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
1433 interrupt-names = "common";
1434 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1435 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1436 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1437 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1438 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1439 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1440 <&bpmp TEGRA234_CLK_MGBE1_TX>,
1441 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1442 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1443 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1444 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1445 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1446 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1447 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1448 "rx-pcs", "tx-pcs";
1449 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1450 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1451 reset-names = "mac", "pcs";
1452 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
1453 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
1454 interconnect-names = "dma-mem", "write";
1455 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
1456 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1457 status = "disabled";
1458 };
1459
1460 ethernet@6a00000 {
1461 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1462 reg = <0x0 0x06a00000 0x0 0x10000>,
1463 <0x0 0x06a10000 0x0 0x10000>,
1464 <0x0 0x06aa0000 0x0 0x10000>;
610cdf31
TR		 1465 reg-names = "hypervisor", "mac", "xpcs";
1466 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
1467 interrupt-names = "common";
1468 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1469 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1470 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1471 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1472 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1473 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1474 <&bpmp TEGRA234_CLK_MGBE2_TX>,
1475 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1476 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1477 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1478 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1479 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1480 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1481 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1482 "rx-pcs", "tx-pcs";
1483 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1484 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1485 reset-names = "mac", "pcs";
1486 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
1487 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
1488 interconnect-names = "dma-mem", "write";
1489 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
1490 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1491 status = "disabled";
1492 };
1493
1494 ethernet@6b00000 {
1495 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1496 reg = <0x0 0x06b00000 0x0 0x10000>,
1497 <0x0 0x06b10000 0x0 0x10000>,
1498 <0x0 0x06ba0000 0x0 0x10000>;
610cdf31
TR		 1499 reg-names = "hypervisor", "mac", "xpcs";
1500 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1501 interrupt-names = "common";
1502 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1503 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1504 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1505 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1506 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1507 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1508 <&bpmp TEGRA234_CLK_MGBE3_TX>,
1509 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1510 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1511 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1512 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1513 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1514 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1515 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1516 "rx-pcs", "tx-pcs";
1517 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1518 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1519 reset-names = "mac", "pcs";
1520 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
1521 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
1522 interconnect-names = "dma-mem", "write";
1523 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
1524 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1525 status = "disabled";
1526 };
1527
5710e16a
TR		 1528 smmu_niso1: iommu@8000000 {
1529 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd
TR		 1530 reg = <0x0 0x8000000 0x0 0x1000000>,
1531 <0x0 0x7000000 0x0 0x1000000>;
5710e16a
TR		 1532 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1628 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1629 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1630 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1631 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1632 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1633 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1634 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1635 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1636 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1637 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1638 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1639 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1640 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1641 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1642 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1643 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1644 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1646 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1647 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1648 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1649 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1650 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1652 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1653 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1654 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1655 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1656 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1657 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1658 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1659 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1660 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1661 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1662 stream-match-mask = <0x7f80>;
1663 #global-interrupts = <2>;
1664 #iommu-cells = <1>;
1665
1666 nvidia,memory-controller = <&mc>;
1667 status = "okay";
1668 };
1669
302e1540
SG		 1670 sce-fabric@b600000 {
1671 compatible = "nvidia,tegra234-sce-fabric";
2838cfdd 1672 reg = <0x0 0xb600000 0x0 0x40000>;
302e1540
SG		 1673 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
1674 status = "okay";
1675 };
1676
1677 rce-fabric@be00000 {
1678 compatible = "nvidia,tegra234-rce-fabric";
2838cfdd 1679 reg = <0x0 0xbe00000 0x0 0x40000>;
302e1540
SG		 1680 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1681 status = "okay";
1682 };
1683
63944891
TR		 1684 hsp_aon: hsp@c150000 {
1685 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
2838cfdd 1686 reg = <0x0 0x0c150000 0x0 0x90000>;
63944891
TR		 1687 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1688 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1689 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1690 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1691 /*
1692 * Shared interrupt 0 is routed only to AON/SPE, so
1693 * we only have 4 shared interrupts for the CCPLEX.
1694 */
1695 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1696 #mbox-cells = <2>;
1697 };
1698
29662d62
DP		 1699 hte_aon: hardware-timestamp@c1e0000 {
1700 compatible = "nvidia,tegra234-gte-aon";
1701 reg = <0x0 0xc1e0000 0x0 0x10000>;
1702 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1703 nvidia,int-threshold = <1>;
1704 nvidia,gpio-controller = <&gpio_aon>;
1705 #timestamp-cells = <1>;
1706 };
1707
156af9de
A		 1708 gen2_i2c: i2c@c240000 {
1709 compatible = "nvidia,tegra194-i2c";
2838cfdd 1710 reg = <0x0 0xc240000 0x0 0x100>;
156af9de 1711 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 1712 #address-cells = <1>;
1713 #size-cells = <0>;
156af9de
A		 1714 status = "disabled";
1715 clock-frequency = <100000>;
1716 clocks = <&bpmp TEGRA234_CLK_I2C2
1717 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1718 clock-names = "div-clk", "parent";
1719 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1720 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1721 resets = <&bpmp TEGRA234_RESET_I2C2>;
1722 reset-names = "i2c";
8e442805
A		 1723 dmas = <&gpcdma 22>, <&gpcdma 22>;
1724 dma-names = "rx", "tx";
156af9de
A		 1725 };
1726
1727 gen8_i2c: i2c@c250000 {
1728 compatible = "nvidia,tegra194-i2c";
2838cfdd 1729 reg = <0x0 0xc250000 0x0 0x100>;
156af9de 1730 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 1731 #address-cells = <1>;
1732 #size-cells = <0>;
156af9de
A		 1733 status = "disabled";
1734 clock-frequency = <400000>;
1735 clocks = <&bpmp TEGRA234_CLK_I2C8
1736 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1737 clock-names = "div-clk", "parent";
1738 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1739 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1740 resets = <&bpmp TEGRA234_RESET_I2C8>;
1741 reset-names = "i2c";
8e442805
A		 1742 dmas = <&gpcdma 0>, <&gpcdma 0>;
1743 dma-names = "rx", "tx";
156af9de
A		 1744 };
1745
63944891
TR		 1746 rtc@c2a0000 {
1747 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
2838cfdd 1748 reg = <0x0 0x0c2a0000 0x0 0x10000>;
63944891
TR		 1749 interrupt-parent = <&pmc>;
1750 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
e537adde
MP		 1751 clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1752 clock-names = "rtc";
63944891
TR		 1753 status = "disabled";
1754 };
1755
f0e12668
TR		 1756 gpio_aon: gpio@c2f0000 {
1757 compatible = "nvidia,tegra234-gpio-aon";
1758 reg-names = "security", "gpio";
2838cfdd
TR		 1759 reg = <0x0 0x0c2f0000 0x0 0x1000>,
1760 <0x0 0x0c2f1000 0x0 0x1000>;
f0e12668
TR		 1761 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1762 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1763 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1764 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1765 #interrupt-cells = <2>;
1766 interrupt-controller;
1767 #gpio-cells = <2>;
1768 gpio-controller;
282fde00
PS		 1769 gpio-ranges = <&pinmux_aon 0 0 32>;
1770 };
1771
1772 pinmux_aon: pinmux@c300000 {
1773 compatible = "nvidia,tegra234-pinmux-aon";
1774 reg = <0x0 0xc300000 0x0 0x4000>;
f0e12668
TR		 1775 };
1776
2566d28c
JH		 1777 pwm4: pwm@c340000 {
1778 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 1779 reg = <0x0 0xc340000 0x0 0x10000>;
2566d28c 1780 clocks = <&bpmp TEGRA234_CLK_PWM4>;
2566d28c
JH		 1781 resets = <&bpmp TEGRA234_RESET_PWM4>;
1782 reset-names = "pwm";
1783 status = "disabled";
1784 #pwm-cells = <2>;
1785 };
1786
63944891
TR		 1787 pmc: pmc@c360000 {
1788 compatible = "nvidia,tegra234-pmc";
2838cfdd
TR		 1789 reg = <0x0 0x0c360000 0x0 0x10000>,
1790 <0x0 0x0c370000 0x0 0x10000>,
1791 <0x0 0x0c380000 0x0 0x10000>,
1792 <0x0 0x0c390000 0x0 0x10000>,
1793 <0x0 0x0c3a0000 0x0 0x10000>;
63944891
TR		 1794 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1795
1796 #interrupt-cells = <2>;
1797 interrupt-controller;
d71b893a 1798
d71b893a
PS		 1799 sdmmc1_1v8: sdmmc1-1v8 {
1800 pins = "sdmmc1-hv";
1801 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1802 };
1803
79ed18d9
TR		 1804 sdmmc1_3v3: sdmmc1-3v3 {
1805 pins = "sdmmc1-hv";
d71b893a
PS		 1806 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1807 };
1808
1809 sdmmc3_1v8: sdmmc3-1v8 {
1810 pins = "sdmmc3-hv";
1811 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1812 };
79ed18d9
TR		 1813
1814 sdmmc3_3v3: sdmmc3-3v3 {
1815 pins = "sdmmc3-hv";
1816 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1817 };
63944891
TR		 1818 };
1819
302e1540
SG		 1820 aon-fabric@c600000 {
1821 compatible = "nvidia,tegra234-aon-fabric";
2838cfdd 1822 reg = <0x0 0xc600000 0x0 0x40000>;
302e1540
SG		 1823 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1824 status = "okay";
1825 };
1826
1827 bpmp-fabric@d600000 {
1828 compatible = "nvidia,tegra234-bpmp-fabric";
2838cfdd 1829 reg = <0x0 0xd600000 0x0 0x40000>;
302e1540
SG		 1830 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1831 status = "okay";
1832 };
1833
1834 dce-fabric@de00000 {
1835 compatible = "nvidia,tegra234-sce-fabric";
2838cfdd 1836 reg = <0x0 0xde00000 0x0 0x40000>;
302e1540
SG		 1837 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
1838 status = "okay";
1839 };
1840
2838cfdd
TR		 1841 ccplex@e000000 {
1842 compatible = "nvidia,tegra234-ccplex-cluster";
1843 reg = <0x0 0x0e000000 0x0 0x5ffff>;
1844 nvidia,bpmp = <&bpmp>;
1845 status = "okay";
1846 };
1847
63944891
TR		 1848 gic: interrupt-controller@f400000 {
1849 compatible = "arm,gic-v3";
2838cfdd
TR		 1850 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
1851 <0x0 0x0f440000 0x0 0x200000>; /* GICR */
63944891
TR		 1852 interrupt-parent = <&gic>;
1853 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1854
1855 #redistributor-regions = <1>;
1856 #interrupt-cells = <3>;
1857 interrupt-controller;
1858 };
5710e16a 1859
58bf48a2 1860 smmu_iso: iommu@10000000 {
5710e16a 1861 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd 1862 reg = <0x0 0x10000000 0x0 0x1000000>;
5710e16a
TR		 1863 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1955 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1964 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1972 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1973 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1974 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1975 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1976 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1977 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1978 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1979 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1980 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1981 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1983 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1984 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1985 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1986 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1987 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1988 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1989 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1990 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1991 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1992 stream-match-mask = <0x7f80>;
1993 #global-interrupts = <1>;
1994 #iommu-cells = <1>;
1995
1996 nvidia,memory-controller = <&mc>;
1997 status = "okay";
1998 };
1999
2000 smmu_niso0: iommu@12000000 {
2001 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd
TR		 2002 reg = <0x0 0x12000000 0x0 0x1000000>,
2003 <0x0 0x11000000 0x0 0x1000000>;
5710e16a
TR		 2004 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2005 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2007 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2055 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2056 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2057 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2058 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2059 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2060 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2061 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2062 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2063 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2064 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2065 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2066 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2067 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2068 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2069 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2070 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2071 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2072 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2073 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2074 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2075 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2076 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2077 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2078 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2079 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2080 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2112 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2113 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2114 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2115 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2116 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2117 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2118 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2119 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2120 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2121 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2122 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2123 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2124 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2125 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2126 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2127 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2128 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2129 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2130 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2131 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2132 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2133 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2134 stream-match-mask = <0x7f80>;
2135 #global-interrupts = <2>;
2136 #iommu-cells = <1>;
2137
2138 nvidia,memory-controller = <&mc>;
2139 status = "okay";
2140 };
302e1540
SG		 2141
2142 cbb-fabric@13a00000 {
2143 compatible = "nvidia,tegra234-cbb-fabric";
2838cfdd 2144 reg = <0x0 0x13a00000 0x0 0x400000>;
302e1540
SG		 2145 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
2146 status = "okay";
2147 };
63944891 2148
79ed18d9
TR		 2149 host1x@13e00000 {
2150 compatible = "nvidia,tegra234-host1x";
2151 reg = <0x0 0x13e00000 0x0 0x10000>,
2152 <0x0 0x13e10000 0x0 0x10000>,
2153 <0x0 0x13e40000 0x0 0x10000>;
2154 reg-names = "common", "hypervisor", "vm";
2155 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
2156 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
2157 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
2158 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
2159 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
2160 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
2161 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
2162 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
2163 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2164 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
2165 "syncpt5", "syncpt6", "syncpt7", "host1x";
2166 clocks = <&bpmp TEGRA234_CLK_HOST1X>;
2167 clock-names = "host1x";
2168
2169 #address-cells = <2>;
2170 #size-cells = <2>;
2171 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
2172
2173 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
2174 interconnect-names = "dma-mem";
2175 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
361238cd 2176 dma-coherent;
79ed18d9
TR		 2177
2178 /* Context isolation domains */
2179 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2180 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
2181 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
2182 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
2183 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
2184 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
2185 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
2186 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
2187 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
2188 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
2189 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
2190 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
2191 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
2192 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
2193 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
2194 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
2195
2196 vic@15340000 {
2197 compatible = "nvidia,tegra234-vic";
2198 reg = <0x0 0x15340000 0x0 0x00040000>;
2199 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2200 clocks = <&bpmp TEGRA234_CLK_VIC>;
2201 clock-names = "vic";
2202 resets = <&bpmp TEGRA234_RESET_VIC>;
2203 reset-names = "vic";
2204
2205 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
2206 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>,
2207 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>;
2208 interconnect-names = "dma-mem", "write";
2209 iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
2210 dma-coherent;
2211 };
2212
2213 nvdec@15480000 {
2214 compatible = "nvidia,tegra234-nvdec";
2215 reg = <0x0 0x15480000 0x0 0x00040000>;
2216 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
2217 <&bpmp TEGRA234_CLK_FUSE>,
2218 <&bpmp TEGRA234_CLK_TSEC_PKA>;
2219 clock-names = "nvdec", "fuse", "tsec_pka";
2220 resets = <&bpmp TEGRA234_RESET_NVDEC>;
2221 reset-names = "nvdec";
2222 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
2223 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
2224 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
2225 interconnect-names = "dma-mem", "write";
2226 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
2227 dma-coherent;
2228
2229 nvidia,memory-controller = <&mc>;
2230
2231 /*
2232 * Placeholder values that firmware needs to update with the real
2233 * offsets parsed from the microcode headers.
2234 */
2235 nvidia,bl-manifest-offset = <0>;
2236 nvidia,bl-data-offset = <0>;
2237 nvidia,bl-code-offset = <0>;
2238 nvidia,os-manifest-offset = <0>;
2239 nvidia,os-data-offset = <0>;
2240 nvidia,os-code-offset = <0>;
2241
2242 /*
2243 * Firmware needs to set this to "okay" once the above values have
2244 * been updated.
2245 */
2246 status = "disabled";
2247 };
2248 };
2249
2838cfdd
TR		 2250 pcie@140a0000 {
2251 compatible = "nvidia,tegra234-pcie";
2252 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2253 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
2254 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
2255 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2256 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2257 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2258 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
962c400d 2259
2838cfdd
TR		 2260 #address-cells = <3>;
2261 #size-cells = <2>;
2262 device_type = "pci";
2263 num-lanes = <4>;
2264 num-viewport = <8>;
2265 linux,pci-domain = <8>;
ec142c44 2266
2838cfdd
TR		 2267 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
2268 clock-names = "core";
ec142c44 2269
2838cfdd
TR		 2270 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
2271 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
2272 reset-names = "apb", "core";
ec142c44 2273
2838cfdd
TR		 2274 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2275 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2276 interrupt-names = "intr", "msi";
ec142c44 2277
2838cfdd
TR		 2278 #interrupt-cells = <1>;
2279 interrupt-map-mask = <0 0 0 0>;
2280 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2281
2838cfdd 2282 nvidia,bpmp = <&bpmp 8>;
ec142c44 2283
2838cfdd
TR		 2284 nvidia,aspm-cmrt-us = <60>;
2285 nvidia,aspm-pwr-on-t-us = <20>;
2286 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2287
2838cfdd 2288 bus-range = <0x0 0xff>;
ec142c44 2289
2838cfdd
TR		 2290 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2291 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2292 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2293
2838cfdd
TR		 2294 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
2295 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
2296 interconnect-names = "dma-mem", "write";
2297 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2298 iommu-map-mask = <0x0>;
2299 dma-coherent;
ec142c44 2300
2838cfdd
TR		 2301 status = "disabled";
2302 };
ec142c44 2303
2838cfdd
TR		 2304 pcie@140c0000 {
2305 compatible = "nvidia,tegra234-pcie";
2306 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2307 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
2308 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
2309 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2310 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2311 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2312 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2313
2838cfdd
TR		 2314 #address-cells = <3>;
2315 #size-cells = <2>;
2316 device_type = "pci";
2317 num-lanes = <4>;
2318 num-viewport = <8>;
2319 linux,pci-domain = <9>;
ec142c44 2320
2838cfdd
TR		 2321 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
2322 clock-names = "core";
ec142c44 2323
2838cfdd
TR		 2324 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
2325 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
2326 reset-names = "apb", "core";
ec142c44 2327
2838cfdd
TR		 2328 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2329 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2330 interrupt-names = "intr", "msi";
ec142c44 2331
2838cfdd
TR		 2332 #interrupt-cells = <1>;
2333 interrupt-map-mask = <0 0 0 0>;
2334 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2335
2838cfdd 2336 nvidia,bpmp = <&bpmp 9>;
ec142c44 2337
2838cfdd
TR		 2338 nvidia,aspm-cmrt-us = <60>;
2339 nvidia,aspm-pwr-on-t-us = <20>;
2340 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2341
2838cfdd 2342 bus-range = <0x0 0xff>;
ec142c44 2343
2838cfdd
TR		 2344 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
2345 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2346 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2347
2838cfdd
TR		 2348 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
2349 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
2350 interconnect-names = "dma-mem", "write";
2351 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2352 iommu-map-mask = <0x0>;
2353 dma-coherent;
ec142c44 2354
2838cfdd
TR		 2355 status = "disabled";
2356 };
ec142c44 2357
2838cfdd
TR		 2358 pcie@140e0000 {
2359 compatible = "nvidia,tegra234-pcie";
2360 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2361 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2362 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
2363 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2364 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2365 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2366 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2367
2838cfdd
TR		 2368 #address-cells = <3>;
2369 #size-cells = <2>;
2370 device_type = "pci";
2371 num-lanes = <4>;
2372 num-viewport = <8>;
2373 linux,pci-domain = <10>;
ec142c44 2374
2838cfdd
TR		 2375 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2376 clock-names = "core";
ec142c44 2377
2838cfdd
TR		 2378 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2379 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2380 reset-names = "apb", "core";
ec142c44 2381
2838cfdd
TR		 2382 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2383 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2384 interrupt-names = "intr", "msi";
ec142c44 2385
2838cfdd
TR		 2386 #interrupt-cells = <1>;
2387 interrupt-map-mask = <0 0 0 0>;
2388 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2389
2838cfdd 2390 nvidia,bpmp = <&bpmp 10>;
ec142c44 2391
2838cfdd
TR		 2392 nvidia,aspm-cmrt-us = <60>;
2393 nvidia,aspm-pwr-on-t-us = <20>;
2394 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2395
2838cfdd 2396 bus-range = <0x0 0xff>;
ec142c44 2397
2838cfdd
TR		 2398 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2399 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2400 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2401
2838cfdd
TR		 2402 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2403 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2404 interconnect-names = "dma-mem", "write";
2405 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2406 iommu-map-mask = <0x0>;
2407 dma-coherent;
ec142c44 2408
2838cfdd
TR		 2409 status = "disabled";
2410 };
ec142c44 2411
2838cfdd
TR		 2412 pcie-ep@140e0000 {
2413 compatible = "nvidia,tegra234-pcie-ep";
2414 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2415 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2416 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2417 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
2418 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2419 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2420
2838cfdd 2421 num-lanes = <4>;
ec142c44 2422
2838cfdd
TR		 2423 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2424 clock-names = "core";
ec142c44 2425
2838cfdd
TR		 2426 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2427 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2428 reset-names = "apb", "core";
ec142c44 2429
2838cfdd
TR		 2430 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2431 interrupt-names = "intr";
ec142c44 2432
2838cfdd 2433 nvidia,bpmp = <&bpmp 10>;
ec142c44 2434
2838cfdd
TR		 2435 nvidia,enable-ext-refclk;
2436 nvidia,aspm-cmrt-us = <60>;
2437 nvidia,aspm-pwr-on-t-us = <20>;
2438 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2439
2838cfdd
TR		 2440 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2441 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2442 interconnect-names = "dma-mem", "write";
2443 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2444 iommu-map-mask = <0x0>;
2445 dma-coherent;
ec142c44 2446
2838cfdd
TR		 2447 status = "disabled";
2448 };
ec142c44 2449
2838cfdd
TR		 2450 pcie@14100000 {
2451 compatible = "nvidia,tegra234-pcie";
2452 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2453 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2454 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2455 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2456 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
2457 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
2458 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2459
2838cfdd
TR		 2460 #address-cells = <3>;
2461 #size-cells = <2>;
2462 device_type = "pci";
2463 num-lanes = <1>;
2464 num-viewport = <8>;
2465 linux,pci-domain = <1>;
ec142c44 2466
2838cfdd
TR		 2467 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2468 clock-names = "core";
ec142c44 2469
2838cfdd
TR		 2470 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2471 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2472 reset-names = "apb", "core";
ec142c44 2473
2838cfdd
TR		 2474 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2475 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2476 interrupt-names = "intr", "msi";
ec142c44 2477
2838cfdd
TR		 2478 #interrupt-cells = <1>;
2479 interrupt-map-mask = <0 0 0 0>;
2480 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2481
2838cfdd 2482 nvidia,bpmp = <&bpmp 1>;
ec142c44 2483
2838cfdd
TR		 2484 nvidia,aspm-cmrt-us = <60>;
2485 nvidia,aspm-pwr-on-t-us = <20>;
2486 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2487
2838cfdd 2488 bus-range = <0x0 0xff>;
ec142c44 2489
2838cfdd
TR		 2490 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2491 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2492 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2493
2838cfdd
TR		 2494 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
2495 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
2496 interconnect-names = "dma-mem", "write";
2497 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2498 iommu-map-mask = <0x0>;
2499 dma-coherent;
ec142c44 2500
2838cfdd
TR		 2501 status = "disabled";
2502 };
ec142c44 2503
2838cfdd
TR		 2504 pcie@14120000 {
2505 compatible = "nvidia,tegra234-pcie";
2506 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2507 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2508 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2509 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2510 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
2511 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
2512 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2513
2838cfdd
TR		 2514 #address-cells = <3>;
2515 #size-cells = <2>;
2516 device_type = "pci";
2517 num-lanes = <1>;
2518 num-viewport = <8>;
2519 linux,pci-domain = <2>;
ec142c44 2520
2838cfdd
TR		 2521 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2522 clock-names = "core";
ec142c44 2523
2838cfdd
TR		 2524 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2525 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2526 reset-names = "apb", "core";
ec142c44 2527
2838cfdd
TR		 2528 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2529 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2530 interrupt-names = "intr", "msi";
ec142c44 2531
2838cfdd
TR		 2532 #interrupt-cells = <1>;
2533 interrupt-map-mask = <0 0 0 0>;
2534 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2535
2838cfdd 2536 nvidia,bpmp = <&bpmp 2>;
ec142c44 2537
2838cfdd
TR		 2538 nvidia,aspm-cmrt-us = <60>;
2539 nvidia,aspm-pwr-on-t-us = <20>;
2540 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2541
2838cfdd 2542 bus-range = <0x0 0xff>;
ec142c44 2543
2838cfdd
TR		 2544 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2545 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2546 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2547
2838cfdd
TR		 2548 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
2549 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
2550 interconnect-names = "dma-mem", "write";
2551 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2552 iommu-map-mask = <0x0>;
2553 dma-coherent;
ec142c44 2554
2838cfdd
TR		 2555 status = "disabled";
2556 };
ec142c44 2557
2838cfdd
TR		 2558 pcie@14140000 {
2559 compatible = "nvidia,tegra234-pcie";
2560 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2561 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2562 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2563 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2564 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
2565 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2566 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2567
2838cfdd
TR		 2568 #address-cells = <3>;
2569 #size-cells = <2>;
2570 device_type = "pci";
2571 num-lanes = <1>;
2572 num-viewport = <8>;
2573 linux,pci-domain = <3>;
ec142c44 2574
2838cfdd
TR		 2575 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2576 clock-names = "core";
ec142c44 2577
2838cfdd
TR		 2578 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2579 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2580 reset-names = "apb", "core";
ec142c44 2581
2838cfdd
TR		 2582 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2583 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2584 interrupt-names = "intr", "msi";
ec142c44 2585
2838cfdd
TR		 2586 #interrupt-cells = <1>;
2587 interrupt-map-mask = <0 0 0 0>;
2588 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2589
2838cfdd 2590 nvidia,bpmp = <&bpmp 3>;
ec142c44 2591
2838cfdd
TR		 2592 nvidia,aspm-cmrt-us = <60>;
2593 nvidia,aspm-pwr-on-t-us = <20>;
2594 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2595
2838cfdd 2596 bus-range = <0x0 0xff>;
ec142c44 2597
2838cfdd
TR		 2598 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2599 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2600 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2601
2838cfdd
TR		 2602 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
2603 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
2604 interconnect-names = "dma-mem", "write";
2605 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2606 iommu-map-mask = <0x0>;
2607 dma-coherent;
ec142c44 2608
2838cfdd
TR		 2609 status = "disabled";
2610 };
ec142c44 2611
2838cfdd
TR		 2612 pcie@14160000 {
2613 compatible = "nvidia,tegra234-pcie";
2614 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2615 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2616 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2617 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2618 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2619 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2620 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2621
2838cfdd
TR		 2622 #address-cells = <3>;
2623 #size-cells = <2>;
2624 device_type = "pci";
2625 num-lanes = <4>;
2626 num-viewport = <8>;
2627 linux,pci-domain = <4>;
ec142c44 2628
2838cfdd
TR		 2629 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2630 clock-names = "core";
ec142c44 2631
2838cfdd
TR		 2632 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2633 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2634 reset-names = "apb", "core";
ec142c44 2635
2838cfdd
TR		 2636 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2637 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2638 interrupt-names = "intr", "msi";
ec142c44 2639
2838cfdd
TR		 2640 #interrupt-cells = <1>;
2641 interrupt-map-mask = <0 0 0 0>;
2642 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2643
2838cfdd 2644 nvidia,bpmp = <&bpmp 4>;
ec142c44 2645
2838cfdd
TR		 2646 nvidia,aspm-cmrt-us = <60>;
2647 nvidia,aspm-pwr-on-t-us = <20>;
2648 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2649
2838cfdd 2650 bus-range = <0x0 0xff>;
ec142c44 2651
2838cfdd
TR		 2652 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2653 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2654 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2655
2838cfdd
TR		 2656 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
2657 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
2658 interconnect-names = "dma-mem", "write";
2659 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2660 iommu-map-mask = <0x0>;
2661 dma-coherent;
2662
2663 status = "disabled";
2664 };
ec142c44 2665
2838cfdd
TR		 2666 pcie@14180000 {
2667 compatible = "nvidia,tegra234-pcie";
2668 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2669 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2670 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2671 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2672 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2673 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2674 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2675
2838cfdd
TR		 2676 #address-cells = <3>;
2677 #size-cells = <2>;
2678 device_type = "pci";
2679 num-lanes = <4>;
2680 num-viewport = <8>;
2681 linux,pci-domain = <0>;
ec142c44 2682
2838cfdd
TR		 2683 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2684 clock-names = "core";
ec142c44 2685
2838cfdd
TR		 2686 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2687 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2688 reset-names = "apb", "core";
ec142c44 2689
2838cfdd
TR		 2690 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2691 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2692 interrupt-names = "intr", "msi";
ec142c44 2693
2838cfdd
TR		 2694 #interrupt-cells = <1>;
2695 interrupt-map-mask = <0 0 0 0>;
2696 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2697
2838cfdd 2698 nvidia,bpmp = <&bpmp 0>;
ec142c44 2699
2838cfdd
TR		 2700 nvidia,aspm-cmrt-us = <60>;
2701 nvidia,aspm-pwr-on-t-us = <20>;
2702 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2703
2838cfdd 2704 bus-range = <0x0 0xff>;
ec142c44 2705
2838cfdd
TR		 2706 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2707 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2708 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2709
2838cfdd
TR		 2710 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
2711 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
2712 interconnect-names = "dma-mem", "write";
2713 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2714 iommu-map-mask = <0x0>;
2715 dma-coherent;
2716
2717 status = "disabled";
2718 };
ec142c44 2719
2838cfdd
TR		 2720 pcie@141a0000 {
2721 compatible = "nvidia,tegra234-pcie";
2722 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2723 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2724 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2725 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2726 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2727 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2728 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2729
2838cfdd
TR		 2730 #address-cells = <3>;
2731 #size-cells = <2>;
2732 device_type = "pci";
2733 num-lanes = <8>;
2734 num-viewport = <8>;
2735 linux,pci-domain = <5>;
ec142c44 2736
2838cfdd
TR		 2737 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2738 clock-names = "core";
ec142c44 2739
2838cfdd
TR		 2740 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2741 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2742 reset-names = "apb", "core";
ec142c44 2743
2838cfdd
TR		 2744 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2745 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2746 interrupt-names = "intr", "msi";
ec142c44 2747
2838cfdd
TR		 2748 #interrupt-cells = <1>;
2749 interrupt-map-mask = <0 0 0 0>;
2750 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2751
2838cfdd 2752 nvidia,bpmp = <&bpmp 5>;
ec142c44 2753
2838cfdd
TR		 2754 nvidia,aspm-cmrt-us = <60>;
2755 nvidia,aspm-pwr-on-t-us = <20>;
2756 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2757
2838cfdd 2758 bus-range = <0x0 0xff>;
ec142c44 2759
2838cfdd
TR		 2760 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
2761 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2762 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2763
2838cfdd
TR		 2764 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2765 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2766 interconnect-names = "dma-mem", "write";
2767 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2768 iommu-map-mask = <0x0>;
2769 dma-coherent;
2770
2771 status = "disabled";
2772 };
ec142c44 2773
2838cfdd
TR		 2774 pcie-ep@141a0000 {
2775 compatible = "nvidia,tegra234-pcie-ep";
2776 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2777 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2778 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2779 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2780 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2781 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2782
2838cfdd 2783 num-lanes = <8>;
ec142c44 2784
2838cfdd
TR		 2785 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2786 clock-names = "core";
ec142c44 2787
2838cfdd
TR		 2788 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2789 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2790 reset-names = "apb", "core";
ec142c44 2791
2838cfdd
TR		 2792 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2793 interrupt-names = "intr";
ec142c44 2794
2838cfdd 2795 nvidia,bpmp = <&bpmp 5>;
ec142c44 2796
2838cfdd
TR		 2797 nvidia,enable-ext-refclk;
2798 nvidia,aspm-cmrt-us = <60>;
2799 nvidia,aspm-pwr-on-t-us = <20>;
2800 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2801
2838cfdd
TR		 2802 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2803 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2804 interconnect-names = "dma-mem", "write";
2805 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2806 iommu-map-mask = <0x0>;
2807 dma-coherent;
ec142c44 2808
2838cfdd
TR		 2809 status = "disabled";
2810 };
ec142c44 2811
2838cfdd
TR		 2812 pcie@141c0000 {
2813 compatible = "nvidia,tegra234-pcie";
2814 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2815 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2816 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2817 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2818 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2819 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2820 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2821
2838cfdd
TR		 2822 #address-cells = <3>;
2823 #size-cells = <2>;
2824 device_type = "pci";
2825 num-lanes = <4>;
2826 num-viewport = <8>;
2827 linux,pci-domain = <6>;
ec142c44 2828
2838cfdd
TR		 2829 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2830 clock-names = "core";
ec142c44 2831
2838cfdd
TR		 2832 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2833 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2834 reset-names = "apb", "core";
ec142c44 2835
2838cfdd
TR		 2836 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2837 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2838 interrupt-names = "intr", "msi";
ec142c44 2839
2838cfdd
TR		 2840 #interrupt-cells = <1>;
2841 interrupt-map-mask = <0 0 0 0>;
2842 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2843
2838cfdd 2844 nvidia,bpmp = <&bpmp 6>;
ec142c44 2845
2838cfdd
TR		 2846 nvidia,aspm-cmrt-us = <60>;
2847 nvidia,aspm-pwr-on-t-us = <20>;
2848 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2849
2838cfdd 2850 bus-range = <0x0 0xff>;
ec142c44 2851
2838cfdd
TR		 2852 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2853 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2854 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2855
2838cfdd
TR		 2856 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2857 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2858 interconnect-names = "dma-mem", "write";
2859 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2860 iommu-map-mask = <0x0>;
2861 dma-coherent;
2862
2863 status = "disabled";
2864 };
ec142c44 2865
2838cfdd
TR		 2866 pcie-ep@141c0000 {
2867 compatible = "nvidia,tegra234-pcie-ep";
2868 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2869 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2870 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2871 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
2872 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2873 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2874
2838cfdd 2875 num-lanes = <4>;
ec142c44 2876
2838cfdd
TR		 2877 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2878 clock-names = "core";
ec142c44 2879
2838cfdd
TR		 2880 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2881 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2882 reset-names = "apb", "core";
ec142c44 2883
2838cfdd
TR		 2884 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2885 interrupt-names = "intr";
ec142c44 2886
2838cfdd 2887 nvidia,bpmp = <&bpmp 6>;
ec142c44 2888
2838cfdd
TR		 2889 nvidia,enable-ext-refclk;
2890 nvidia,aspm-cmrt-us = <60>;
2891 nvidia,aspm-pwr-on-t-us = <20>;
2892 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2893
2838cfdd
TR		 2894 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2895 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2896 interconnect-names = "dma-mem", "write";
2897 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2898 iommu-map-mask = <0x0>;
2899 dma-coherent;
ec142c44 2900
2838cfdd
TR		 2901 status = "disabled";
2902 };
ec142c44 2903
2838cfdd
TR		 2904 pcie@141e0000 {
2905 compatible = "nvidia,tegra234-pcie";
2906 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2907 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2908 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2909 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2910 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2911 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2912 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2913
2838cfdd
TR		 2914 #address-cells = <3>;
2915 #size-cells = <2>;
2916 device_type = "pci";
2917 num-lanes = <8>;
2918 num-viewport = <8>;
2919 linux,pci-domain = <7>;
ec142c44 2920
2838cfdd
TR		 2921 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2922 clock-names = "core";
ec142c44 2923
2838cfdd
TR		 2924 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2925 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2926 reset-names = "apb", "core";
ec142c44 2927
2838cfdd
TR		 2928 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2929 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2930 interrupt-names = "intr", "msi";
ec142c44 2931
2838cfdd
TR		 2932 #interrupt-cells = <1>;
2933 interrupt-map-mask = <0 0 0 0>;
2934 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2935
2838cfdd 2936 nvidia,bpmp = <&bpmp 7>;
ec142c44 2937
2838cfdd
TR		 2938 nvidia,aspm-cmrt-us = <60>;
2939 nvidia,aspm-pwr-on-t-us = <20>;
2940 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2941
2838cfdd 2942 bus-range = <0x0 0xff>;
ec142c44 2943
2838cfdd
TR		 2944 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
2945 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2946 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2947
2838cfdd
TR		 2948 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2949 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2950 interconnect-names = "dma-mem", "write";
2951 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2952 iommu-map-mask = <0x0>;
2953 dma-coherent;
2954
2955 status = "disabled";
2956 };
2957
2958 pcie-ep@141e0000 {
2959 compatible = "nvidia,tegra234-pcie-ep";
2960 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2961 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2962 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2963 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
2964 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2965 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2966
2967 num-lanes = <8>;
2968
2969 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2970 clock-names = "core";
ec142c44 2971
2838cfdd
TR		 2972 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2973 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2974 reset-names = "apb", "core";
ec142c44 2975
2838cfdd
TR		 2976 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2977 interrupt-names = "intr";
ec142c44 2978
2838cfdd 2979 nvidia,bpmp = <&bpmp 7>;
ec142c44 2980
2838cfdd
TR		 2981 nvidia,enable-ext-refclk;
2982 nvidia,aspm-cmrt-us = <60>;
2983 nvidia,aspm-pwr-on-t-us = <20>;
2984 nvidia,aspm-l0s-entrance-latency-us = <3>;
2985
2986 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2987 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2988 interconnect-names = "dma-mem", "write";
2989 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2990 iommu-map-mask = <0x0>;
2991 dma-coherent;
2992
2993 status = "disabled";
2994 };
ec142c44
VS		 2995 };
2996
7fa30752 2997 sram@40000000 {
63944891 2998 compatible = "nvidia,tegra234-sysram", "mmio-sram";
98094be1 2999 reg = <0x0 0x40000000 0x0 0x80000>;
2838cfdd 3000
63944891
TR		 3001 #address-cells = <1>;
3002 #size-cells = <1>;
98094be1 3003 ranges = <0x0 0x0 0x40000000 0x80000>;
2838cfdd 3004
61192a9d 3005 no-memory-wc;
63944891 3006
98094be1
MP		 3007 cpu_bpmp_tx: sram@70000 {
3008 reg = <0x70000 0x1000>;
63944891
TR		 3009 label = "cpu-bpmp-tx";
3010 pool;
3011 };
3012
98094be1
MP		 3013 cpu_bpmp_rx: sram@71000 {
3014 reg = <0x71000 0x1000>;
63944891
TR		 3015 label = "cpu-bpmp-rx";
3016 pool;
3017 };
3018 };
3019
3020 bpmp: bpmp {
3021 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
3022 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
3023 TEGRA_HSP_DB_MASTER_BPMP>;
7fa30752 3024 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
63944891
TR		 3025 #clock-cells = <1>;
3026 #reset-cells = <1>;
3027 #power-domain-cells = <1>;
6de481e5
TR		 3028 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
3029 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
3030 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
3031 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
3032 interconnect-names = "read", "write", "dma-mem", "dma-write";
5710e16a 3033 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
63944891
TR		 3034
3035 bpmp_i2c: i2c {
3036 compatible = "nvidia,tegra186-bpmp-i2c";
3037 nvidia,bpmp-bus-id = <5>;
3038 #address-cells = <1>;
3039 #size-cells = <0>;
3040 };
09d99078
TR		 3041
3042 bpmp_thermal: thermal {
3043 compatible = "nvidia,tegra186-bpmp-thermal";
3044 #thermal-sensor-cells = <1>;
3045 };
63944891
TR		 3046 };
3047
3048 cpus {
3049 #address-cells = <1>;
3050 #size-cells = <0>;
3051
a12cf5c3
TR		 3052 cpu0_0: cpu@0 {
3053 compatible = "arm,cortex-a78";
63944891 3054 device_type = "cpu";
a12cf5c3 3055 reg = <0x00000>;
63944891
TR		 3056
3057 enable-method = "psci";
a12cf5c3 3058
1582e1d1
SG		 3059 operating-points-v2 = <&cl0_opp_tbl>;
3060 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
3061
a12cf5c3
TR		 3062 i-cache-size = <65536>;
3063 i-cache-line-size = <64>;
3064 i-cache-sets = <256>;
3065 d-cache-size = <65536>;
3066 d-cache-line-size = <64>;
3067 d-cache-sets = <256>;
3068 next-level-cache = <&l2c0_0>;
3069 };
3070
3071 cpu0_1: cpu@100 {
3072 compatible = "arm,cortex-a78";
3073 device_type = "cpu";
3074 reg = <0x00100>;
3075
3076 enable-method = "psci";
3077
1582e1d1
SG		 3078 operating-points-v2 = <&cl0_opp_tbl>;
3079 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
3080
a12cf5c3
TR		 3081 i-cache-size = <65536>;
3082 i-cache-line-size = <64>;
3083 i-cache-sets = <256>;
3084 d-cache-size = <65536>;
3085 d-cache-line-size = <64>;
3086 d-cache-sets = <256>;
3087 next-level-cache = <&l2c0_1>;
63944891 3088 };
a12cf5c3
TR		 3089
3090 cpu0_2: cpu@200 {
3091 compatible = "arm,cortex-a78";
3092 device_type = "cpu";
3093 reg = <0x00200>;
3094
3095 enable-method = "psci";
3096
1582e1d1
SG		 3097 operating-points-v2 = <&cl0_opp_tbl>;
3098 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
3099
a12cf5c3
TR		 3100 i-cache-size = <65536>;
3101 i-cache-line-size = <64>;
3102 i-cache-sets = <256>;
3103 d-cache-size = <65536>;
3104 d-cache-line-size = <64>;
3105 d-cache-sets = <256>;
3106 next-level-cache = <&l2c0_2>;
3107 };
3108
3109 cpu0_3: cpu@300 {
3110 compatible = "arm,cortex-a78";
3111 device_type = "cpu";
3112 reg = <0x00300>;
3113
3114 enable-method = "psci";
3115
1582e1d1
SG		 3116 operating-points-v2 = <&cl0_opp_tbl>;
3117 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
3118
a12cf5c3
TR		 3119 i-cache-size = <65536>;
3120 i-cache-line-size = <64>;
3121 i-cache-sets = <256>;
3122 d-cache-size = <65536>;
3123 d-cache-line-size = <64>;
3124 d-cache-sets = <256>;
3125 next-level-cache = <&l2c0_3>;
3126 };
3127
3128 cpu1_0: cpu@10000 {
3129 compatible = "arm,cortex-a78";
3130 device_type = "cpu";
3131 reg = <0x10000>;
3132
3133 enable-method = "psci";
3134
1582e1d1
SG		 3135 operating-points-v2 = <&cl1_opp_tbl>;
3136 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
3137
a12cf5c3
TR		 3138 i-cache-size = <65536>;
3139 i-cache-line-size = <64>;
3140 i-cache-sets = <256>;
3141 d-cache-size = <65536>;
3142 d-cache-line-size = <64>;
3143 d-cache-sets = <256>;
3144 next-level-cache = <&l2c1_0>;
3145 };
3146
3147 cpu1_1: cpu@10100 {
3148 compatible = "arm,cortex-a78";
3149 device_type = "cpu";
3150 reg = <0x10100>;
3151
3152 enable-method = "psci";
3153
1582e1d1
SG		 3154 operating-points-v2 = <&cl1_opp_tbl>;
3155 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
3156
a12cf5c3
TR		 3157 i-cache-size = <65536>;
3158 i-cache-line-size = <64>;
3159 i-cache-sets = <256>;
3160 d-cache-size = <65536>;
3161 d-cache-line-size = <64>;
3162 d-cache-sets = <256>;
3163 next-level-cache = <&l2c1_1>;
3164 };
3165
3166 cpu1_2: cpu@10200 {
3167 compatible = "arm,cortex-a78";
3168 device_type = "cpu";
3169 reg = <0x10200>;
3170
3171 enable-method = "psci";
3172
1582e1d1
SG		 3173 operating-points-v2 = <&cl1_opp_tbl>;
3174 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
3175
a12cf5c3
TR		 3176 i-cache-size = <65536>;
3177 i-cache-line-size = <64>;
3178 i-cache-sets = <256>;
3179 d-cache-size = <65536>;
3180 d-cache-line-size = <64>;
3181 d-cache-sets = <256>;
3182 next-level-cache = <&l2c1_2>;
3183 };
3184
3185 cpu1_3: cpu@10300 {
3186 compatible = "arm,cortex-a78";
3187 device_type = "cpu";
3188 reg = <0x10300>;
3189
3190 enable-method = "psci";
3191
1582e1d1
SG		 3192 operating-points-v2 = <&cl1_opp_tbl>;
3193 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
3194
a12cf5c3
TR		 3195 i-cache-size = <65536>;
3196 i-cache-line-size = <64>;
3197 i-cache-sets = <256>;
3198 d-cache-size = <65536>;
3199 d-cache-line-size = <64>;
3200 d-cache-sets = <256>;
3201 next-level-cache = <&l2c1_3>;
3202 };
3203
3204 cpu2_0: cpu@20000 {
3205 compatible = "arm,cortex-a78";
3206 device_type = "cpu";
3207 reg = <0x20000>;
3208
3209 enable-method = "psci";
3210
1582e1d1
SG		 3211 operating-points-v2 = <&cl2_opp_tbl>;
3212 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
3213
a12cf5c3
TR		 3214 i-cache-size = <65536>;
3215 i-cache-line-size = <64>;
3216 i-cache-sets = <256>;
3217 d-cache-size = <65536>;
3218 d-cache-line-size = <64>;
3219 d-cache-sets = <256>;
3220 next-level-cache = <&l2c2_0>;
3221 };
3222
3223 cpu2_1: cpu@20100 {
3224 compatible = "arm,cortex-a78";
3225 device_type = "cpu";
3226 reg = <0x20100>;
3227
3228 enable-method = "psci";
3229
1582e1d1
SG		 3230 operating-points-v2 = <&cl2_opp_tbl>;
3231 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
3232
a12cf5c3
TR		 3233 i-cache-size = <65536>;
3234 i-cache-line-size = <64>;
3235 i-cache-sets = <256>;
3236 d-cache-size = <65536>;
3237 d-cache-line-size = <64>;
3238 d-cache-sets = <256>;
3239 next-level-cache = <&l2c2_1>;
3240 };
3241
3242 cpu2_2: cpu@20200 {
3243 compatible = "arm,cortex-a78";
3244 device_type = "cpu";
3245 reg = <0x20200>;
3246
3247 enable-method = "psci";
3248
1582e1d1
SG		 3249 operating-points-v2 = <&cl2_opp_tbl>;
3250 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
3251
a12cf5c3
TR		 3252 i-cache-size = <65536>;
3253 i-cache-line-size = <64>;
3254 i-cache-sets = <256>;
3255 d-cache-size = <65536>;
3256 d-cache-line-size = <64>;
3257 d-cache-sets = <256>;
3258 next-level-cache = <&l2c2_2>;
3259 };
3260
3261 cpu2_3: cpu@20300 {
3262 compatible = "arm,cortex-a78";
3263 device_type = "cpu";
3264 reg = <0x20300>;
3265
3266 enable-method = "psci";
3267
1582e1d1
SG		 3268 operating-points-v2 = <&cl2_opp_tbl>;
3269 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
3270
a12cf5c3
TR		 3271 i-cache-size = <65536>;
3272 i-cache-line-size = <64>;
3273 i-cache-sets = <256>;
3274 d-cache-size = <65536>;
3275 d-cache-line-size = <64>;
3276 d-cache-sets = <256>;
3277 next-level-cache = <&l2c2_3>;
3278 };
3279
3280 cpu-map {
3281 cluster0 {
3282 core0 {
3283 cpu = <&cpu0_0>;
3284 };
3285
3286 core1 {
3287 cpu = <&cpu0_1>;
3288 };
3289
3290 core2 {
3291 cpu = <&cpu0_2>;
3292 };
3293
3294 core3 {
3295 cpu = <&cpu0_3>;
3296 };
3297 };
3298
3299 cluster1 {
3300 core0 {
3301 cpu = <&cpu1_0>;
3302 };
3303
3304 core1 {
3305 cpu = <&cpu1_1>;
3306 };
3307
3308 core2 {
3309 cpu = <&cpu1_2>;
3310 };
3311
3312 core3 {
3313 cpu = <&cpu1_3>;
3314 };
3315 };
3316
3317 cluster2 {
3318 core0 {
3319 cpu = <&cpu2_0>;
3320 };
3321
3322 core1 {
3323 cpu = <&cpu2_1>;
3324 };
3325
3326 core2 {
3327 cpu = <&cpu2_2>;
3328 };
3329
3330 core3 {
3331 cpu = <&cpu2_3>;
3332 };
3333 };
3334 };
3335
3336 l2c0_0: l2-cache00 {
27f1568b 3337 compatible = "cache";
a12cf5c3
TR		 3338 cache-size = <262144>;
3339 cache-line-size = <64>;
3340 cache-sets = <512>;
3341 cache-unified;
27f1568b 3342 cache-level = <2>;
a12cf5c3
TR		 3343 next-level-cache = <&l3c0>;
3344 };
3345
3346 l2c0_1: l2-cache01 {
27f1568b 3347 compatible = "cache";
a12cf5c3
TR		 3348 cache-size = <262144>;
3349 cache-line-size = <64>;
3350 cache-sets = <512>;
3351 cache-unified;
27f1568b 3352 cache-level = <2>;
a12cf5c3
TR		 3353 next-level-cache = <&l3c0>;
3354 };
3355
3356 l2c0_2: l2-cache02 {
27f1568b 3357 compatible = "cache";
a12cf5c3
TR		 3358 cache-size = <262144>;
3359 cache-line-size = <64>;
3360 cache-sets = <512>;
3361 cache-unified;
27f1568b 3362 cache-level = <2>;
a12cf5c3
TR		 3363 next-level-cache = <&l3c0>;
3364 };
3365
3366 l2c0_3: l2-cache03 {
27f1568b 3367 compatible = "cache";
a12cf5c3
TR		 3368 cache-size = <262144>;
3369 cache-line-size = <64>;
3370 cache-sets = <512>;
3371 cache-unified;
27f1568b 3372 cache-level = <2>;
a12cf5c3
TR		 3373 next-level-cache = <&l3c0>;
3374 };
3375
3376 l2c1_0: l2-cache10 {
27f1568b 3377 compatible = "cache";
a12cf5c3
TR		 3378 cache-size = <262144>;
3379 cache-line-size = <64>;
3380 cache-sets = <512>;
3381 cache-unified;
27f1568b 3382 cache-level = <2>;
a12cf5c3
TR		 3383 next-level-cache = <&l3c1>;
3384 };
3385
3386 l2c1_1: l2-cache11 {
27f1568b 3387 compatible = "cache";
a12cf5c3
TR		 3388 cache-size = <262144>;
3389 cache-line-size = <64>;
3390 cache-sets = <512>;
3391 cache-unified;
27f1568b 3392 cache-level = <2>;
a12cf5c3
TR		 3393 next-level-cache = <&l3c1>;
3394 };
3395
3396 l2c1_2: l2-cache12 {
27f1568b 3397 compatible = "cache";
a12cf5c3
TR		 3398 cache-size = <262144>;
3399 cache-line-size = <64>;
3400 cache-sets = <512>;
3401 cache-unified;
27f1568b 3402 cache-level = <2>;
a12cf5c3
TR		 3403 next-level-cache = <&l3c1>;
3404 };
3405
3406 l2c1_3: l2-cache13 {
27f1568b 3407 compatible = "cache";
a12cf5c3
TR		 3408 cache-size = <262144>;
3409 cache-line-size = <64>;
3410 cache-sets = <512>;
3411 cache-unified;
27f1568b 3412 cache-level = <2>;
a12cf5c3
TR		 3413 next-level-cache = <&l3c1>;
3414 };
3415
3416 l2c2_0: l2-cache20 {
27f1568b 3417 compatible = "cache";
a12cf5c3
TR		 3418 cache-size = <262144>;
3419 cache-line-size = <64>;
3420 cache-sets = <512>;
3421 cache-unified;
27f1568b 3422 cache-level = <2>;
a12cf5c3
TR		 3423 next-level-cache = <&l3c2>;
3424 };
3425
3426 l2c2_1: l2-cache21 {
27f1568b 3427 compatible = "cache";
a12cf5c3
TR		 3428 cache-size = <262144>;
3429 cache-line-size = <64>;
3430 cache-sets = <512>;
3431 cache-unified;
27f1568b 3432 cache-level = <2>;
a12cf5c3
TR		 3433 next-level-cache = <&l3c2>;
3434 };
3435
3436 l2c2_2: l2-cache22 {
27f1568b 3437 compatible = "cache";
a12cf5c3
TR		 3438 cache-size = <262144>;
3439 cache-line-size = <64>;
3440 cache-sets = <512>;
3441 cache-unified;
27f1568b 3442 cache-level = <2>;
a12cf5c3
TR		 3443 next-level-cache = <&l3c2>;
3444 };
3445
3446 l2c2_3: l2-cache23 {
27f1568b 3447 compatible = "cache";
a12cf5c3
TR		 3448 cache-size = <262144>;
3449 cache-line-size = <64>;
3450 cache-sets = <512>;
3451 cache-unified;
27f1568b 3452 cache-level = <2>;
a12cf5c3
TR		 3453 next-level-cache = <&l3c2>;
3454 };
3455
3456 l3c0: l3-cache0 {
27f1568b
PG		 3457 compatible = "cache";
3458 cache-unified;
a12cf5c3
TR		 3459 cache-size = <2097152>;
3460 cache-line-size = <64>;
3461 cache-sets = <2048>;
27f1568b 3462 cache-level = <3>;
a12cf5c3
TR		 3463 };
3464
3465 l3c1: l3-cache1 {
27f1568b
PG		 3466 compatible = "cache";
3467 cache-unified;
a12cf5c3
TR		 3468 cache-size = <2097152>;
3469 cache-line-size = <64>;
3470 cache-sets = <2048>;
27f1568b 3471 cache-level = <3>;
a12cf5c3
TR		 3472 };
3473
3474 l3c2: l3-cache2 {
27f1568b
PG		 3475 compatible = "cache";
3476 cache-unified;
a12cf5c3
TR		 3477 cache-size = <2097152>;
3478 cache-line-size = <64>;
3479 cache-sets = <2048>;
27f1568b 3480 cache-level = <3>;
a12cf5c3
TR		 3481 };
3482 };
3483
8e0ae0fb
JH		 3484 dsu-pmu0 {
3485 compatible = "arm,dsu-pmu";
3486 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
3487 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>;
3488 };
3489
3490 dsu-pmu1 {
3491 compatible = "arm,dsu-pmu";
3492 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
3493 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>;
3494 };
3495
3496 dsu-pmu2 {
3497 compatible = "arm,dsu-pmu";
3498 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
3499 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>;
3500 };
3501
a12cf5c3
TR		 3502 pmu {
3503 compatible = "arm,cortex-a78-pmu";
3504 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
3505 status = "okay";
63944891
TR		 3506 };
3507
3508 psci {
3509 compatible = "arm,psci-1.0";
3510 status = "okay";
3511 method = "smc";
3512 };
3513
06ad2ec4
MP		 3514 tcu: serial {
3515 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3516 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3517 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3518 mbox-names = "rx", "tx";
3519 status = "disabled";
3520 };
3521
09614acd
SP		 3522 sound {
3523 status = "disabled";
3524
3525 clocks = <&bpmp TEGRA234_CLK_PLLA>,
3526 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3527 clock-names = "pll_a", "plla_out0";
3528 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3529 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3530 <&bpmp TEGRA234_CLK_AUD_MCLK>;
3531 assigned-clock-parents = <0>,
3532 <&bpmp TEGRA234_CLK_PLLA>,
3533 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3534 };
3535
09d99078
TR		 3536 thermal-zones {
3537 cpu-thermal {
3538 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
3539 status = "disabled";
3540 };
3541
3542 gpu-thermal {
3543 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
3544 status = "disabled";
3545 };
3546
3547 cv0-thermal {
3548 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
3549 status = "disabled";
3550 };
3551
3552 cv1-thermal {
3553 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
3554 status = "disabled";
3555 };
3556
3557 cv2-thermal {
3558 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
3559 status = "disabled";
3560 };
3561
3562 soc0-thermal {
3563 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
3564 status = "disabled";
3565 };
3566
3567 soc1-thermal {
3568 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
3569 status = "disabled";
3570 };
3571
3572 soc2-thermal {
3573 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
3574 status = "disabled";
3575 };
3576
3577 tj-thermal {
3578 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
3579 status = "disabled";
3580 };
3581 };
3582
63944891
TR		 3583 timer {
3584 compatible = "arm,armv8-timer";
3585 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3586 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3587 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3588 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3589 interrupt-parent = <&gic>;
3590 always-on;
3591 };
1582e1d1
SG		 3592
3593 cl0_opp_tbl: opp-table-cluster0 {
3594 compatible = "operating-points-v2";
3595 opp-shared;
3596
3597 cl0_ch1_opp1: opp-115200000 {
3598 opp-hz = /bits/ 64 <115200000>;
3599 opp-peak-kBps = <816000>;
3600 };
3601
20515700
SG		 3602 cl0_ch1_opp2: opp-192000000 {
3603 opp-hz = /bits/ 64 <192000000>;
3604 opp-peak-kBps = <816000>;
3605 };
3606
3607 cl0_ch1_opp3: opp-268800000 {
1582e1d1
SG		 3608 opp-hz = /bits/ 64 <268800000>;
3609 opp-peak-kBps = <816000>;
3610 };
3611
20515700
SG		 3612 cl0_ch1_opp4: opp-345600000 {
3613 opp-hz = /bits/ 64 <345600000>;
3614 opp-peak-kBps = <816000>;
3615 };
3616
3617 cl0_ch1_opp5: opp-422400000 {
1582e1d1
SG		 3618 opp-hz = /bits/ 64 <422400000>;
3619 opp-peak-kBps = <816000>;
3620 };
3621
20515700
SG		 3622 cl0_ch1_opp6: opp-499200000 {
3623 opp-hz = /bits/ 64 <499200000>;
3624 opp-peak-kBps = <816000>;
3625 };
3626
3627 cl0_ch1_opp7: opp-576000000 {
1582e1d1
SG		 3628 opp-hz = /bits/ 64 <576000000>;
3629 opp-peak-kBps = <816000>;
3630 };
3631
20515700
SG		 3632 cl0_ch1_opp8: opp-652800000 {
3633 opp-hz = /bits/ 64 <652800000>;
3634 opp-peak-kBps = <816000>;
3635 };
3636
3637 cl0_ch1_opp9: opp-729600000 {
1582e1d1
SG		 3638 opp-hz = /bits/ 64 <729600000>;
3639 opp-peak-kBps = <816000>;
3640 };
3641
20515700
SG		 3642 cl0_ch1_opp10: opp-806400000 {
3643 opp-hz = /bits/ 64 <806400000>;
3644 opp-peak-kBps = <816000>;
3645 };
3646
3647 cl0_ch1_opp11: opp-883200000 {
1582e1d1
SG		 3648 opp-hz = /bits/ 64 <883200000>;
3649 opp-peak-kBps = <816000>;
3650 };
3651
20515700
SG		 3652 cl0_ch1_opp12: opp-960000000 {
3653 opp-hz = /bits/ 64 <960000000>;
3654 opp-peak-kBps = <816000>;
3655 };
3656
3657 cl0_ch1_opp13: opp-1036800000 {
1582e1d1
SG		 3658 opp-hz = /bits/ 64 <1036800000>;
3659 opp-peak-kBps = <816000>;
3660 };
3661
20515700
SG		 3662 cl0_ch1_opp14: opp-1113600000 {
3663 opp-hz = /bits/ 64 <1113600000>;
3664 opp-peak-kBps = <1632000>;
3665 };
3666
3667 cl0_ch1_opp15: opp-1190400000 {
1582e1d1 3668 opp-hz = /bits/ 64 <1190400000>;
20515700 3669 opp-peak-kBps = <1632000>;
1582e1d1
SG		 3670 };
3671
20515700
SG		 3672 cl0_ch1_opp16: opp-1267200000 {
3673 opp-hz = /bits/ 64 <1267200000>;
3674 opp-peak-kBps = <1632000>;
3675 };
3676
3677 cl0_ch1_opp17: opp-1344000000 {
1582e1d1
SG		 3678 opp-hz = /bits/ 64 <1344000000>;
3679 opp-peak-kBps = <1632000>;
3680 };
3681
20515700
SG		 3682 cl0_ch1_opp18: opp-1420800000 {
3683 opp-hz = /bits/ 64 <1420800000>;
1582e1d1
SG		 3684 opp-peak-kBps = <1632000>;
3685 };
3686
20515700
SG		 3687 cl0_ch1_opp19: opp-1497600000 {
3688 opp-hz = /bits/ 64 <1497600000>;
3689 opp-peak-kBps = <3200000>;
3690 };
3691
3692 cl0_ch1_opp20: opp-1574400000 {
3693 opp-hz = /bits/ 64 <1574400000>;
3694 opp-peak-kBps = <3200000>;
3695 };
3696
3697 cl0_ch1_opp21: opp-1651200000 {
1582e1d1 3698 opp-hz = /bits/ 64 <1651200000>;
20515700
SG		 3699 opp-peak-kBps = <3200000>;
3700 };
3701
3702 cl0_ch1_opp22: opp-1728000000 {
3703 opp-hz = /bits/ 64 <1728000000>;
3704 opp-peak-kBps = <3200000>;
1582e1d1
SG		 3705 };
3706
20515700 3707 cl0_ch1_opp23: opp-1804800000 {
1582e1d1 3708 opp-hz = /bits/ 64 <1804800000>;
20515700 3709 opp-peak-kBps = <3200000>;
1582e1d1
SG		 3710 };
3711
20515700
SG		 3712 cl0_ch1_opp24: opp-1881600000 {
3713 opp-hz = /bits/ 64 <1881600000>;
3714 opp-peak-kBps = <3200000>;
3715 };
3716
3717 cl0_ch1_opp25: opp-1958400000 {
1582e1d1
SG		 3718 opp-hz = /bits/ 64 <1958400000>;
3719 opp-peak-kBps = <3200000>;
3720 };
3721
20515700
SG		 3722 cl0_ch1_opp26: opp-2035200000 {
3723 opp-hz = /bits/ 64 <2035200000>;
3724 opp-peak-kBps = <3200000>;
3725 };
3726
3727 cl0_ch1_opp27: opp-2112000000 {
1582e1d1
SG		 3728 opp-hz = /bits/ 64 <2112000000>;
3729 opp-peak-kBps = <6400000>;
3730 };
3731
20515700
SG		 3732 cl0_ch1_opp28: opp-2188800000 {
3733 opp-hz = /bits/ 64 <2188800000>;
3734 opp-peak-kBps = <6400000>;
3735 };
3736
3737 cl0_ch1_opp29: opp-2201600000 {
1582e1d1
SG		 3738 opp-hz = /bits/ 64 <2201600000>;
3739 opp-peak-kBps = <6400000>;
3740 };
3741 };
3742
3743 cl1_opp_tbl: opp-table-cluster1 {
3744 compatible = "operating-points-v2";
3745 opp-shared;
3746
3747 cl1_ch1_opp1: opp-115200000 {
3748 opp-hz = /bits/ 64 <115200000>;
3749 opp-peak-kBps = <816000>;
3750 };
3751
20515700
SG		 3752 cl1_ch1_opp2: opp-192000000 {
3753 opp-hz = /bits/ 64 <192000000>;
3754 opp-peak-kBps = <816000>;
3755 };
3756
3757 cl1_ch1_opp3: opp-268800000 {
1582e1d1
SG		 3758 opp-hz = /bits/ 64 <268800000>;
3759 opp-peak-kBps = <816000>;
3760 };
3761
20515700
SG		 3762 cl1_ch1_opp4: opp-345600000 {
3763 opp-hz = /bits/ 64 <345600000>;
3764 opp-peak-kBps = <816000>;
3765 };
3766
3767 cl1_ch1_opp5: opp-422400000 {
1582e1d1
SG		 3768 opp-hz = /bits/ 64 <422400000>;
3769 opp-peak-kBps = <816000>;
3770 };
3771
20515700
SG		 3772 cl1_ch1_opp6: opp-499200000 {
3773 opp-hz = /bits/ 64 <499200000>;
3774 opp-peak-kBps = <816000>;
3775 };
3776
3777 cl1_ch1_opp7: opp-576000000 {
1582e1d1
SG		 3778 opp-hz = /bits/ 64 <576000000>;
3779 opp-peak-kBps = <816000>;
3780 };
3781
20515700
SG		 3782 cl1_ch1_opp8: opp-652800000 {
3783 opp-hz = /bits/ 64 <652800000>;
3784 opp-peak-kBps = <816000>;
3785 };
3786
3787 cl1_ch1_opp9: opp-729600000 {
1582e1d1
SG		 3788 opp-hz = /bits/ 64 <729600000>;
3789 opp-peak-kBps = <816000>;
3790 };
3791
20515700
SG		 3792 cl1_ch1_opp10: opp-806400000 {
3793 opp-hz = /bits/ 64 <806400000>;
3794 opp-peak-kBps = <816000>;
3795 };
3796
3797 cl1_ch1_opp11: opp-883200000 {
1582e1d1
SG		 3798 opp-hz = /bits/ 64 <883200000>;
3799 opp-peak-kBps = <816000>;
3800 };
3801
20515700
SG		 3802 cl1_ch1_opp12: opp-960000000 {
3803 opp-hz = /bits/ 64 <960000000>;
3804 opp-peak-kBps = <816000>;
3805 };
3806
3807 cl1_ch1_opp13: opp-1036800000 {
1582e1d1
SG		 3808 opp-hz = /bits/ 64 <1036800000>;
3809 opp-peak-kBps = <816000>;
3810 };
3811
20515700
SG		 3812 cl1_ch1_opp14: opp-1113600000 {
3813 opp-hz = /bits/ 64 <1113600000>;
3814 opp-peak-kBps = <1632000>;
3815 };
3816
3817 cl1_ch1_opp15: opp-1190400000 {
1582e1d1 3818 opp-hz = /bits/ 64 <1190400000>;
20515700
SG		 3819 opp-peak-kBps = <1632000>;
3820 };
3821
3822 cl1_ch1_opp16: opp-1267200000 {
3823 opp-hz = /bits/ 64 <1267200000>;
3824 opp-peak-kBps = <1632000>;
1582e1d1
SG		 3825 };
3826
20515700 3827 cl1_ch1_opp17: opp-1344000000 {
1582e1d1
SG		 3828 opp-hz = /bits/ 64 <1344000000>;
3829 opp-peak-kBps = <1632000>;
3830 };
3831
20515700
SG		 3832 cl1_ch1_opp18: opp-1420800000 {
3833 opp-hz = /bits/ 64 <1420800000>;
1582e1d1
SG		 3834 opp-peak-kBps = <1632000>;
3835 };
3836
20515700
SG		 3837 cl1_ch1_opp19: opp-1497600000 {
3838 opp-hz = /bits/ 64 <1497600000>;
3839 opp-peak-kBps = <3200000>;
3840 };
3841
3842 cl1_ch1_opp20: opp-1574400000 {
3843 opp-hz = /bits/ 64 <1574400000>;
3844 opp-peak-kBps = <3200000>;
3845 };
3846
3847 cl1_ch1_opp21: opp-1651200000 {
1582e1d1 3848 opp-hz = /bits/ 64 <1651200000>;
20515700
SG		 3849 opp-peak-kBps = <3200000>;
3850 };
3851
3852 cl1_ch1_opp22: opp-1728000000 {
3853 opp-hz = /bits/ 64 <1728000000>;
3854 opp-peak-kBps = <3200000>;
1582e1d1
SG		 3855 };
3856
20515700 3857 cl1_ch1_opp23: opp-1804800000 {
1582e1d1 3858 opp-hz = /bits/ 64 <1804800000>;
20515700
SG		 3859 opp-peak-kBps = <3200000>;
3860 };
3861
3862 cl1_ch1_opp24: opp-1881600000 {
3863 opp-hz = /bits/ 64 <1881600000>;
3864 opp-peak-kBps = <3200000>;
1582e1d1
SG		 3865 };
3866
20515700 3867 cl1_ch1_opp25: opp-1958400000 {
1582e1d1
SG		 3868 opp-hz = /bits/ 64 <1958400000>;
3869 opp-peak-kBps = <3200000>;
3870 };
3871
20515700
SG		 3872 cl1_ch1_opp26: opp-2035200000 {
3873 opp-hz = /bits/ 64 <2035200000>;
3874 opp-peak-kBps = <3200000>;
3875 };
3876
3877 cl1_ch1_opp27: opp-2112000000 {
1582e1d1
SG		 3878 opp-hz = /bits/ 64 <2112000000>;
3879 opp-peak-kBps = <6400000>;
3880 };
3881
20515700
SG		 3882 cl1_ch1_opp28: opp-2188800000 {
3883 opp-hz = /bits/ 64 <2188800000>;
3884 opp-peak-kBps = <6400000>;
3885 };
3886
3887 cl1_ch1_opp29: opp-2201600000 {
1582e1d1
SG		 3888 opp-hz = /bits/ 64 <2201600000>;
3889 opp-peak-kBps = <6400000>;
3890 };
3891 };
3892
3893 cl2_opp_tbl: opp-table-cluster2 {
3894 compatible = "operating-points-v2";
3895 opp-shared;
3896
3897 cl2_ch1_opp1: opp-115200000 {
3898 opp-hz = /bits/ 64 <115200000>;
3899 opp-peak-kBps = <816000>;
3900 };
3901
20515700
SG		 3902 cl2_ch1_opp2: opp-192000000 {
3903 opp-hz = /bits/ 64 <192000000>;
3904 opp-peak-kBps = <816000>;
3905 };
3906
3907 cl2_ch1_opp3: opp-268800000 {
1582e1d1
SG		 3908 opp-hz = /bits/ 64 <268800000>;
3909 opp-peak-kBps = <816000>;
3910 };
3911
20515700
SG		 3912 cl2_ch1_opp4: opp-345600000 {
3913 opp-hz = /bits/ 64 <345600000>;
3914 opp-peak-kBps = <816000>;
3915 };
3916
3917 cl2_ch1_opp5: opp-422400000 {
1582e1d1
SG		 3918 opp-hz = /bits/ 64 <422400000>;
3919 opp-peak-kBps = <816000>;
3920 };
3921
20515700
SG		 3922 cl2_ch1_opp6: opp-499200000 {
3923 opp-hz = /bits/ 64 <499200000>;
3924 opp-peak-kBps = <816000>;
3925 };
3926
3927 cl2_ch1_opp7: opp-576000000 {
1582e1d1
SG		 3928 opp-hz = /bits/ 64 <576000000>;
3929 opp-peak-kBps = <816000>;
3930 };
3931
20515700
SG		 3932 cl2_ch1_opp8: opp-652800000 {
3933 opp-hz = /bits/ 64 <652800000>;
3934 opp-peak-kBps = <816000>;
3935 };
3936
3937 cl2_ch1_opp9: opp-729600000 {
1582e1d1
SG		 3938 opp-hz = /bits/ 64 <729600000>;
3939 opp-peak-kBps = <816000>;
3940 };
3941
20515700
SG		 3942 cl2_ch1_opp10: opp-806400000 {
3943 opp-hz = /bits/ 64 <806400000>;
3944 opp-peak-kBps = <816000>;
3945 };
3946
3947 cl2_ch1_opp11: opp-883200000 {
1582e1d1
SG		 3948 opp-hz = /bits/ 64 <883200000>;
3949 opp-peak-kBps = <816000>;
3950 };
3951
20515700
SG		 3952 cl2_ch1_opp12: opp-960000000 {
3953 opp-hz = /bits/ 64 <960000000>;
3954 opp-peak-kBps = <816000>;
3955 };
3956
3957 cl2_ch1_opp13: opp-1036800000 {
1582e1d1
SG		 3958 opp-hz = /bits/ 64 <1036800000>;
3959 opp-peak-kBps = <816000>;
3960 };
3961
20515700
SG		 3962 cl2_ch1_opp14: opp-1113600000 {
3963 opp-hz = /bits/ 64 <1113600000>;
3964 opp-peak-kBps = <1632000>;
3965 };
3966
3967 cl2_ch1_opp15: opp-1190400000 {
1582e1d1 3968 opp-hz = /bits/ 64 <1190400000>;
20515700
SG		 3969 opp-peak-kBps = <1632000>;
3970 };
3971
3972 cl2_ch1_opp16: opp-1267200000 {
3973 opp-hz = /bits/ 64 <1267200000>;
3974 opp-peak-kBps = <1632000>;
1582e1d1
SG		 3975 };
3976
20515700 3977 cl2_ch1_opp17: opp-1344000000 {
1582e1d1
SG		 3978 opp-hz = /bits/ 64 <1344000000>;
3979 opp-peak-kBps = <1632000>;
3980 };
3981
20515700
SG		 3982 cl2_ch1_opp18: opp-1420800000 {
3983 opp-hz = /bits/ 64 <1420800000>;
1582e1d1
SG		 3984 opp-peak-kBps = <1632000>;
3985 };
3986
20515700
SG		 3987 cl2_ch1_opp19: opp-1497600000 {
3988 opp-hz = /bits/ 64 <1497600000>;
3989 opp-peak-kBps = <3200000>;
3990 };
3991
3992 cl2_ch1_opp20: opp-1574400000 {
3993 opp-hz = /bits/ 64 <1574400000>;
3994 opp-peak-kBps = <3200000>;
3995 };
3996
3997 cl2_ch1_opp21: opp-1651200000 {
1582e1d1 3998 opp-hz = /bits/ 64 <1651200000>;
20515700 3999 opp-peak-kBps = <3200000>;
1582e1d1
SG		 4000 };
4001
20515700
SG		 4002 cl2_ch1_opp22: opp-1728000000 {
4003 opp-hz = /bits/ 64 <1728000000>;
4004 opp-peak-kBps = <3200000>;
4005 };
4006
4007 cl2_ch1_opp23: opp-1804800000 {
1582e1d1 4008 opp-hz = /bits/ 64 <1804800000>;
20515700 4009 opp-peak-kBps = <3200000>;
1582e1d1
SG		 4010 };
4011
20515700
SG		 4012 cl2_ch1_opp24: opp-1881600000 {
4013 opp-hz = /bits/ 64 <1881600000>;
4014 opp-peak-kBps = <3200000>;
4015 };
4016
4017 cl2_ch1_opp25: opp-1958400000 {
1582e1d1
SG		 4018 opp-hz = /bits/ 64 <1958400000>;
4019 opp-peak-kBps = <3200000>;
4020 };
4021
20515700
SG		 4022 cl2_ch1_opp26: opp-2035200000 {
4023 opp-hz = /bits/ 64 <2035200000>;
4024 opp-peak-kBps = <3200000>;
4025 };
4026
4027 cl2_ch1_opp27: opp-2112000000 {
1582e1d1
SG		 4028 opp-hz = /bits/ 64 <2112000000>;
4029 opp-peak-kBps = <6400000>;
4030 };
4031
20515700
SG		 4032 cl2_ch1_opp28: opp-2188800000 {
4033 opp-hz = /bits/ 64 <2188800000>;
4034 opp-peak-kBps = <6400000>;
4035 };
4036
4037 cl2_ch1_opp29: opp-2201600000 {
1582e1d1
SG		 4038 opp-hz = /bits/ 64 <2201600000>;
4039 opp-peak-kBps = <6400000>;
4040 };
4041 };
63944891 4042};
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