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arm64: tegra: Update AHUB clock parent and rate on Tegra234
[thirdparty/linux.git] / arch / arm64 / boot / dts / nvidia / tegra234.dtsi
CommitLineData
63944891
TR		 1// SPDX-License-Identifier: GPL-2.0
2
3#include <dt-bindings/clock/tegra234-clock.h>
699349e0 4#include <dt-bindings/gpio/tegra234-gpio.h>
63944891
TR		 5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/mailbox/tegra186-hsp.h>
eed280df 7#include <dt-bindings/memory/tegra234-mc.h>
c71e1897 8#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
dc94a94d 9#include <dt-bindings/power/tegra234-powergate.h>
63944891 10#include <dt-bindings/reset/tegra234-reset.h>
09d99078 11#include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
63944891
TR		 12
13/ {
14 compatible = "nvidia,tegra234";
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
18
19 bus@0 {
20 compatible = "simple-bus";
63944891 21
2838cfdd
TR		 22 #address-cells = <2>;
23 #size-cells = <2>;
4bb54c2c 24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
63944891 25
79ed18d9
TR		 26 misc@100000 {
27 compatible = "nvidia,tegra234-misc";
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
30 status = "okay";
31 };
32
33 timer@2080000 {
34 compatible = "nvidia,tegra234-timer";
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
38 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
39 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
40 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
41 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
42 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
43 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
44 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
45 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
46 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
47 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
48 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
49 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
50 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
51 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
52 status = "okay";
53 };
54
55 gpio: gpio@2200000 {
56 compatible = "nvidia,tegra234-gpio";
57 reg-names = "security", "gpio";
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
60 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>,
61 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
62 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
63 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>,
64 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>,
65 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
66 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
71 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
72 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
73 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
74 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
75 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
79 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
81 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
82 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
83 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
86 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
89 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
90 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
91 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
92 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
97 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
98 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
99 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
100 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
102 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
103 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
104 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
105 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
106 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
107 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 #gpio-cells = <2>;
111 gpio-controller;
282fde00
PS		 112 gpio-ranges = <&pinmux 0 0 164>;
113 };
114
115 pinmux: pinmux@2430000 {
116 compatible = "nvidia,tegra234-pinmux";
117 reg = <0x0 0x2430000 0x0 0x19100>;
79ed18d9
TR		 118 };
119
60d2016a 120 gpcdma: dma-controller@2600000 {
f7b93a08 121 compatible = "nvidia,tegra234-gpcdma",
f7b93a08 122 "nvidia,tegra186-gpcdma";
2838cfdd 123 reg = <0x0 0x2600000 0x0 0x210000>;
60d2016a
A		 124 resets = <&bpmp TEGRA234_RESET_GPCDMA>;
125 reset-names = "gpcdma";
dd0be827
A		 126 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
60d2016a
A		 128 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
134 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
135 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
136 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
140 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
141 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
142 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
143 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
144 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
145 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
146 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
147 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
148 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
149 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
155 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
156 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
157 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
158 #dma-cells = <1>;
159 iommus = <&smmu_niso0 TEGRA234_SID_GPCDMA>;
dd0be827 160 dma-channel-mask = <0xfffffffe>;
60d2016a
A		 161 dma-coherent;
162 };
163
dc94a94d
SP		 164 aconnect@2900000 {
165 compatible = "nvidia,tegra234-aconnect",
166 "nvidia,tegra210-aconnect";
167 clocks = <&bpmp TEGRA234_CLK_APE>,
168 <&bpmp TEGRA234_CLK_APB2APE>;
169 clock-names = "ape", "apb2ape";
170 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_AUD>;
dc94a94d
SP		 171 status = "disabled";
172
2838cfdd
TR		 173 #address-cells = <2>;
174 #size-cells = <2>;
175 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
176
dc94a94d
SP		 177 tegra_ahub: ahub@2900800 {
178 compatible = "nvidia,tegra234-ahub";
2838cfdd 179 reg = <0x0 0x02900800 0x0 0x800>;
dc94a94d
SP		 180 clocks = <&bpmp TEGRA234_CLK_AHUB>;
181 clock-names = "ahub";
182 assigned-clocks = <&bpmp TEGRA234_CLK_AHUB>;
e483fe34
S		 183 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
184 assigned-clock-rates = <81600000>;
dc94a94d
SP		 185 status = "disabled";
186
2838cfdd
TR		 187 #address-cells = <2>;
188 #size-cells = <2>;
189 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
190
dc94a94d
SP		 191 tegra_i2s1: i2s@2901000 {
192 compatible = "nvidia,tegra234-i2s",
193 "nvidia,tegra210-i2s";
2838cfdd 194 reg = <0x0 0x2901000 0x0 0x100>;
dc94a94d
SP		 195 clocks = <&bpmp TEGRA234_CLK_I2S1>,
196 <&bpmp TEGRA234_CLK_I2S1_SYNC_INPUT>;
197 clock-names = "i2s", "sync_input";
198 assigned-clocks = <&bpmp TEGRA234_CLK_I2S1>;
199 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
200 assigned-clock-rates = <1536000>;
201 sound-name-prefix = "I2S1";
202 status = "disabled";
203 };
204
205 tegra_i2s2: i2s@2901100 {
206 compatible = "nvidia,tegra234-i2s",
207 "nvidia,tegra210-i2s";
2838cfdd 208 reg = <0x0 0x2901100 0x0 0x100>;
dc94a94d
SP		 209 clocks = <&bpmp TEGRA234_CLK_I2S2>,
210 <&bpmp TEGRA234_CLK_I2S2_SYNC_INPUT>;
211 clock-names = "i2s", "sync_input";
212 assigned-clocks = <&bpmp TEGRA234_CLK_I2S2>;
213 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
214 assigned-clock-rates = <1536000>;
215 sound-name-prefix = "I2S2";
216 status = "disabled";
217 };
218
219 tegra_i2s3: i2s@2901200 {
220 compatible = "nvidia,tegra234-i2s",
221 "nvidia,tegra210-i2s";
2838cfdd 222 reg = <0x0 0x2901200 0x0 0x100>;
dc94a94d
SP		 223 clocks = <&bpmp TEGRA234_CLK_I2S3>,
224 <&bpmp TEGRA234_CLK_I2S3_SYNC_INPUT>;
225 clock-names = "i2s", "sync_input";
226 assigned-clocks = <&bpmp TEGRA234_CLK_I2S3>;
227 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
228 assigned-clock-rates = <1536000>;
229 sound-name-prefix = "I2S3";
230 status = "disabled";
231 };
232
233 tegra_i2s4: i2s@2901300 {
234 compatible = "nvidia,tegra234-i2s",
235 "nvidia,tegra210-i2s";
2838cfdd 236 reg = <0x0 0x2901300 0x0 0x100>;
dc94a94d
SP		 237 clocks = <&bpmp TEGRA234_CLK_I2S4>,
238 <&bpmp TEGRA234_CLK_I2S4_SYNC_INPUT>;
239 clock-names = "i2s", "sync_input";
240 assigned-clocks = <&bpmp TEGRA234_CLK_I2S4>;
241 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
242 assigned-clock-rates = <1536000>;
243 sound-name-prefix = "I2S4";
244 status = "disabled";
245 };
246
247 tegra_i2s5: i2s@2901400 {
248 compatible = "nvidia,tegra234-i2s",
249 "nvidia,tegra210-i2s";
2838cfdd 250 reg = <0x0 0x2901400 0x0 0x100>;
dc94a94d
SP		 251 clocks = <&bpmp TEGRA234_CLK_I2S5>,
252 <&bpmp TEGRA234_CLK_I2S5_SYNC_INPUT>;
253 clock-names = "i2s", "sync_input";
254 assigned-clocks = <&bpmp TEGRA234_CLK_I2S5>;
255 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
256 assigned-clock-rates = <1536000>;
257 sound-name-prefix = "I2S5";
258 status = "disabled";
259 };
260
261 tegra_i2s6: i2s@2901500 {
262 compatible = "nvidia,tegra234-i2s",
263 "nvidia,tegra210-i2s";
2838cfdd 264 reg = <0x0 0x2901500 0x0 0x100>;
dc94a94d
SP		 265 clocks = <&bpmp TEGRA234_CLK_I2S6>,
266 <&bpmp TEGRA234_CLK_I2S6_SYNC_INPUT>;
267 clock-names = "i2s", "sync_input";
268 assigned-clocks = <&bpmp TEGRA234_CLK_I2S6>;
269 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
270 assigned-clock-rates = <1536000>;
271 sound-name-prefix = "I2S6";
272 status = "disabled";
273 };
274
275 tegra_sfc1: sfc@2902000 {
276 compatible = "nvidia,tegra234-sfc",
277 "nvidia,tegra210-sfc";
2838cfdd 278 reg = <0x0 0x2902000 0x0 0x200>;
dc94a94d
SP		 279 sound-name-prefix = "SFC1";
280 status = "disabled";
281 };
282
283 tegra_sfc2: sfc@2902200 {
284 compatible = "nvidia,tegra234-sfc",
285 "nvidia,tegra210-sfc";
2838cfdd 286 reg = <0x0 0x2902200 0x0 0x200>;
dc94a94d
SP		 287 sound-name-prefix = "SFC2";
288 status = "disabled";
289 };
290
291 tegra_sfc3: sfc@2902400 {
292 compatible = "nvidia,tegra234-sfc",
293 "nvidia,tegra210-sfc";
2838cfdd 294 reg = <0x0 0x2902400 0x0 0x200>;
dc94a94d
SP		 295 sound-name-prefix = "SFC3";
296 status = "disabled";
297 };
298
299 tegra_sfc4: sfc@2902600 {
300 compatible = "nvidia,tegra234-sfc",
301 "nvidia,tegra210-sfc";
2838cfdd 302 reg = <0x0 0x2902600 0x0 0x200>;
dc94a94d
SP		 303 sound-name-prefix = "SFC4";
304 status = "disabled";
305 };
306
307 tegra_amx1: amx@2903000 {
308 compatible = "nvidia,tegra234-amx",
309 "nvidia,tegra194-amx";
2838cfdd 310 reg = <0x0 0x2903000 0x0 0x100>;
dc94a94d
SP		 311 sound-name-prefix = "AMX1";
312 status = "disabled";
313 };
314
315 tegra_amx2: amx@2903100 {
316 compatible = "nvidia,tegra234-amx",
317 "nvidia,tegra194-amx";
2838cfdd 318 reg = <0x0 0x2903100 0x0 0x100>;
dc94a94d
SP		 319 sound-name-prefix = "AMX2";
320 status = "disabled";
321 };
322
323 tegra_amx3: amx@2903200 {
324 compatible = "nvidia,tegra234-amx",
325 "nvidia,tegra194-amx";
2838cfdd 326 reg = <0x0 0x2903200 0x0 0x100>;
dc94a94d
SP		 327 sound-name-prefix = "AMX3";
328 status = "disabled";
329 };
330
331 tegra_amx4: amx@2903300 {
332 compatible = "nvidia,tegra234-amx",
333 "nvidia,tegra194-amx";
2838cfdd 334 reg = <0x0 0x2903300 0x0 0x100>;
dc94a94d
SP		 335 sound-name-prefix = "AMX4";
336 status = "disabled";
337 };
338
339 tegra_adx1: adx@2903800 {
340 compatible = "nvidia,tegra234-adx",
341 "nvidia,tegra210-adx";
2838cfdd 342 reg = <0x0 0x2903800 0x0 0x100>;
dc94a94d
SP		 343 sound-name-prefix = "ADX1";
344 status = "disabled";
345 };
346
347 tegra_adx2: adx@2903900 {
348 compatible = "nvidia,tegra234-adx",
349 "nvidia,tegra210-adx";
2838cfdd 350 reg = <0x0 0x2903900 0x0 0x100>;
dc94a94d
SP		 351 sound-name-prefix = "ADX2";
352 status = "disabled";
353 };
354
355 tegra_adx3: adx@2903a00 {
356 compatible = "nvidia,tegra234-adx",
357 "nvidia,tegra210-adx";
2838cfdd 358 reg = <0x0 0x2903a00 0x0 0x100>;
dc94a94d
SP		 359 sound-name-prefix = "ADX3";
360 status = "disabled";
361 };
362
363 tegra_adx4: adx@2903b00 {
364 compatible = "nvidia,tegra234-adx",
365 "nvidia,tegra210-adx";
2838cfdd 366 reg = <0x0 0x2903b00 0x0 0x100>;
dc94a94d
SP		 367 sound-name-prefix = "ADX4";
368 status = "disabled";
369 };
370
371
372 tegra_dmic1: dmic@2904000 {
373 compatible = "nvidia,tegra234-dmic",
374 "nvidia,tegra210-dmic";
2838cfdd 375 reg = <0x0 0x2904000 0x0 0x100>;
dc94a94d
SP		 376 clocks = <&bpmp TEGRA234_CLK_DMIC1>;
377 clock-names = "dmic";
378 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC1>;
379 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
380 assigned-clock-rates = <3072000>;
381 sound-name-prefix = "DMIC1";
382 status = "disabled";
383 };
384
385 tegra_dmic2: dmic@2904100 {
386 compatible = "nvidia,tegra234-dmic",
387 "nvidia,tegra210-dmic";
2838cfdd 388 reg = <0x0 0x2904100 0x0 0x100>;
dc94a94d
SP		 389 clocks = <&bpmp TEGRA234_CLK_DMIC2>;
390 clock-names = "dmic";
391 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC2>;
392 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
393 assigned-clock-rates = <3072000>;
394 sound-name-prefix = "DMIC2";
395 status = "disabled";
396 };
397
398 tegra_dmic3: dmic@2904200 {
399 compatible = "nvidia,tegra234-dmic",
400 "nvidia,tegra210-dmic";
2838cfdd 401 reg = <0x0 0x2904200 0x0 0x100>;
dc94a94d
SP		 402 clocks = <&bpmp TEGRA234_CLK_DMIC3>;
403 clock-names = "dmic";
404 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC3>;
405 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
406 assigned-clock-rates = <3072000>;
407 sound-name-prefix = "DMIC3";
408 status = "disabled";
409 };
410
411 tegra_dmic4: dmic@2904300 {
412 compatible = "nvidia,tegra234-dmic",
413 "nvidia,tegra210-dmic";
2838cfdd 414 reg = <0x0 0x2904300 0x0 0x100>;
dc94a94d
SP		 415 clocks = <&bpmp TEGRA234_CLK_DMIC4>;
416 clock-names = "dmic";
417 assigned-clocks = <&bpmp TEGRA234_CLK_DMIC4>;
418 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
419 assigned-clock-rates = <3072000>;
420 sound-name-prefix = "DMIC4";
421 status = "disabled";
422 };
423
424 tegra_dspk1: dspk@2905000 {
425 compatible = "nvidia,tegra234-dspk",
426 "nvidia,tegra186-dspk";
2838cfdd 427 reg = <0x0 0x2905000 0x0 0x100>;
dc94a94d
SP		 428 clocks = <&bpmp TEGRA234_CLK_DSPK1>;
429 clock-names = "dspk";
430 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK1>;
431 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
432 assigned-clock-rates = <12288000>;
433 sound-name-prefix = "DSPK1";
434 status = "disabled";
435 };
436
437 tegra_dspk2: dspk@2905100 {
438 compatible = "nvidia,tegra234-dspk",
439 "nvidia,tegra186-dspk";
2838cfdd 440 reg = <0x0 0x2905100 0x0 0x100>;
dc94a94d
SP		 441 clocks = <&bpmp TEGRA234_CLK_DSPK2>;
442 clock-names = "dspk";
443 assigned-clocks = <&bpmp TEGRA234_CLK_DSPK2>;
444 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLA_OUT0>;
445 assigned-clock-rates = <12288000>;
446 sound-name-prefix = "DSPK2";
447 status = "disabled";
448 };
449
4b6a1b7c
SP		 450 tegra_ope1: processing-engine@2908000 {
451 compatible = "nvidia,tegra234-ope",
452 "nvidia,tegra210-ope";
2838cfdd 453 reg = <0x0 0x2908000 0x0 0x100>;
4b6a1b7c
SP		 454 sound-name-prefix = "OPE1";
455 status = "disabled";
456
2838cfdd
TR		 457 #address-cells = <2>;
458 #size-cells = <2>;
459 ranges;
460
4b6a1b7c
SP		 461 equalizer@2908100 {
462 compatible = "nvidia,tegra234-peq",
463 "nvidia,tegra210-peq";
2838cfdd 464 reg = <0x0 0x2908100 0x0 0x100>;
4b6a1b7c
SP		 465 };
466
467 dynamic-range-compressor@2908200 {
468 compatible = "nvidia,tegra234-mbdrc",
469 "nvidia,tegra210-mbdrc";
2838cfdd 470 reg = <0x0 0x2908200 0x0 0x200>;
4b6a1b7c
SP		 471 };
472 };
473
dc94a94d
SP		 474 tegra_mvc1: mvc@290a000 {
475 compatible = "nvidia,tegra234-mvc",
476 "nvidia,tegra210-mvc";
2838cfdd 477 reg = <0x0 0x290a000 0x0 0x200>;
dc94a94d
SP		 478 sound-name-prefix = "MVC1";
479 status = "disabled";
480 };
481
482 tegra_mvc2: mvc@290a200 {
483 compatible = "nvidia,tegra234-mvc",
484 "nvidia,tegra210-mvc";
2838cfdd 485 reg = <0x0 0x290a200 0x0 0x200>;
dc94a94d
SP		 486 sound-name-prefix = "MVC2";
487 status = "disabled";
488 };
489
490 tegra_amixer: amixer@290bb00 {
491 compatible = "nvidia,tegra234-amixer",
492 "nvidia,tegra210-amixer";
2838cfdd 493 reg = <0x0 0x290bb00 0x0 0x800>;
dc94a94d
SP		 494 sound-name-prefix = "MIXER1";
495 status = "disabled";
496 };
497
498 tegra_admaif: admaif@290f000 {
499 compatible = "nvidia,tegra234-admaif",
500 "nvidia,tegra186-admaif";
2838cfdd 501 reg = <0x0 0x0290f000 0x0 0x1000>;
dc94a94d
SP		 502 dmas = <&adma 1>, <&adma 1>,
503 <&adma 2>, <&adma 2>,
504 <&adma 3>, <&adma 3>,
505 <&adma 4>, <&adma 4>,
506 <&adma 5>, <&adma 5>,
507 <&adma 6>, <&adma 6>,
508 <&adma 7>, <&adma 7>,
509 <&adma 8>, <&adma 8>,
510 <&adma 9>, <&adma 9>,
511 <&adma 10>, <&adma 10>,
512 <&adma 11>, <&adma 11>,
513 <&adma 12>, <&adma 12>,
514 <&adma 13>, <&adma 13>,
515 <&adma 14>, <&adma 14>,
516 <&adma 15>, <&adma 15>,
517 <&adma 16>, <&adma 16>,
518 <&adma 17>, <&adma 17>,
519 <&adma 18>, <&adma 18>,
520 <&adma 19>, <&adma 19>,
521 <&adma 20>, <&adma 20>;
522 dma-names = "rx1", "tx1",
523 "rx2", "tx2",
524 "rx3", "tx3",
525 "rx4", "tx4",
526 "rx5", "tx5",
527 "rx6", "tx6",
528 "rx7", "tx7",
529 "rx8", "tx8",
530 "rx9", "tx9",
531 "rx10", "tx10",
532 "rx11", "tx11",
533 "rx12", "tx12",
534 "rx13", "tx13",
535 "rx14", "tx14",
536 "rx15", "tx15",
537 "rx16", "tx16",
538 "rx17", "tx17",
539 "rx18", "tx18",
540 "rx19", "tx19",
541 "rx20", "tx20";
542 interconnects = <&mc TEGRA234_MEMORY_CLIENT_APEDMAR &emc>,
543 <&mc TEGRA234_MEMORY_CLIENT_APEDMAW &emc>;
544 interconnect-names = "dma-mem", "write";
545 iommus = <&smmu_niso0 TEGRA234_SID_APE>;
546 status = "disabled";
547 };
47a08153
SP		 548
549 tegra_asrc: asrc@2910000 {
550 compatible = "nvidia,tegra234-asrc",
551 "nvidia,tegra186-asrc";
2838cfdd 552 reg = <0x0 0x2910000 0x0 0x2000>;
47a08153
SP		 553 sound-name-prefix = "ASRC1";
554 status = "disabled";
555 };
dc94a94d
SP		 556 };
557
558 adma: dma-controller@2930000 {
559 compatible = "nvidia,tegra234-adma",
560 "nvidia,tegra186-adma";
2838cfdd 561 reg = <0x0 0x02930000 0x0 0x20000>;
dc94a94d
SP		 562 interrupt-parent = <&agic>;
563 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
564 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
565 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
566 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
570 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
571 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
573 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
574 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
575 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
576 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
577 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
578 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
579 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
586 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
587 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
588 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
589 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
590 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
591 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
592 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
593 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
594 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
595 #dma-cells = <1>;
596 clocks = <&bpmp TEGRA234_CLK_AHUB>;
597 clock-names = "d_audio";
598 status = "disabled";
599 };
600
601 agic: interrupt-controller@2a40000 {
602 compatible = "nvidia,tegra234-agic",
603 "nvidia,tegra210-agic";
604 #interrupt-cells = <3>;
605 interrupt-controller;
2838cfdd
TR		 606 reg = <0x0 0x02a41000 0x0 0x1000>,
607 <0x0 0x02a42000 0x0 0x2000>;
dc94a94d
SP		 608 interrupts = <GIC_SPI 145
609 (GIC_CPU_MASK_SIMPLE(4) |
610 IRQ_TYPE_LEVEL_HIGH)>;
611 clocks = <&bpmp TEGRA234_CLK_APE>;
612 clock-names = "clk";
613 status = "disabled";
614 };
615 };
616
eed280df
TR		 617 mc: memory-controller@2c00000 {
618 compatible = "nvidia,tegra234-mc";
2838cfdd
TR		 619 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
620 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
621 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
622 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
623 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
624 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
625 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
626 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
627 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
628 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
629 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
630 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
631 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
632 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
633 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
634 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
635 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
636 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
000b99e5
AM		 637 reg-names = "sid", "broadcast", "ch0", "ch1", "ch2", "ch3",
638 "ch4", "ch5", "ch6", "ch7", "ch8", "ch9", "ch10",
639 "ch11", "ch12", "ch13", "ch14", "ch15";
eed280df
TR		 640 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
641 #interconnect-cells = <1>;
642 status = "okay";
643
644 #address-cells = <2>;
645 #size-cells = <2>;
2838cfdd
TR		 646 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
647 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
648 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
eed280df
TR		 649
650 /*
651 * Bit 39 of addresses passing through the memory
652 * controller selects the XBAR format used when memory
653 * is accessed. This is used to transparently access
654 * memory in the XBAR format used by the discrete GPU
655 * (bit 39 set) or Tegra (bit 39 clear).
656 *
657 * As a consequence, the operating system must ensure
658 * that bit 39 is never used implicitly, for example
659 * via an I/O virtual address mapping of an IOMMU. If
660 * devices require access to the XBAR switch, their
661 * drivers must set this bit explicitly.
662 *
663 * Limit the DMA range for memory clients to [38:0].
664 */
2838cfdd 665 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
eed280df
TR		 666
667 emc: external-memory-controller@2c60000 {
668 compatible = "nvidia,tegra234-emc";
669 reg = <0x0 0x02c60000 0x0 0x90000>,
670 <0x0 0x01780000 0x0 0x80000>;
671 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
672 clocks = <&bpmp TEGRA234_CLK_EMC>;
673 clock-names = "emc";
674 status = "okay";
675
676 #interconnect-cells = <0>;
677
678 nvidia,bpmp = <&bpmp>;
679 };
680 };
681
63944891
TR		 682 uarta: serial@3100000 {
683 compatible = "nvidia,tegra234-uart", "nvidia,tegra20-uart";
2838cfdd 684 reg = <0x0 0x03100000 0x0 0x10000>;
63944891
TR		 685 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
686 clocks = <&bpmp TEGRA234_CLK_UARTA>;
63944891 687 resets = <&bpmp TEGRA234_RESET_UARTA>;
63944891
TR		 688 status = "disabled";
689 };
690
156af9de
A		 691 gen1_i2c: i2c@3160000 {
692 compatible = "nvidia,tegra194-i2c";
2838cfdd 693 reg = <0x0 0x3160000 0x0 0x100>;
156af9de
A		 694 status = "disabled";
695 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 696 #address-cells = <1>;
697 #size-cells = <0>;
156af9de
A		 698 clock-frequency = <400000>;
699 clocks = <&bpmp TEGRA234_CLK_I2C1
700 &bpmp TEGRA234_CLK_PLLP_OUT0>;
701 assigned-clocks = <&bpmp TEGRA234_CLK_I2C1>;
702 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
703 clock-names = "div-clk", "parent";
704 resets = <&bpmp TEGRA234_RESET_I2C1>;
705 reset-names = "i2c";
8e442805
A		 706 dmas = <&gpcdma 21>, <&gpcdma 21>;
707 dma-names = "rx", "tx";
156af9de
A		 708 };
709
710 cam_i2c: i2c@3180000 {
711 compatible = "nvidia,tegra194-i2c";
2838cfdd 712 reg = <0x0 0x3180000 0x0 0x100>;
156af9de 713 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 714 #address-cells = <1>;
715 #size-cells = <0>;
156af9de
A		 716 status = "disabled";
717 clock-frequency = <400000>;
718 clocks = <&bpmp TEGRA234_CLK_I2C3
719 &bpmp TEGRA234_CLK_PLLP_OUT0>;
720 assigned-clocks = <&bpmp TEGRA234_CLK_I2C3>;
721 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
722 clock-names = "div-clk", "parent";
723 resets = <&bpmp TEGRA234_RESET_I2C3>;
724 reset-names = "i2c";
8e442805
A		 725 dmas = <&gpcdma 23>, <&gpcdma 23>;
726 dma-names = "rx", "tx";
156af9de
A		 727 };
728
729 dp_aux_ch1_i2c: i2c@3190000 {
730 compatible = "nvidia,tegra194-i2c";
2838cfdd 731 reg = <0x0 0x3190000 0x0 0x100>;
156af9de 732 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 733 #address-cells = <1>;
734 #size-cells = <0>;
156af9de
A		 735 status = "disabled";
736 clock-frequency = <100000>;
737 clocks = <&bpmp TEGRA234_CLK_I2C4
738 &bpmp TEGRA234_CLK_PLLP_OUT0>;
739 assigned-clocks = <&bpmp TEGRA234_CLK_I2C4>;
740 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
741 clock-names = "div-clk", "parent";
742 resets = <&bpmp TEGRA234_RESET_I2C4>;
743 reset-names = "i2c";
8e442805
A		 744 dmas = <&gpcdma 26>, <&gpcdma 26>;
745 dma-names = "rx", "tx";
156af9de
A		 746 };
747
748 dp_aux_ch0_i2c: i2c@31b0000 {
749 compatible = "nvidia,tegra194-i2c";
2838cfdd 750 reg = <0x0 0x31b0000 0x0 0x100>;
156af9de 751 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 752 #address-cells = <1>;
753 #size-cells = <0>;
156af9de
A		 754 status = "disabled";
755 clock-frequency = <100000>;
756 clocks = <&bpmp TEGRA234_CLK_I2C6
757 &bpmp TEGRA234_CLK_PLLP_OUT0>;
758 assigned-clocks = <&bpmp TEGRA234_CLK_I2C6>;
759 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
760 clock-names = "div-clk", "parent";
761 resets = <&bpmp TEGRA234_RESET_I2C6>;
762 reset-names = "i2c";
8e442805
A		 763 dmas = <&gpcdma 30>, <&gpcdma 30>;
764 dma-names = "rx", "tx";
156af9de
A		 765 };
766
767 dp_aux_ch2_i2c: i2c@31c0000 {
768 compatible = "nvidia,tegra194-i2c";
2838cfdd 769 reg = <0x0 0x31c0000 0x0 0x100>;
156af9de 770 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 771 #address-cells = <1>;
772 #size-cells = <0>;
156af9de
A		 773 status = "disabled";
774 clock-frequency = <100000>;
775 clocks = <&bpmp TEGRA234_CLK_I2C7
776 &bpmp TEGRA234_CLK_PLLP_OUT0>;
777 assigned-clocks = <&bpmp TEGRA234_CLK_I2C7>;
778 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
779 clock-names = "div-clk", "parent";
780 resets = <&bpmp TEGRA234_RESET_I2C7>;
781 reset-names = "i2c";
8e442805
A		 782 dmas = <&gpcdma 27>, <&gpcdma 27>;
783 dma-names = "rx", "tx";
156af9de
A		 784 };
785
1bbba854
JH		 786 uarti: serial@31d0000 {
787 compatible = "arm,sbsa-uart";
2838cfdd 788 reg = <0x0 0x31d0000 0x0 0x10000>;
1bbba854
JH		 789 interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
790 status = "disabled";
791 };
792
156af9de
A		 793 dp_aux_ch3_i2c: i2c@31e0000 {
794 compatible = "nvidia,tegra194-i2c";
2838cfdd 795 reg = <0x0 0x31e0000 0x0 0x100>;
156af9de 796 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 797 #address-cells = <1>;
798 #size-cells = <0>;
156af9de
A		 799 status = "disabled";
800 clock-frequency = <100000>;
801 clocks = <&bpmp TEGRA234_CLK_I2C9
802 &bpmp TEGRA234_CLK_PLLP_OUT0>;
803 assigned-clocks = <&bpmp TEGRA234_CLK_I2C9>;
804 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
805 clock-names = "div-clk", "parent";
806 resets = <&bpmp TEGRA234_RESET_I2C9>;
807 reset-names = "i2c";
8e442805
A		 808 dmas = <&gpcdma 31>, <&gpcdma 31>;
809 dma-names = "rx", "tx";
156af9de
A		 810 };
811
71f69ffa
AS		 812 spi@3270000 {
813 compatible = "nvidia,tegra234-qspi";
2838cfdd 814 reg = <0x0 0x3270000 0x0 0x1000>;
71f69ffa
AS		 815 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
816 #address-cells = <1>;
817 #size-cells = <0>;
818 clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
819 <&bpmp TEGRA234_CLK_QSPI0_PM>;
820 clock-names = "qspi", "qspi_out";
821 resets = <&bpmp TEGRA234_RESET_QSPI0>;
71f69ffa
AS		 822 status = "disabled";
823 };
824
5e69088d 825 pwm1: pwm@3280000 {
2566d28c 826 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 827 reg = <0x0 0x3280000 0x0 0x10000>;
5e69088d 828 clocks = <&bpmp TEGRA234_CLK_PWM1>;
5e69088d
A		 829 resets = <&bpmp TEGRA234_RESET_PWM1>;
830 reset-names = "pwm";
831 status = "disabled";
832 #pwm-cells = <2>;
833 };
834
2566d28c
JH		 835 pwm2: pwm@3290000 {
836 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 837 reg = <0x0 0x3290000 0x0 0x10000>;
2566d28c 838 clocks = <&bpmp TEGRA234_CLK_PWM2>;
2566d28c
JH		 839 resets = <&bpmp TEGRA234_RESET_PWM2>;
840 reset-names = "pwm";
841 status = "disabled";
842 #pwm-cells = <2>;
843 };
844
845 pwm3: pwm@32a0000 {
846 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 847 reg = <0x0 0x32a0000 0x0 0x10000>;
2566d28c 848 clocks = <&bpmp TEGRA234_CLK_PWM3>;
2566d28c
JH		 849 resets = <&bpmp TEGRA234_RESET_PWM3>;
850 reset-names = "pwm";
851 status = "disabled";
852 #pwm-cells = <2>;
853 };
854
855 pwm5: pwm@32c0000 {
856 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 857 reg = <0x0 0x32c0000 0x0 0x10000>;
2566d28c 858 clocks = <&bpmp TEGRA234_CLK_PWM5>;
2566d28c
JH		 859 resets = <&bpmp TEGRA234_RESET_PWM5>;
860 reset-names = "pwm";
861 status = "disabled";
862 #pwm-cells = <2>;
863 };
864
865 pwm6: pwm@32d0000 {
866 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 867 reg = <0x0 0x32d0000 0x0 0x10000>;
2566d28c 868 clocks = <&bpmp TEGRA234_CLK_PWM6>;
2566d28c
JH		 869 resets = <&bpmp TEGRA234_RESET_PWM6>;
870 reset-names = "pwm";
871 status = "disabled";
872 #pwm-cells = <2>;
873 };
874
875 pwm7: pwm@32e0000 {
876 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 877 reg = <0x0 0x32e0000 0x0 0x10000>;
2566d28c 878 clocks = <&bpmp TEGRA234_CLK_PWM7>;
2566d28c
JH		 879 resets = <&bpmp TEGRA234_RESET_PWM7>;
880 reset-names = "pwm";
881 status = "disabled";
882 #pwm-cells = <2>;
883 };
884
885 pwm8: pwm@32f0000 {
886 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 887 reg = <0x0 0x32f0000 0x0 0x10000>;
2566d28c 888 clocks = <&bpmp TEGRA234_CLK_PWM8>;
2566d28c
JH		 889 resets = <&bpmp TEGRA234_RESET_PWM8>;
890 reset-names = "pwm";
891 status = "disabled";
892 #pwm-cells = <2>;
893 };
894
71f69ffa
AS		 895 spi@3300000 {
896 compatible = "nvidia,tegra234-qspi";
2838cfdd 897 reg = <0x0 0x3300000 0x0 0x1000>;
71f69ffa
AS		 898 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
899 #address-cells = <1>;
900 #size-cells = <0>;
901 clocks = <&bpmp TEGRA234_CLK_QSPI1_2X_PM>,
902 <&bpmp TEGRA234_CLK_QSPI1_PM>;
903 clock-names = "qspi", "qspi_out";
904 resets = <&bpmp TEGRA234_RESET_QSPI1>;
71f69ffa
AS		 905 status = "disabled";
906 };
907
d71b893a 908 mmc@3400000 {
132b552c 909 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
2838cfdd 910 reg = <0x0 0x03400000 0x0 0x20000>;
d71b893a
PS		 911 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
912 clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
913 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
914 clock-names = "sdhci", "tmclk";
915 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC1>,
916 <&bpmp TEGRA234_CLK_PLLC4_MUXED>;
917 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4_MUXED>,
918 <&bpmp TEGRA234_CLK_PLLC4_VCO_DIV2>;
919 resets = <&bpmp TEGRA234_RESET_SDMMC1>;
920 reset-names = "sdhci";
921 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRA &emc>,
922 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWA &emc>;
923 interconnect-names = "dma-mem", "write";
924 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC1A>;
925 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
926 pinctrl-0 = <&sdmmc1_3v3>;
927 pinctrl-1 = <&sdmmc1_1v8>;
928 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
929 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
930 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
931 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
932 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
933 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
934 nvidia,default-tap = <14>;
935 nvidia,default-trim = <0x8>;
936 sd-uhs-sdr25;
937 sd-uhs-sdr50;
938 sd-uhs-ddr50;
939 sd-uhs-sdr104;
940 status = "disabled";
941 };
942
63944891
TR		 943 mmc@3460000 {
944 compatible = "nvidia,tegra234-sdhci", "nvidia,tegra186-sdhci";
2838cfdd 945 reg = <0x0 0x03460000 0x0 0x20000>;
63944891 946 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
e086d82d
MP		 947 clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
948 <&bpmp TEGRA234_CLK_SDMMC_LEGACY_TM>;
949 clock-names = "sdhci", "tmclk";
950 assigned-clocks = <&bpmp TEGRA234_CLK_SDMMC4>,
951 <&bpmp TEGRA234_CLK_PLLC4>;
952 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC4>;
63944891
TR		 953 resets = <&bpmp TEGRA234_RESET_SDMMC4>;
954 reset-names = "sdhci";
6de481e5
TR		 955 interconnects = <&mc TEGRA234_MEMORY_CLIENT_SDMMCRAB &emc>,
956 <&mc TEGRA234_MEMORY_CLIENT_SDMMCWAB &emc>;
957 interconnect-names = "dma-mem", "write";
5710e16a 958 iommus = <&smmu_niso1 TEGRA234_SID_SDMMC4>;
e086d82d
MP		 959 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
960 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
961 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
962 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
963 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
964 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
965 nvidia,default-tap = <0x8>;
966 nvidia,default-trim = <0x14>;
967 nvidia,dqs-trim = <40>;
968 supports-cqe;
63944891
TR		 969 status = "disabled";
970 };
971
621e12a1 972 hda@3510000 {
b2fbcbe1 973 compatible = "nvidia,tegra234-hda";
2838cfdd 974 reg = <0x0 0x3510000 0x0 0x10000>;
621e12a1
MK		 975 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
976 clocks = <&bpmp TEGRA234_CLK_AZA_BIT>,
977 <&bpmp TEGRA234_CLK_AZA_2XBIT>;
978 clock-names = "hda", "hda2codec_2x";
979 resets = <&bpmp TEGRA234_RESET_HDA>,
980 <&bpmp TEGRA234_RESET_HDACODEC>;
981 reset-names = "hda", "hda2codec_2x";
982 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_DISP>;
983 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HDAR &emc>,
984 <&mc TEGRA234_MEMORY_CLIENT_HDAW &emc>;
985 interconnect-names = "dma-mem", "write";
af4c2773 986 iommus = <&smmu_niso0 TEGRA234_SID_HDA>;
621e12a1
MK		 987 status = "disabled";
988 };
989
6e505dd6
WC		 990 xusb_padctl: padctl@3520000 {
991 compatible = "nvidia,tegra234-xusb-padctl";
992 reg = <0x0 0x03520000 0x0 0x20000>,
993 <0x0 0x03540000 0x0 0x10000>;
994 reg-names = "padctl", "ao";
995 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
996
997 resets = <&bpmp TEGRA234_RESET_XUSB_PADCTL>;
998 reset-names = "padctl";
999
1000 status = "disabled";
1001
1002 pads {
1003 usb2 {
1004 clocks = <&bpmp TEGRA234_CLK_USB2_TRK>;
1005 clock-names = "trk";
1006
1007 lanes {
1008 usb2-0 {
1009 nvidia,function = "xusb";
1010 status = "disabled";
1011 #phy-cells = <0>;
1012 };
1013
1014 usb2-1 {
1015 nvidia,function = "xusb";
1016 status = "disabled";
1017 #phy-cells = <0>;
1018 };
1019
1020 usb2-2 {
1021 nvidia,function = "xusb";
1022 status = "disabled";
1023 #phy-cells = <0>;
1024 };
1025
1026 usb2-3 {
1027 nvidia,function = "xusb";
1028 status = "disabled";
1029 #phy-cells = <0>;
1030 };
1031 };
1032 };
1033
1034 usb3 {
1035 lanes {
1036 usb3-0 {
1037 nvidia,function = "xusb";
1038 status = "disabled";
1039 #phy-cells = <0>;
1040 };
1041
1042 usb3-1 {
1043 nvidia,function = "xusb";
1044 status = "disabled";
1045 #phy-cells = <0>;
1046 };
1047
1048 usb3-2 {
1049 nvidia,function = "xusb";
1050 status = "disabled";
1051 #phy-cells = <0>;
1052 };
1053
1054 usb3-3 {
1055 nvidia,function = "xusb";
1056 status = "disabled";
1057 #phy-cells = <0>;
1058 };
1059 };
1060 };
1061 };
1062
1063 ports {
1064 usb2-0 {
1065 status = "disabled";
1066 };
1067
1068 usb2-1 {
1069 status = "disabled";
1070 };
1071
1072 usb2-2 {
1073 status = "disabled";
1074 };
1075
1076 usb2-3 {
1077 status = "disabled";
1078 };
1079
1080 usb3-0 {
1081 status = "disabled";
1082 };
1083
1084 usb3-1 {
1085 status = "disabled";
1086 };
1087
1088 usb3-2 {
1089 status = "disabled";
1090 };
1091
1092 usb3-3 {
1093 status = "disabled";
1094 };
1095 };
1096 };
1097
320e0a70
JH		 1098 usb@3550000 {
1099 compatible = "nvidia,tegra234-xudc";
1100 reg = <0x0 0x03550000 0x0 0x8000>,
1101 <0x0 0x03558000 0x0 0x8000>;
1102 reg-names = "base", "fpci";
1103 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
1104 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_DEV>,
1105 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1106 <&bpmp TEGRA234_CLK_XUSB_SS>,
1107 <&bpmp TEGRA234_CLK_XUSB_FS>;
1108 clock-names = "dev", "ss", "ss_src", "fs_src";
1109 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVR &emc>,
1110 <&mc TEGRA234_MEMORY_CLIENT_XUSB_DEVW &emc>;
1111 interconnect-names = "dma-mem", "write";
1112 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_DEV>;
1113 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBB>,
1114 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1115 power-domain-names = "dev", "ss";
1116 nvidia,xusb-padctl = <&xusb_padctl>;
1117 dma-coherent;
1118 status = "disabled";
1119 };
1120
6e505dd6
WC		 1121 usb@3610000 {
1122 compatible = "nvidia,tegra234-xusb";
1123 reg = <0x0 0x03610000 0x0 0x40000>,
1124 <0x0 0x03600000 0x0 0x10000>,
1125 <0x0 0x03650000 0x0 0x10000>;
1126 reg-names = "hcd", "fpci", "bar2";
1127
1128 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1129 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
1130
1131 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>,
1132 <&bpmp TEGRA234_CLK_XUSB_FALCON>,
1133 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>,
1134 <&bpmp TEGRA234_CLK_XUSB_SS>,
1135 <&bpmp TEGRA234_CLK_CLK_M>,
1136 <&bpmp TEGRA234_CLK_XUSB_FS>,
1137 <&bpmp TEGRA234_CLK_UTMIP_PLL>,
1138 <&bpmp TEGRA234_CLK_CLK_M>,
1139 <&bpmp TEGRA234_CLK_PLLE>;
1140 clock-names = "xusb_host", "xusb_falcon_src",
1141 "xusb_ss", "xusb_ss_src", "xusb_hs_src",
1142 "xusb_fs_src", "pll_u_480m", "clk_m",
1143 "pll_e";
1144 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>,
1145 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>;
1146 interconnect-names = "dma-mem", "write";
1147 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>;
1148
1149 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>,
1150 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>;
1151 power-domain-names = "xusb_host", "xusb_ss";
1152
1153 nvidia,xusb-padctl = <&xusb_padctl>;
1154 dma-coherent;
1155 status = "disabled";
1156 };
1157
63944891
TR		 1158 fuse@3810000 {
1159 compatible = "nvidia,tegra234-efuse";
2838cfdd 1160 reg = <0x0 0x03810000 0x0 0x10000>;
63944891
TR		 1161 clocks = <&bpmp TEGRA234_CLK_FUSE>;
1162 clock-names = "fuse";
1163 };
1164
29662d62
DP		 1165 hte_lic: hardware-timestamp@3aa0000 {
1166 compatible = "nvidia,tegra234-gte-lic";
1167 reg = <0x0 0x3aa0000 0x0 0x10000>;
1168 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1169 nvidia,int-threshold = <1>;
1170 #timestamp-cells = <1>;
1171 };
1172
63944891
TR		 1173 hsp_top0: hsp@3c00000 {
1174 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
2838cfdd 1175 reg = <0x0 0x03c00000 0x0 0xa0000>;
63944891
TR		 1176 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
1177 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1178 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1179 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
1180 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1181 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1183 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1184 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1185 interrupt-names = "doorbell", "shared0", "shared1", "shared2",
1186 "shared3", "shared4", "shared5", "shared6",
1187 "shared7";
1188 #mbox-cells = <2>;
1189 };
1190
78159542
TR		 1191 p2u_hsio_0: phy@3e00000 {
1192 compatible = "nvidia,tegra234-p2u";
2838cfdd 1193 reg = <0x0 0x03e00000 0x0 0x10000>;
78159542
TR		 1194 reg-names = "ctl";
1195
1196 #phy-cells = <0>;
1197 };
1198
1199 p2u_hsio_1: phy@3e10000 {
1200 compatible = "nvidia,tegra234-p2u";
2838cfdd 1201 reg = <0x0 0x03e10000 0x0 0x10000>;
78159542
TR		 1202 reg-names = "ctl";
1203
1204 #phy-cells = <0>;
1205 };
1206
1207 p2u_hsio_2: phy@3e20000 {
1208 compatible = "nvidia,tegra234-p2u";
2838cfdd 1209 reg = <0x0 0x03e20000 0x0 0x10000>;
78159542
TR		 1210 reg-names = "ctl";
1211
1212 #phy-cells = <0>;
1213 };
1214
1215 p2u_hsio_3: phy@3e30000 {
1216 compatible = "nvidia,tegra234-p2u";
2838cfdd 1217 reg = <0x0 0x03e30000 0x0 0x10000>;
78159542
TR		 1218 reg-names = "ctl";
1219
1220 #phy-cells = <0>;
1221 };
1222
1223 p2u_hsio_4: phy@3e40000 {
1224 compatible = "nvidia,tegra234-p2u";
2838cfdd 1225 reg = <0x0 0x03e40000 0x0 0x10000>;
78159542
TR		 1226 reg-names = "ctl";
1227
1228 #phy-cells = <0>;
1229 };
1230
1231 p2u_hsio_5: phy@3e50000 {
1232 compatible = "nvidia,tegra234-p2u";
2838cfdd 1233 reg = <0x0 0x03e50000 0x0 0x10000>;
78159542
TR		 1234 reg-names = "ctl";
1235
1236 #phy-cells = <0>;
1237 };
1238
1239 p2u_hsio_6: phy@3e60000 {
1240 compatible = "nvidia,tegra234-p2u";
2838cfdd 1241 reg = <0x0 0x03e60000 0x0 0x10000>;
78159542
TR		 1242 reg-names = "ctl";
1243
1244 #phy-cells = <0>;
1245 };
1246
1247 p2u_hsio_7: phy@3e70000 {
1248 compatible = "nvidia,tegra234-p2u";
2838cfdd 1249 reg = <0x0 0x03e70000 0x0 0x10000>;
78159542
TR		 1250 reg-names = "ctl";
1251
1252 #phy-cells = <0>;
1253 };
1254
1255 p2u_nvhs_0: phy@3e90000 {
1256 compatible = "nvidia,tegra234-p2u";
2838cfdd 1257 reg = <0x0 0x03e90000 0x0 0x10000>;
78159542
TR		 1258 reg-names = "ctl";
1259
1260 #phy-cells = <0>;
1261 };
1262
1263 p2u_nvhs_1: phy@3ea0000 {
1264 compatible = "nvidia,tegra234-p2u";
2838cfdd 1265 reg = <0x0 0x03ea0000 0x0 0x10000>;
78159542
TR		 1266 reg-names = "ctl";
1267
1268 #phy-cells = <0>;
1269 };
1270
1271 p2u_nvhs_2: phy@3eb0000 {
1272 compatible = "nvidia,tegra234-p2u";
2838cfdd 1273 reg = <0x0 0x03eb0000 0x0 0x10000>;
78159542
TR		 1274 reg-names = "ctl";
1275
1276 #phy-cells = <0>;
1277 };
1278
1279 p2u_nvhs_3: phy@3ec0000 {
1280 compatible = "nvidia,tegra234-p2u";
2838cfdd 1281 reg = <0x0 0x03ec0000 0x0 0x10000>;
78159542
TR		 1282 reg-names = "ctl";
1283
1284 #phy-cells = <0>;
1285 };
1286
1287 p2u_nvhs_4: phy@3ed0000 {
1288 compatible = "nvidia,tegra234-p2u";
2838cfdd 1289 reg = <0x0 0x03ed0000 0x0 0x10000>;
78159542
TR		 1290 reg-names = "ctl";
1291
1292 #phy-cells = <0>;
1293 };
1294
1295 p2u_nvhs_5: phy@3ee0000 {
1296 compatible = "nvidia,tegra234-p2u";
2838cfdd 1297 reg = <0x0 0x03ee0000 0x0 0x10000>;
78159542
TR		 1298 reg-names = "ctl";
1299
1300 #phy-cells = <0>;
1301 };
1302
1303 p2u_nvhs_6: phy@3ef0000 {
1304 compatible = "nvidia,tegra234-p2u";
2838cfdd 1305 reg = <0x0 0x03ef0000 0x0 0x10000>;
78159542
TR		 1306 reg-names = "ctl";
1307
1308 #phy-cells = <0>;
1309 };
1310
1311 p2u_nvhs_7: phy@3f00000 {
1312 compatible = "nvidia,tegra234-p2u";
2838cfdd 1313 reg = <0x0 0x03f00000 0x0 0x10000>;
78159542
TR		 1314 reg-names = "ctl";
1315
1316 #phy-cells = <0>;
1317 };
1318
1319 p2u_gbe_0: phy@3f20000 {
1320 compatible = "nvidia,tegra234-p2u";
2838cfdd 1321 reg = <0x0 0x03f20000 0x0 0x10000>;
78159542
TR		 1322 reg-names = "ctl";
1323
1324 #phy-cells = <0>;
1325 };
1326
1327 p2u_gbe_1: phy@3f30000 {
1328 compatible = "nvidia,tegra234-p2u";
2838cfdd 1329 reg = <0x0 0x03f30000 0x0 0x10000>;
78159542
TR		 1330 reg-names = "ctl";
1331
1332 #phy-cells = <0>;
1333 };
1334
1335 p2u_gbe_2: phy@3f40000 {
1336 compatible = "nvidia,tegra234-p2u";
2838cfdd 1337 reg = <0x0 0x03f40000 0x0 0x10000>;
78159542
TR		 1338 reg-names = "ctl";
1339
1340 #phy-cells = <0>;
1341 };
1342
1343 p2u_gbe_3: phy@3f50000 {
1344 compatible = "nvidia,tegra234-p2u";
2838cfdd 1345 reg = <0x0 0x03f50000 0x0 0x10000>;
78159542
TR		 1346 reg-names = "ctl";
1347
1348 #phy-cells = <0>;
1349 };
1350
1351 p2u_gbe_4: phy@3f60000 {
1352 compatible = "nvidia,tegra234-p2u";
2838cfdd 1353 reg = <0x0 0x03f60000 0x0 0x10000>;
78159542
TR		 1354 reg-names = "ctl";
1355
1356 #phy-cells = <0>;
1357 };
1358
1359 p2u_gbe_5: phy@3f70000 {
1360 compatible = "nvidia,tegra234-p2u";
2838cfdd 1361 reg = <0x0 0x03f70000 0x0 0x10000>;
78159542
TR		 1362 reg-names = "ctl";
1363
1364 #phy-cells = <0>;
1365 };
1366
1367 p2u_gbe_6: phy@3f80000 {
1368 compatible = "nvidia,tegra234-p2u";
2838cfdd 1369 reg = <0x0 0x03f80000 0x0 0x10000>;
78159542
TR		 1370 reg-names = "ctl";
1371
1372 #phy-cells = <0>;
1373 };
1374
1375 p2u_gbe_7: phy@3f90000 {
1376 compatible = "nvidia,tegra234-p2u";
2838cfdd 1377 reg = <0x0 0x03f90000 0x0 0x10000>;
78159542
TR		 1378 reg-names = "ctl";
1379
1380 #phy-cells = <0>;
1381 };
1382
610cdf31
TR		 1383 ethernet@6800000 {
1384 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1385 reg = <0x0 0x06800000 0x0 0x10000>,
1386 <0x0 0x06810000 0x0 0x10000>,
1387 <0x0 0x068a0000 0x0 0x10000>;
610cdf31
TR		 1388 reg-names = "hypervisor", "mac", "xpcs";
1389 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>;
1390 interrupt-names = "common";
1391 clocks = <&bpmp TEGRA234_CLK_MGBE0_APP>,
1392 <&bpmp TEGRA234_CLK_MGBE0_MAC>,
1393 <&bpmp TEGRA234_CLK_MGBE0_MAC_DIVIDER>,
1394 <&bpmp TEGRA234_CLK_MGBE0_PTP_REF>,
1395 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT_M>,
1396 <&bpmp TEGRA234_CLK_MGBE0_RX_INPUT>,
1397 <&bpmp TEGRA234_CLK_MGBE0_TX>,
1398 <&bpmp TEGRA234_CLK_MGBE0_EEE_PCS>,
1399 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_INPUT>,
1400 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS_M>,
1401 <&bpmp TEGRA234_CLK_MGBE0_RX_PCS>,
1402 <&bpmp TEGRA234_CLK_MGBE0_TX_PCS>;
1403 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1404 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1405 "rx-pcs", "tx-pcs";
1406 resets = <&bpmp TEGRA234_RESET_MGBE0_MAC>,
1407 <&bpmp TEGRA234_RESET_MGBE0_PCS>;
1408 reset-names = "mac", "pcs";
1409 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEARD &emc>,
1410 <&mc TEGRA234_MEMORY_CLIENT_MGBEAWR &emc>;
1411 interconnect-names = "dma-mem", "write";
1412 iommus = <&smmu_niso0 TEGRA234_SID_MGBE>;
1413 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEA>;
1414 status = "disabled";
1415 };
1416
1417 ethernet@6900000 {
1418 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1419 reg = <0x0 0x06900000 0x0 0x10000>,
1420 <0x0 0x06910000 0x0 0x10000>,
1421 <0x0 0x069a0000 0x0 0x10000>;
610cdf31
TR		 1422 reg-names = "hypervisor", "mac", "xpcs";
1423 interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>;
1424 interrupt-names = "common";
1425 clocks = <&bpmp TEGRA234_CLK_MGBE1_APP>,
1426 <&bpmp TEGRA234_CLK_MGBE1_MAC>,
1427 <&bpmp TEGRA234_CLK_MGBE1_MAC_DIVIDER>,
1428 <&bpmp TEGRA234_CLK_MGBE1_PTP_REF>,
1429 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT_M>,
1430 <&bpmp TEGRA234_CLK_MGBE1_RX_INPUT>,
1431 <&bpmp TEGRA234_CLK_MGBE1_TX>,
1432 <&bpmp TEGRA234_CLK_MGBE1_EEE_PCS>,
1433 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_INPUT>,
1434 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS_M>,
1435 <&bpmp TEGRA234_CLK_MGBE1_RX_PCS>,
1436 <&bpmp TEGRA234_CLK_MGBE1_TX_PCS>;
1437 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1438 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1439 "rx-pcs", "tx-pcs";
1440 resets = <&bpmp TEGRA234_RESET_MGBE1_MAC>,
1441 <&bpmp TEGRA234_RESET_MGBE1_PCS>;
1442 reset-names = "mac", "pcs";
1443 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEBRD &emc>,
1444 <&mc TEGRA234_MEMORY_CLIENT_MGBEBWR &emc>;
1445 interconnect-names = "dma-mem", "write";
1446 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF1>;
1447 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEB>;
1448 status = "disabled";
1449 };
1450
1451 ethernet@6a00000 {
1452 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1453 reg = <0x0 0x06a00000 0x0 0x10000>,
1454 <0x0 0x06a10000 0x0 0x10000>,
1455 <0x0 0x06aa0000 0x0 0x10000>;
610cdf31
TR		 1456 reg-names = "hypervisor", "mac", "xpcs";
1457 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
1458 interrupt-names = "common";
1459 clocks = <&bpmp TEGRA234_CLK_MGBE2_APP>,
1460 <&bpmp TEGRA234_CLK_MGBE2_MAC>,
1461 <&bpmp TEGRA234_CLK_MGBE2_MAC_DIVIDER>,
1462 <&bpmp TEGRA234_CLK_MGBE2_PTP_REF>,
1463 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT_M>,
1464 <&bpmp TEGRA234_CLK_MGBE2_RX_INPUT>,
1465 <&bpmp TEGRA234_CLK_MGBE2_TX>,
1466 <&bpmp TEGRA234_CLK_MGBE2_EEE_PCS>,
1467 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_INPUT>,
1468 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS_M>,
1469 <&bpmp TEGRA234_CLK_MGBE2_RX_PCS>,
1470 <&bpmp TEGRA234_CLK_MGBE2_TX_PCS>;
1471 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1472 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1473 "rx-pcs", "tx-pcs";
1474 resets = <&bpmp TEGRA234_RESET_MGBE2_MAC>,
1475 <&bpmp TEGRA234_RESET_MGBE2_PCS>;
1476 reset-names = "mac", "pcs";
1477 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBECRD &emc>,
1478 <&mc TEGRA234_MEMORY_CLIENT_MGBECWR &emc>;
1479 interconnect-names = "dma-mem", "write";
1480 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF2>;
1481 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBEC>;
1482 status = "disabled";
1483 };
1484
1485 ethernet@6b00000 {
1486 compatible = "nvidia,tegra234-mgbe";
2838cfdd
TR		 1487 reg = <0x0 0x06b00000 0x0 0x10000>,
1488 <0x0 0x06b10000 0x0 0x10000>,
1489 <0x0 0x06ba0000 0x0 0x10000>;
610cdf31
TR		 1490 reg-names = "hypervisor", "mac", "xpcs";
1491 interrupts = <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
1492 interrupt-names = "common";
1493 clocks = <&bpmp TEGRA234_CLK_MGBE3_APP>,
1494 <&bpmp TEGRA234_CLK_MGBE3_MAC>,
1495 <&bpmp TEGRA234_CLK_MGBE3_MAC_DIVIDER>,
1496 <&bpmp TEGRA234_CLK_MGBE3_PTP_REF>,
1497 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT_M>,
1498 <&bpmp TEGRA234_CLK_MGBE3_RX_INPUT>,
1499 <&bpmp TEGRA234_CLK_MGBE3_TX>,
1500 <&bpmp TEGRA234_CLK_MGBE3_EEE_PCS>,
1501 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_INPUT>,
1502 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS_M>,
1503 <&bpmp TEGRA234_CLK_MGBE3_RX_PCS>,
1504 <&bpmp TEGRA234_CLK_MGBE3_TX_PCS>;
1505 clock-names = "mgbe", "mac", "mac-divider", "ptp-ref", "rx-input-m",
1506 "rx-input", "tx", "eee-pcs", "rx-pcs-input", "rx-pcs-m",
1507 "rx-pcs", "tx-pcs";
1508 resets = <&bpmp TEGRA234_RESET_MGBE3_MAC>,
1509 <&bpmp TEGRA234_RESET_MGBE3_PCS>;
1510 reset-names = "mac", "pcs";
1511 interconnects = <&mc TEGRA234_MEMORY_CLIENT_MGBEDRD &emc>,
1512 <&mc TEGRA234_MEMORY_CLIENT_MGBEDWR &emc>;
1513 interconnect-names = "dma-mem", "write";
1514 iommus = <&smmu_niso0 TEGRA234_SID_MGBE_VF3>;
1515 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_MGBED>;
1516 status = "disabled";
1517 };
1518
5710e16a
TR		 1519 smmu_niso1: iommu@8000000 {
1520 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd
TR		 1521 reg = <0x0 0x8000000 0x0 0x1000000>,
1522 <0x0 0x7000000 0x0 0x1000000>;
5710e16a
TR		 1523 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1524 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1525 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1526 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
1527 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1528 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1529 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1530 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1531 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1532 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1533 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1535 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1536 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1537 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1538 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1539 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1540 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1541 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1542 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1543 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1544 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1545 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1546 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1547 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1548 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1549 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1550 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1551 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1552 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1553 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1554 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1555 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1556 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1557 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1558 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1559 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1560 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1561 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1562 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1564 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1565 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1566 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1567 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1568 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1569 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1570 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1571 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1572 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1573 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1574 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1575 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1576 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1577 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1578 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1579 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1580 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1581 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1582 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1583 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1584 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1585 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1586 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1587 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1588 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1589 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1590 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1591 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1592 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1593 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1594 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1595 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1596 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1597 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1598 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1599 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1600 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1601 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1602 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1603 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1604 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1605 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1606 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1607 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1608 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1609 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1610 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1611 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1612 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1613 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1614 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1615 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1616 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1617 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1618 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1619 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1620 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1621 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1622 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1623 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1624 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1625 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1626 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1627 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1628 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1629 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1630 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1631 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1632 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1633 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1634 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1635 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1636 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1637 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1638 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1639 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1640 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1641 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1642 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1643 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1644 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1645 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1646 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1647 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1648 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1649 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1650 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1651 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
1652 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1653 stream-match-mask = <0x7f80>;
1654 #global-interrupts = <2>;
1655 #iommu-cells = <1>;
1656
1657 nvidia,memory-controller = <&mc>;
1658 status = "okay";
1659 };
1660
302e1540
SG		 1661 sce-fabric@b600000 {
1662 compatible = "nvidia,tegra234-sce-fabric";
2838cfdd 1663 reg = <0x0 0xb600000 0x0 0x40000>;
302e1540
SG		 1664 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
1665 status = "okay";
1666 };
1667
1668 rce-fabric@be00000 {
1669 compatible = "nvidia,tegra234-rce-fabric";
2838cfdd 1670 reg = <0x0 0xbe00000 0x0 0x40000>;
302e1540
SG		 1671 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
1672 status = "okay";
1673 };
1674
63944891
TR		 1675 hsp_aon: hsp@c150000 {
1676 compatible = "nvidia,tegra234-hsp", "nvidia,tegra194-hsp";
2838cfdd 1677 reg = <0x0 0x0c150000 0x0 0x90000>;
63944891
TR		 1678 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1679 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
1680 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1681 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1682 /*
1683 * Shared interrupt 0 is routed only to AON/SPE, so
1684 * we only have 4 shared interrupts for the CCPLEX.
1685 */
1686 interrupt-names = "shared1", "shared2", "shared3", "shared4";
1687 #mbox-cells = <2>;
1688 };
1689
29662d62
DP		 1690 hte_aon: hardware-timestamp@c1e0000 {
1691 compatible = "nvidia,tegra234-gte-aon";
1692 reg = <0x0 0xc1e0000 0x0 0x10000>;
1693 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1694 nvidia,int-threshold = <1>;
1695 nvidia,gpio-controller = <&gpio_aon>;
1696 #timestamp-cells = <1>;
1697 };
1698
156af9de
A		 1699 gen2_i2c: i2c@c240000 {
1700 compatible = "nvidia,tegra194-i2c";
2838cfdd 1701 reg = <0x0 0xc240000 0x0 0x100>;
156af9de 1702 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 1703 #address-cells = <1>;
1704 #size-cells = <0>;
156af9de
A		 1705 status = "disabled";
1706 clock-frequency = <100000>;
1707 clocks = <&bpmp TEGRA234_CLK_I2C2
1708 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1709 clock-names = "div-clk", "parent";
1710 assigned-clocks = <&bpmp TEGRA234_CLK_I2C2>;
1711 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1712 resets = <&bpmp TEGRA234_RESET_I2C2>;
1713 reset-names = "i2c";
8e442805
A		 1714 dmas = <&gpcdma 22>, <&gpcdma 22>;
1715 dma-names = "rx", "tx";
156af9de
A		 1716 };
1717
1718 gen8_i2c: i2c@c250000 {
1719 compatible = "nvidia,tegra194-i2c";
2838cfdd 1720 reg = <0x0 0xc250000 0x0 0x100>;
156af9de 1721 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
260e8d42
JH		 1722 #address-cells = <1>;
1723 #size-cells = <0>;
156af9de
A		 1724 status = "disabled";
1725 clock-frequency = <400000>;
1726 clocks = <&bpmp TEGRA234_CLK_I2C8
1727 &bpmp TEGRA234_CLK_PLLP_OUT0>;
1728 clock-names = "div-clk", "parent";
1729 assigned-clocks = <&bpmp TEGRA234_CLK_I2C8>;
1730 assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLP_OUT0>;
1731 resets = <&bpmp TEGRA234_RESET_I2C8>;
1732 reset-names = "i2c";
8e442805
A		 1733 dmas = <&gpcdma 0>, <&gpcdma 0>;
1734 dma-names = "rx", "tx";
156af9de
A		 1735 };
1736
63944891
TR		 1737 rtc@c2a0000 {
1738 compatible = "nvidia,tegra234-rtc", "nvidia,tegra20-rtc";
2838cfdd 1739 reg = <0x0 0x0c2a0000 0x0 0x10000>;
63944891
TR		 1740 interrupt-parent = <&pmc>;
1741 interrupts = <73 IRQ_TYPE_LEVEL_HIGH>;
e537adde
MP		 1742 clocks = <&bpmp TEGRA234_CLK_CLK_32K>;
1743 clock-names = "rtc";
63944891
TR		 1744 status = "disabled";
1745 };
1746
f0e12668
TR		 1747 gpio_aon: gpio@c2f0000 {
1748 compatible = "nvidia,tegra234-gpio-aon";
1749 reg-names = "security", "gpio";
2838cfdd
TR		 1750 reg = <0x0 0x0c2f0000 0x0 0x1000>,
1751 <0x0 0x0c2f1000 0x0 0x1000>;
f0e12668
TR		 1752 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
1753 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
1754 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
1755 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1756 #interrupt-cells = <2>;
1757 interrupt-controller;
1758 #gpio-cells = <2>;
1759 gpio-controller;
282fde00
PS		 1760 gpio-ranges = <&pinmux_aon 0 0 32>;
1761 };
1762
1763 pinmux_aon: pinmux@c300000 {
1764 compatible = "nvidia,tegra234-pinmux-aon";
1765 reg = <0x0 0xc300000 0x0 0x4000>;
f0e12668
TR		 1766 };
1767
2566d28c
JH		 1768 pwm4: pwm@c340000 {
1769 compatible = "nvidia,tegra234-pwm", "nvidia,tegra194-pwm";
2838cfdd 1770 reg = <0x0 0xc340000 0x0 0x10000>;
2566d28c 1771 clocks = <&bpmp TEGRA234_CLK_PWM4>;
2566d28c
JH		 1772 resets = <&bpmp TEGRA234_RESET_PWM4>;
1773 reset-names = "pwm";
1774 status = "disabled";
1775 #pwm-cells = <2>;
1776 };
1777
63944891
TR		 1778 pmc: pmc@c360000 {
1779 compatible = "nvidia,tegra234-pmc";
2838cfdd
TR		 1780 reg = <0x0 0x0c360000 0x0 0x10000>,
1781 <0x0 0x0c370000 0x0 0x10000>,
1782 <0x0 0x0c380000 0x0 0x10000>,
1783 <0x0 0x0c390000 0x0 0x10000>,
1784 <0x0 0x0c3a0000 0x0 0x10000>;
63944891
TR		 1785 reg-names = "pmc", "wake", "aotag", "scratch", "misc";
1786
1787 #interrupt-cells = <2>;
1788 interrupt-controller;
d71b893a 1789
d71b893a
PS		 1790 sdmmc1_1v8: sdmmc1-1v8 {
1791 pins = "sdmmc1-hv";
1792 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1793 };
1794
79ed18d9
TR		 1795 sdmmc1_3v3: sdmmc1-3v3 {
1796 pins = "sdmmc1-hv";
d71b893a
PS		 1797 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1798 };
1799
1800 sdmmc3_1v8: sdmmc3-1v8 {
1801 pins = "sdmmc3-hv";
1802 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>;
1803 };
79ed18d9
TR		 1804
1805 sdmmc3_3v3: sdmmc3-3v3 {
1806 pins = "sdmmc3-hv";
1807 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>;
1808 };
63944891
TR		 1809 };
1810
302e1540
SG		 1811 aon-fabric@c600000 {
1812 compatible = "nvidia,tegra234-aon-fabric";
2838cfdd 1813 reg = <0x0 0xc600000 0x0 0x40000>;
302e1540
SG		 1814 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1815 status = "okay";
1816 };
1817
1818 bpmp-fabric@d600000 {
1819 compatible = "nvidia,tegra234-bpmp-fabric";
2838cfdd 1820 reg = <0x0 0xd600000 0x0 0x40000>;
302e1540
SG		 1821 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1822 status = "okay";
1823 };
1824
1825 dce-fabric@de00000 {
1826 compatible = "nvidia,tegra234-sce-fabric";
2838cfdd 1827 reg = <0x0 0xde00000 0x0 0x40000>;
302e1540
SG		 1828 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>;
1829 status = "okay";
1830 };
1831
2838cfdd
TR		 1832 ccplex@e000000 {
1833 compatible = "nvidia,tegra234-ccplex-cluster";
1834 reg = <0x0 0x0e000000 0x0 0x5ffff>;
1835 nvidia,bpmp = <&bpmp>;
1836 status = "okay";
1837 };
1838
63944891
TR		 1839 gic: interrupt-controller@f400000 {
1840 compatible = "arm,gic-v3";
2838cfdd
TR		 1841 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
1842 <0x0 0x0f440000 0x0 0x200000>; /* GICR */
63944891
TR		 1843 interrupt-parent = <&gic>;
1844 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1845
1846 #redistributor-regions = <1>;
1847 #interrupt-cells = <3>;
1848 interrupt-controller;
1849 };
5710e16a 1850
58bf48a2 1851 smmu_iso: iommu@10000000 {
5710e16a 1852 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd 1853 reg = <0x0 0x10000000 0x0 0x1000000>;
5710e16a
TR		 1854 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1855 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1856 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1857 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1858 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1859 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1860 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1861 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1862 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1863 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1864 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1865 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1866 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1867 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1868 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1869 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1870 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1871 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1872 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1873 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1874 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1875 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1876 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1877 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1878 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1879 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1880 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1881 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1882 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1883 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1884 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1885 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1886 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1887 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1888 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1889 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1891 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1892 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1893 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1894 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1895 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1896 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1897 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1898 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1899 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1900 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1901 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1902 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1903 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1904 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1905 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1906 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1907 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1908 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1909 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1910 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1911 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1912 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1913 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1914 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1915 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1916 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1917 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1918 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1919 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1920 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1921 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1922 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1923 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1924 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1925 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1926 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1927 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1928 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1929 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1930 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1931 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1932 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1933 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1934 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1935 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1936 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1937 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1938 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1939 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1940 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1941 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1942 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1943 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1944 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1945 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1946 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1947 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1948 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1949 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1950 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1951 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1952 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1953 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1954 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1955 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1956 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1957 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1958 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1959 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1960 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1961 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1962 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1963 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1964 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1965 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1966 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1967 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1968 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1969 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1970 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1971 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1972 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1973 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1974 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1975 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1976 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1977 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1978 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1979 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1980 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1981 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
1982 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
1983 stream-match-mask = <0x7f80>;
1984 #global-interrupts = <1>;
1985 #iommu-cells = <1>;
1986
1987 nvidia,memory-controller = <&mc>;
1988 status = "okay";
1989 };
1990
1991 smmu_niso0: iommu@12000000 {
1992 compatible = "nvidia,tegra234-smmu", "nvidia,smmu-500";
2838cfdd
TR		 1993 reg = <0x0 0x12000000 0x0 0x1000000>,
1994 <0x0 0x11000000 0x0 0x1000000>;
5710e16a
TR		 1995 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1996 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1997 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1998 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>,
1999 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2000 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2001 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2002 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2003 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2004 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2005 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2006 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2007 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2008 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2009 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2010 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2011 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2012 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2013 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2014 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2015 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2016 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2017 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2018 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2019 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2020 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2021 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2022 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2023 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2024 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2025 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2026 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2027 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2028 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2029 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2030 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2031 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2032 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2033 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2034 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2035 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2036 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2037 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2038 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2039 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2040 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2041 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2042 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2043 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2044 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2045 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2046 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2047 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2048 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2049 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2050 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2051 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2052 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2053 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2054 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2055 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2056 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2057 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2058 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2059 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2060 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2061 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2062 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2063 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2064 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2065 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2066 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2067 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2068 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2069 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2070 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2071 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2072 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2073 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2074 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2075 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2076 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2077 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2078 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2079 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2080 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2081 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2082 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2083 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2084 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2085 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2086 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2087 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2088 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2089 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2090 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2091 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2092 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2093 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2094 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2095 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2096 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2097 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2098 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2099 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2100 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2101 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2102 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2103 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2104 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2105 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2106 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2107 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2108 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2109 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2110 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2111 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2112 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2113 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2114 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2115 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2116 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2117 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2118 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2119 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2120 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2121 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2122 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2123 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
2124 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
2125 stream-match-mask = <0x7f80>;
2126 #global-interrupts = <2>;
2127 #iommu-cells = <1>;
2128
2129 nvidia,memory-controller = <&mc>;
2130 status = "okay";
2131 };
302e1540
SG		 2132
2133 cbb-fabric@13a00000 {
2134 compatible = "nvidia,tegra234-cbb-fabric";
2838cfdd 2135 reg = <0x0 0x13a00000 0x0 0x400000>;
302e1540
SG		 2136 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
2137 status = "okay";
2138 };
63944891 2139
79ed18d9
TR		 2140 host1x@13e00000 {
2141 compatible = "nvidia,tegra234-host1x";
2142 reg = <0x0 0x13e00000 0x0 0x10000>,
2143 <0x0 0x13e10000 0x0 0x10000>,
2144 <0x0 0x13e40000 0x0 0x10000>;
2145 reg-names = "common", "hypervisor", "vm";
2146 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
2147 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
2148 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
2149 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
2150 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
2151 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
2152 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
2153 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
2154 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
2155 interrupt-names = "syncpt0", "syncpt1", "syncpt2", "syncpt3", "syncpt4",
2156 "syncpt5", "syncpt6", "syncpt7", "host1x";
2157 clocks = <&bpmp TEGRA234_CLK_HOST1X>;
2158 clock-names = "host1x";
2159
2160 #address-cells = <2>;
2161 #size-cells = <2>;
2162 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
2163
2164 interconnects = <&mc TEGRA234_MEMORY_CLIENT_HOST1XDMAR &emc>;
2165 interconnect-names = "dma-mem";
2166 iommus = <&smmu_niso1 TEGRA234_SID_HOST1X>;
361238cd 2167 dma-coherent;
79ed18d9
TR		 2168
2169 /* Context isolation domains */
2170 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2171 <1 &smmu_niso0 TEGRA234_SID_HOST1X_CTX1 1>,
2172 <2 &smmu_niso0 TEGRA234_SID_HOST1X_CTX2 1>,
2173 <3 &smmu_niso0 TEGRA234_SID_HOST1X_CTX3 1>,
2174 <4 &smmu_niso0 TEGRA234_SID_HOST1X_CTX4 1>,
2175 <5 &smmu_niso0 TEGRA234_SID_HOST1X_CTX5 1>,
2176 <6 &smmu_niso0 TEGRA234_SID_HOST1X_CTX6 1>,
2177 <7 &smmu_niso0 TEGRA234_SID_HOST1X_CTX7 1>,
2178 <8 &smmu_niso1 TEGRA234_SID_HOST1X_CTX0 1>,
2179 <9 &smmu_niso1 TEGRA234_SID_HOST1X_CTX1 1>,
2180 <10 &smmu_niso1 TEGRA234_SID_HOST1X_CTX2 1>,
2181 <11 &smmu_niso1 TEGRA234_SID_HOST1X_CTX3 1>,
2182 <12 &smmu_niso1 TEGRA234_SID_HOST1X_CTX4 1>,
2183 <13 &smmu_niso1 TEGRA234_SID_HOST1X_CTX5 1>,
2184 <14 &smmu_niso1 TEGRA234_SID_HOST1X_CTX6 1>,
2185 <15 &smmu_niso1 TEGRA234_SID_HOST1X_CTX7 1>;
2186
2187 vic@15340000 {
2188 compatible = "nvidia,tegra234-vic";
2189 reg = <0x0 0x15340000 0x0 0x00040000>;
2190 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
2191 clocks = <&bpmp TEGRA234_CLK_VIC>;
2192 clock-names = "vic";
2193 resets = <&bpmp TEGRA234_RESET_VIC>;
2194 reset-names = "vic";
2195
2196 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_VIC>;
2197 interconnects = <&mc TEGRA234_MEMORY_CLIENT_VICSRD &emc>,
2198 <&mc TEGRA234_MEMORY_CLIENT_VICSWR &emc>;
2199 interconnect-names = "dma-mem", "write";
2200 iommus = <&smmu_niso1 TEGRA234_SID_VIC>;
2201 dma-coherent;
2202 };
2203
2204 nvdec@15480000 {
2205 compatible = "nvidia,tegra234-nvdec";
2206 reg = <0x0 0x15480000 0x0 0x00040000>;
2207 clocks = <&bpmp TEGRA234_CLK_NVDEC>,
2208 <&bpmp TEGRA234_CLK_FUSE>,
2209 <&bpmp TEGRA234_CLK_TSEC_PKA>;
2210 clock-names = "nvdec", "fuse", "tsec_pka";
2211 resets = <&bpmp TEGRA234_RESET_NVDEC>;
2212 reset-names = "nvdec";
2213 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_NVDEC>;
2214 interconnects = <&mc TEGRA234_MEMORY_CLIENT_NVDECSRD &emc>,
2215 <&mc TEGRA234_MEMORY_CLIENT_NVDECSWR &emc>;
2216 interconnect-names = "dma-mem", "write";
2217 iommus = <&smmu_niso1 TEGRA234_SID_NVDEC>;
2218 dma-coherent;
2219
2220 nvidia,memory-controller = <&mc>;
2221
2222 /*
2223 * Placeholder values that firmware needs to update with the real
2224 * offsets parsed from the microcode headers.
2225 */
2226 nvidia,bl-manifest-offset = <0>;
2227 nvidia,bl-data-offset = <0>;
2228 nvidia,bl-code-offset = <0>;
2229 nvidia,os-manifest-offset = <0>;
2230 nvidia,os-data-offset = <0>;
2231 nvidia,os-code-offset = <0>;
2232
2233 /*
2234 * Firmware needs to set this to "okay" once the above values have
2235 * been updated.
2236 */
2237 status = "disabled";
2238 };
2239 };
2240
2838cfdd
TR		 2241 pcie@140a0000 {
2242 compatible = "nvidia,tegra234-pcie";
2243 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CA>;
2244 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
2245 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
2246 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2247 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2248 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2249 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
962c400d 2250
2838cfdd
TR		 2251 #address-cells = <3>;
2252 #size-cells = <2>;
2253 device_type = "pci";
2254 num-lanes = <4>;
2255 num-viewport = <8>;
2256 linux,pci-domain = <8>;
ec142c44 2257
2838cfdd
TR		 2258 clocks = <&bpmp TEGRA234_CLK_PEX2_C8_CORE>;
2259 clock-names = "core";
ec142c44 2260
2838cfdd
TR		 2261 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_8_APB>,
2262 <&bpmp TEGRA234_RESET_PEX2_CORE_8>;
2263 reset-names = "apb", "core";
ec142c44 2264
2838cfdd
TR		 2265 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2266 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2267 interrupt-names = "intr", "msi";
ec142c44 2268
2838cfdd
TR		 2269 #interrupt-cells = <1>;
2270 interrupt-map-mask = <0 0 0 0>;
2271 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2272
2838cfdd 2273 nvidia,bpmp = <&bpmp 8>;
ec142c44 2274
2838cfdd
TR		 2275 nvidia,aspm-cmrt-us = <60>;
2276 nvidia,aspm-pwr-on-t-us = <20>;
2277 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2278
2838cfdd 2279 bus-range = <0x0 0xff>;
ec142c44 2280
2838cfdd
TR		 2281 ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2282 <0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2283 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2284
2838cfdd
TR		 2285 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE8AR &emc>,
2286 <&mc TEGRA234_MEMORY_CLIENT_PCIE8AW &emc>;
2287 interconnect-names = "dma-mem", "write";
2288 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2289 iommu-map-mask = <0x0>;
2290 dma-coherent;
ec142c44 2291
2838cfdd
TR		 2292 status = "disabled";
2293 };
ec142c44 2294
2838cfdd
TR		 2295 pcie@140c0000 {
2296 compatible = "nvidia,tegra234-pcie";
2297 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CB>;
2298 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
2299 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
2300 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2301 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2302 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2303 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2304
2838cfdd
TR		 2305 #address-cells = <3>;
2306 #size-cells = <2>;
2307 device_type = "pci";
2308 num-lanes = <4>;
2309 num-viewport = <8>;
2310 linux,pci-domain = <9>;
ec142c44 2311
2838cfdd
TR		 2312 clocks = <&bpmp TEGRA234_CLK_PEX2_C9_CORE>;
2313 clock-names = "core";
ec142c44 2314
2838cfdd
TR		 2315 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_9_APB>,
2316 <&bpmp TEGRA234_RESET_PEX2_CORE_9>;
2317 reset-names = "apb", "core";
ec142c44 2318
2838cfdd
TR		 2319 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2320 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2321 interrupt-names = "intr", "msi";
ec142c44 2322
2838cfdd
TR		 2323 #interrupt-cells = <1>;
2324 interrupt-map-mask = <0 0 0 0>;
2325 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2326
2838cfdd 2327 nvidia,bpmp = <&bpmp 9>;
ec142c44 2328
2838cfdd
TR		 2329 nvidia,aspm-cmrt-us = <60>;
2330 nvidia,aspm-pwr-on-t-us = <20>;
2331 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2332
2838cfdd 2333 bus-range = <0x0 0xff>;
ec142c44 2334
2838cfdd
TR		 2335 ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (11264 MB) */
2336 <0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2337 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2338
2838cfdd
TR		 2339 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE9AR &emc>,
2340 <&mc TEGRA234_MEMORY_CLIENT_PCIE9AW &emc>;
2341 interconnect-names = "dma-mem", "write";
2342 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2343 iommu-map-mask = <0x0>;
2344 dma-coherent;
ec142c44 2345
2838cfdd
TR		 2346 status = "disabled";
2347 };
ec142c44 2348
2838cfdd
TR		 2349 pcie@140e0000 {
2350 compatible = "nvidia,tegra234-pcie";
2351 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2352 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2353 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
2354 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2355 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2356 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2357 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2358
2838cfdd
TR		 2359 #address-cells = <3>;
2360 #size-cells = <2>;
2361 device_type = "pci";
2362 num-lanes = <4>;
2363 num-viewport = <8>;
2364 linux,pci-domain = <10>;
ec142c44 2365
2838cfdd
TR		 2366 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2367 clock-names = "core";
ec142c44 2368
2838cfdd
TR		 2369 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2370 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2371 reset-names = "apb", "core";
ec142c44 2372
2838cfdd
TR		 2373 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2374 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2375 interrupt-names = "intr", "msi";
ec142c44 2376
2838cfdd
TR		 2377 #interrupt-cells = <1>;
2378 interrupt-map-mask = <0 0 0 0>;
2379 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2380
2838cfdd 2381 nvidia,bpmp = <&bpmp 10>;
ec142c44 2382
2838cfdd
TR		 2383 nvidia,aspm-cmrt-us = <60>;
2384 nvidia,aspm-pwr-on-t-us = <20>;
2385 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2386
2838cfdd 2387 bus-range = <0x0 0xff>;
ec142c44 2388
2838cfdd
TR		 2389 ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2390 <0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2391 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2392
2838cfdd
TR		 2393 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2394 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2395 interconnect-names = "dma-mem", "write";
2396 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2397 iommu-map-mask = <0x0>;
2398 dma-coherent;
ec142c44 2399
2838cfdd
TR		 2400 status = "disabled";
2401 };
ec142c44 2402
2838cfdd
TR		 2403 pcie-ep@140e0000 {
2404 compatible = "nvidia,tegra234-pcie-ep";
2405 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4CC>;
2406 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2407 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2408 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
2409 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2410 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2411
2838cfdd 2412 num-lanes = <4>;
ec142c44 2413
2838cfdd
TR		 2414 clocks = <&bpmp TEGRA234_CLK_PEX2_C10_CORE>;
2415 clock-names = "core";
ec142c44 2416
2838cfdd
TR		 2417 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_10_APB>,
2418 <&bpmp TEGRA234_RESET_PEX2_CORE_10>;
2419 reset-names = "apb", "core";
ec142c44 2420
2838cfdd
TR		 2421 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2422 interrupt-names = "intr";
ec142c44 2423
2838cfdd 2424 nvidia,bpmp = <&bpmp 10>;
ec142c44 2425
2838cfdd
TR		 2426 nvidia,enable-ext-refclk;
2427 nvidia,aspm-cmrt-us = <60>;
2428 nvidia,aspm-pwr-on-t-us = <20>;
2429 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2430
2838cfdd
TR		 2431 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE10AR &emc>,
2432 <&mc TEGRA234_MEMORY_CLIENT_PCIE10AW &emc>;
2433 interconnect-names = "dma-mem", "write";
2434 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2435 iommu-map-mask = <0x0>;
2436 dma-coherent;
ec142c44 2437
2838cfdd
TR		 2438 status = "disabled";
2439 };
ec142c44 2440
2838cfdd
TR		 2441 pcie@14100000 {
2442 compatible = "nvidia,tegra234-pcie";
2443 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2444 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2445 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2446 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2447 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
2448 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
2449 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2450
2838cfdd
TR		 2451 #address-cells = <3>;
2452 #size-cells = <2>;
2453 device_type = "pci";
2454 num-lanes = <1>;
2455 num-viewport = <8>;
2456 linux,pci-domain = <1>;
ec142c44 2457
2838cfdd
TR		 2458 clocks = <&bpmp TEGRA234_CLK_PEX0_C1_CORE>;
2459 clock-names = "core";
ec142c44 2460
2838cfdd
TR		 2461 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_1_APB>,
2462 <&bpmp TEGRA234_RESET_PEX0_CORE_1>;
2463 reset-names = "apb", "core";
ec142c44 2464
2838cfdd
TR		 2465 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2466 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2467 interrupt-names = "intr", "msi";
ec142c44 2468
2838cfdd
TR		 2469 #interrupt-cells = <1>;
2470 interrupt-map-mask = <0 0 0 0>;
2471 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2472
2838cfdd 2473 nvidia,bpmp = <&bpmp 1>;
ec142c44 2474
2838cfdd
TR		 2475 nvidia,aspm-cmrt-us = <60>;
2476 nvidia,aspm-pwr-on-t-us = <20>;
2477 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2478
2838cfdd 2479 bus-range = <0x0 0xff>;
ec142c44 2480
2838cfdd
TR		 2481 ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2482 <0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2483 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2484
2838cfdd
TR		 2485 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE1R &emc>,
2486 <&mc TEGRA234_MEMORY_CLIENT_PCIE1W &emc>;
2487 interconnect-names = "dma-mem", "write";
2488 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2489 iommu-map-mask = <0x0>;
2490 dma-coherent;
ec142c44 2491
2838cfdd
TR		 2492 status = "disabled";
2493 };
ec142c44 2494
2838cfdd
TR		 2495 pcie@14120000 {
2496 compatible = "nvidia,tegra234-pcie";
2497 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2498 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2499 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2500 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2501 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
2502 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
2503 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2504
2838cfdd
TR		 2505 #address-cells = <3>;
2506 #size-cells = <2>;
2507 device_type = "pci";
2508 num-lanes = <1>;
2509 num-viewport = <8>;
2510 linux,pci-domain = <2>;
ec142c44 2511
2838cfdd
TR		 2512 clocks = <&bpmp TEGRA234_CLK_PEX0_C2_CORE>;
2513 clock-names = "core";
ec142c44 2514
2838cfdd
TR		 2515 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_2_APB>,
2516 <&bpmp TEGRA234_RESET_PEX0_CORE_2>;
2517 reset-names = "apb", "core";
ec142c44 2518
2838cfdd
TR		 2519 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2520 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2521 interrupt-names = "intr", "msi";
ec142c44 2522
2838cfdd
TR		 2523 #interrupt-cells = <1>;
2524 interrupt-map-mask = <0 0 0 0>;
2525 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2526
2838cfdd 2527 nvidia,bpmp = <&bpmp 2>;
ec142c44 2528
2838cfdd
TR		 2529 nvidia,aspm-cmrt-us = <60>;
2530 nvidia,aspm-pwr-on-t-us = <20>;
2531 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2532
2838cfdd 2533 bus-range = <0x0 0xff>;
ec142c44 2534
2838cfdd
TR		 2535 ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2536 <0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2537 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2538
2838cfdd
TR		 2539 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE2AR &emc>,
2540 <&mc TEGRA234_MEMORY_CLIENT_PCIE2AW &emc>;
2541 interconnect-names = "dma-mem", "write";
2542 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2543 iommu-map-mask = <0x0>;
2544 dma-coherent;
ec142c44 2545
2838cfdd
TR		 2546 status = "disabled";
2547 };
ec142c44 2548
2838cfdd
TR		 2549 pcie@14140000 {
2550 compatible = "nvidia,tegra234-pcie";
2551 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX1A>;
2552 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2553 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2554 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2555 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
2556 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2557 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2558
2838cfdd
TR		 2559 #address-cells = <3>;
2560 #size-cells = <2>;
2561 device_type = "pci";
2562 num-lanes = <1>;
2563 num-viewport = <8>;
2564 linux,pci-domain = <3>;
ec142c44 2565
2838cfdd
TR		 2566 clocks = <&bpmp TEGRA234_CLK_PEX0_C3_CORE>;
2567 clock-names = "core";
ec142c44 2568
2838cfdd
TR		 2569 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_3_APB>,
2570 <&bpmp TEGRA234_RESET_PEX0_CORE_3>;
2571 reset-names = "apb", "core";
ec142c44 2572
2838cfdd
TR		 2573 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2574 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2575 interrupt-names = "intr", "msi";
ec142c44 2576
2838cfdd
TR		 2577 #interrupt-cells = <1>;
2578 interrupt-map-mask = <0 0 0 0>;
2579 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2580
2838cfdd 2581 nvidia,bpmp = <&bpmp 3>;
ec142c44 2582
2838cfdd
TR		 2583 nvidia,aspm-cmrt-us = <60>;
2584 nvidia,aspm-pwr-on-t-us = <20>;
2585 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2586
2838cfdd 2587 bus-range = <0x0 0xff>;
ec142c44 2588
2838cfdd
TR		 2589 ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 MB) */
2590 <0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2591 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2592
2838cfdd
TR		 2593 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE3R &emc>,
2594 <&mc TEGRA234_MEMORY_CLIENT_PCIE3W &emc>;
2595 interconnect-names = "dma-mem", "write";
2596 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2597 iommu-map-mask = <0x0>;
2598 dma-coherent;
ec142c44 2599
2838cfdd
TR		 2600 status = "disabled";
2601 };
ec142c44 2602
2838cfdd
TR		 2603 pcie@14160000 {
2604 compatible = "nvidia,tegra234-pcie";
2605 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
2606 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2607 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2608 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2609 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2610 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2611 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2612
2838cfdd
TR		 2613 #address-cells = <3>;
2614 #size-cells = <2>;
2615 device_type = "pci";
2616 num-lanes = <4>;
2617 num-viewport = <8>;
2618 linux,pci-domain = <4>;
ec142c44 2619
2838cfdd
TR		 2620 clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
2621 clock-names = "core";
ec142c44 2622
2838cfdd
TR		 2623 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
2624 <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
2625 reset-names = "apb", "core";
ec142c44 2626
2838cfdd
TR		 2627 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2628 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2629 interrupt-names = "intr", "msi";
ec142c44 2630
2838cfdd
TR		 2631 #interrupt-cells = <1>;
2632 interrupt-map-mask = <0 0 0 0>;
2633 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2634
2838cfdd 2635 nvidia,bpmp = <&bpmp 4>;
ec142c44 2636
2838cfdd
TR		 2637 nvidia,aspm-cmrt-us = <60>;
2638 nvidia,aspm-pwr-on-t-us = <20>;
2639 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2640
2838cfdd 2641 bus-range = <0x0 0xff>;
ec142c44 2642
2838cfdd
TR		 2643 ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2644 <0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2645 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2646
2838cfdd
TR		 2647 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE4R &emc>,
2648 <&mc TEGRA234_MEMORY_CLIENT_PCIE4W &emc>;
2649 interconnect-names = "dma-mem", "write";
2650 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2651 iommu-map-mask = <0x0>;
2652 dma-coherent;
2653
2654 status = "disabled";
2655 };
ec142c44 2656
2838cfdd
TR		 2657 pcie@14180000 {
2658 compatible = "nvidia,tegra234-pcie";
2659 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BA>;
2660 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2661 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2662 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2663 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2664 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2665 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2666
2838cfdd
TR		 2667 #address-cells = <3>;
2668 #size-cells = <2>;
2669 device_type = "pci";
2670 num-lanes = <4>;
2671 num-viewport = <8>;
2672 linux,pci-domain = <0>;
ec142c44 2673
2838cfdd
TR		 2674 clocks = <&bpmp TEGRA234_CLK_PEX0_C0_CORE>;
2675 clock-names = "core";
ec142c44 2676
2838cfdd
TR		 2677 resets = <&bpmp TEGRA234_RESET_PEX0_CORE_0_APB>,
2678 <&bpmp TEGRA234_RESET_PEX0_CORE_0>;
2679 reset-names = "apb", "core";
ec142c44 2680
2838cfdd
TR		 2681 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2682 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2683 interrupt-names = "intr", "msi";
ec142c44 2684
2838cfdd
TR		 2685 #interrupt-cells = <1>;
2686 interrupt-map-mask = <0 0 0 0>;
2687 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2688
2838cfdd 2689 nvidia,bpmp = <&bpmp 0>;
ec142c44 2690
2838cfdd
TR		 2691 nvidia,aspm-cmrt-us = <60>;
2692 nvidia,aspm-pwr-on-t-us = <20>;
2693 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2694
2838cfdd 2695 bus-range = <0x0 0xff>;
ec142c44 2696
2838cfdd
TR		 2697 ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2698 <0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2699 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2700
2838cfdd
TR		 2701 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE0R &emc>,
2702 <&mc TEGRA234_MEMORY_CLIENT_PCIE0W &emc>;
2703 interconnect-names = "dma-mem", "write";
2704 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2705 iommu-map-mask = <0x0>;
2706 dma-coherent;
2707
2708 status = "disabled";
2709 };
ec142c44 2710
2838cfdd
TR		 2711 pcie@141a0000 {
2712 compatible = "nvidia,tegra234-pcie";
2713 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2714 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2715 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2716 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2717 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2718 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2719 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2720
2838cfdd
TR		 2721 #address-cells = <3>;
2722 #size-cells = <2>;
2723 device_type = "pci";
2724 num-lanes = <8>;
2725 num-viewport = <8>;
2726 linux,pci-domain = <5>;
ec142c44 2727
2838cfdd
TR		 2728 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2729 clock-names = "core";
ec142c44 2730
2838cfdd
TR		 2731 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2732 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2733 reset-names = "apb", "core";
ec142c44 2734
2838cfdd
TR		 2735 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2736 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2737 interrupt-names = "intr", "msi";
ec142c44 2738
2838cfdd
TR		 2739 #interrupt-cells = <1>;
2740 interrupt-map-mask = <0 0 0 0>;
2741 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2742
2838cfdd 2743 nvidia,bpmp = <&bpmp 5>;
ec142c44 2744
2838cfdd
TR		 2745 nvidia,aspm-cmrt-us = <60>;
2746 nvidia,aspm-pwr-on-t-us = <20>;
2747 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2748
2838cfdd 2749 bus-range = <0x0 0xff>;
ec142c44 2750
2838cfdd
TR		 2751 ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (12928 MB) */
2752 <0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2753 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2754
2838cfdd
TR		 2755 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2756 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2757 interconnect-names = "dma-mem", "write";
2758 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2759 iommu-map-mask = <0x0>;
2760 dma-coherent;
2761
2762 status = "disabled";
2763 };
ec142c44 2764
2838cfdd
TR		 2765 pcie-ep@141a0000 {
2766 compatible = "nvidia,tegra234-pcie-ep";
2767 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>;
2768 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2769 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2770 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2771 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2772 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2773
2838cfdd 2774 num-lanes = <8>;
ec142c44 2775
2838cfdd
TR		 2776 clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>;
2777 clock-names = "core";
ec142c44 2778
2838cfdd
TR		 2779 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>,
2780 <&bpmp TEGRA234_RESET_PEX1_CORE_5>;
2781 reset-names = "apb", "core";
ec142c44 2782
2838cfdd
TR		 2783 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2784 interrupt-names = "intr";
ec142c44 2785
2838cfdd 2786 nvidia,bpmp = <&bpmp 5>;
ec142c44 2787
2838cfdd
TR		 2788 nvidia,enable-ext-refclk;
2789 nvidia,aspm-cmrt-us = <60>;
2790 nvidia,aspm-pwr-on-t-us = <20>;
2791 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2792
2838cfdd
TR		 2793 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE5R &emc>,
2794 <&mc TEGRA234_MEMORY_CLIENT_PCIE5W &emc>;
2795 interconnect-names = "dma-mem", "write";
2796 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2797 iommu-map-mask = <0x0>;
2798 dma-coherent;
ec142c44 2799
2838cfdd
TR		 2800 status = "disabled";
2801 };
ec142c44 2802
2838cfdd
TR		 2803 pcie@141c0000 {
2804 compatible = "nvidia,tegra234-pcie";
2805 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2806 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2807 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2808 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2809 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2810 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2811 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2812
2838cfdd
TR		 2813 #address-cells = <3>;
2814 #size-cells = <2>;
2815 device_type = "pci";
2816 num-lanes = <4>;
2817 num-viewport = <8>;
2818 linux,pci-domain = <6>;
ec142c44 2819
2838cfdd
TR		 2820 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2821 clock-names = "core";
ec142c44 2822
2838cfdd
TR		 2823 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2824 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2825 reset-names = "apb", "core";
ec142c44 2826
2838cfdd
TR		 2827 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2828 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2829 interrupt-names = "intr", "msi";
ec142c44 2830
2838cfdd
TR		 2831 #interrupt-cells = <1>;
2832 interrupt-map-mask = <0 0 0 0>;
2833 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2834
2838cfdd 2835 nvidia,bpmp = <&bpmp 6>;
ec142c44 2836
2838cfdd
TR		 2837 nvidia,aspm-cmrt-us = <60>;
2838 nvidia,aspm-pwr-on-t-us = <20>;
2839 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2840
2838cfdd 2841 bus-range = <0x0 0xff>;
ec142c44 2842
2838cfdd
TR		 2843 ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (11904 MB) */
2844 <0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2845 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2846
2838cfdd
TR		 2847 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2848 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2849 interconnect-names = "dma-mem", "write";
2850 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2851 iommu-map-mask = <0x0>;
2852 dma-coherent;
2853
2854 status = "disabled";
2855 };
ec142c44 2856
2838cfdd
TR		 2857 pcie-ep@141c0000 {
2858 compatible = "nvidia,tegra234-pcie-ep";
2859 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4A>;
2860 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2861 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2862 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
2863 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2864 reg-names = "appl", "atu_dma", "dbi", "addr_space";
ec142c44 2865
2838cfdd 2866 num-lanes = <4>;
ec142c44 2867
2838cfdd
TR		 2868 clocks = <&bpmp TEGRA234_CLK_PEX1_C6_CORE>;
2869 clock-names = "core";
ec142c44 2870
2838cfdd
TR		 2871 resets = <&bpmp TEGRA234_RESET_PEX1_CORE_6_APB>,
2872 <&bpmp TEGRA234_RESET_PEX1_CORE_6>;
2873 reset-names = "apb", "core";
ec142c44 2874
2838cfdd
TR		 2875 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2876 interrupt-names = "intr";
ec142c44 2877
2838cfdd 2878 nvidia,bpmp = <&bpmp 6>;
ec142c44 2879
2838cfdd
TR		 2880 nvidia,enable-ext-refclk;
2881 nvidia,aspm-cmrt-us = <60>;
2882 nvidia,aspm-pwr-on-t-us = <20>;
2883 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2884
2838cfdd
TR		 2885 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE6AR &emc>,
2886 <&mc TEGRA234_MEMORY_CLIENT_PCIE6AW &emc>;
2887 interconnect-names = "dma-mem", "write";
2888 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2889 iommu-map-mask = <0x0>;
2890 dma-coherent;
ec142c44 2891
2838cfdd
TR		 2892 status = "disabled";
2893 };
ec142c44 2894
2838cfdd
TR		 2895 pcie@141e0000 {
2896 compatible = "nvidia,tegra234-pcie";
2897 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2898 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2899 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2900 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2901 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2902 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2903 reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
ec142c44 2904
2838cfdd
TR		 2905 #address-cells = <3>;
2906 #size-cells = <2>;
2907 device_type = "pci";
2908 num-lanes = <8>;
2909 num-viewport = <8>;
2910 linux,pci-domain = <7>;
ec142c44 2911
2838cfdd
TR		 2912 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2913 clock-names = "core";
ec142c44 2914
2838cfdd
TR		 2915 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2916 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2917 reset-names = "apb", "core";
ec142c44 2918
2838cfdd
TR		 2919 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
2920 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
2921 interrupt-names = "intr", "msi";
ec142c44 2922
2838cfdd
TR		 2923 #interrupt-cells = <1>;
2924 interrupt-map-mask = <0 0 0 0>;
2925 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
ec142c44 2926
2838cfdd 2927 nvidia,bpmp = <&bpmp 7>;
ec142c44 2928
2838cfdd
TR		 2929 nvidia,aspm-cmrt-us = <60>;
2930 nvidia,aspm-pwr-on-t-us = <20>;
2931 nvidia,aspm-l0s-entrance-latency-us = <3>;
ec142c44 2932
2838cfdd 2933 bus-range = <0x0 0xff>;
ec142c44 2934
2838cfdd
TR		 2935 ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832 MB) */
2936 <0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2937 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
ec142c44 2938
2838cfdd
TR		 2939 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2940 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2941 interconnect-names = "dma-mem", "write";
2942 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2943 iommu-map-mask = <0x0>;
2944 dma-coherent;
2945
2946 status = "disabled";
2947 };
2948
2949 pcie-ep@141e0000 {
2950 compatible = "nvidia,tegra234-pcie-ep";
2951 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8B>;
2952 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2953 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2954 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
2955 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2956 reg-names = "appl", "atu_dma", "dbi", "addr_space";
2957
2958 num-lanes = <8>;
2959
2960 clocks = <&bpmp TEGRA234_CLK_PEX2_C7_CORE>;
2961 clock-names = "core";
ec142c44 2962
2838cfdd
TR		 2963 resets = <&bpmp TEGRA234_RESET_PEX2_CORE_7_APB>,
2964 <&bpmp TEGRA234_RESET_PEX2_CORE_7>;
2965 reset-names = "apb", "core";
ec142c44 2966
2838cfdd
TR		 2967 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
2968 interrupt-names = "intr";
ec142c44 2969
2838cfdd 2970 nvidia,bpmp = <&bpmp 7>;
ec142c44 2971
2838cfdd
TR		 2972 nvidia,enable-ext-refclk;
2973 nvidia,aspm-cmrt-us = <60>;
2974 nvidia,aspm-pwr-on-t-us = <20>;
2975 nvidia,aspm-l0s-entrance-latency-us = <3>;
2976
2977 interconnects = <&mc TEGRA234_MEMORY_CLIENT_PCIE7AR &emc>,
2978 <&mc TEGRA234_MEMORY_CLIENT_PCIE7AW &emc>;
2979 interconnect-names = "dma-mem", "write";
2980 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
2981 iommu-map-mask = <0x0>;
2982 dma-coherent;
2983
2984 status = "disabled";
2985 };
ec142c44
VS		 2986 };
2987
7fa30752 2988 sram@40000000 {
63944891 2989 compatible = "nvidia,tegra234-sysram", "mmio-sram";
98094be1 2990 reg = <0x0 0x40000000 0x0 0x80000>;
2838cfdd 2991
63944891
TR		 2992 #address-cells = <1>;
2993 #size-cells = <1>;
98094be1 2994 ranges = <0x0 0x0 0x40000000 0x80000>;
2838cfdd 2995
61192a9d 2996 no-memory-wc;
63944891 2997
98094be1
MP		 2998 cpu_bpmp_tx: sram@70000 {
2999 reg = <0x70000 0x1000>;
63944891
TR		 3000 label = "cpu-bpmp-tx";
3001 pool;
3002 };
3003
98094be1
MP		 3004 cpu_bpmp_rx: sram@71000 {
3005 reg = <0x71000 0x1000>;
63944891
TR		 3006 label = "cpu-bpmp-rx";
3007 pool;
3008 };
3009 };
3010
3011 bpmp: bpmp {
3012 compatible = "nvidia,tegra234-bpmp", "nvidia,tegra186-bpmp";
3013 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
3014 TEGRA_HSP_DB_MASTER_BPMP>;
7fa30752 3015 shmem = <&cpu_bpmp_tx>, <&cpu_bpmp_rx>;
63944891
TR		 3016 #clock-cells = <1>;
3017 #reset-cells = <1>;
3018 #power-domain-cells = <1>;
6de481e5
TR		 3019 interconnects = <&mc TEGRA234_MEMORY_CLIENT_BPMPR &emc>,
3020 <&mc TEGRA234_MEMORY_CLIENT_BPMPW &emc>,
3021 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAR &emc>,
3022 <&mc TEGRA234_MEMORY_CLIENT_BPMPDMAW &emc>;
3023 interconnect-names = "read", "write", "dma-mem", "dma-write";
5710e16a 3024 iommus = <&smmu_niso1 TEGRA234_SID_BPMP>;
63944891
TR		 3025
3026 bpmp_i2c: i2c {
3027 compatible = "nvidia,tegra186-bpmp-i2c";
3028 nvidia,bpmp-bus-id = <5>;
3029 #address-cells = <1>;
3030 #size-cells = <0>;
3031 };
09d99078
TR		 3032
3033 bpmp_thermal: thermal {
3034 compatible = "nvidia,tegra186-bpmp-thermal";
3035 #thermal-sensor-cells = <1>;
3036 };
63944891
TR		 3037 };
3038
3039 cpus {
3040 #address-cells = <1>;
3041 #size-cells = <0>;
3042
a12cf5c3
TR		 3043 cpu0_0: cpu@0 {
3044 compatible = "arm,cortex-a78";
63944891 3045 device_type = "cpu";
a12cf5c3 3046 reg = <0x00000>;
63944891
TR		 3047
3048 enable-method = "psci";
a12cf5c3 3049
1582e1d1
SG		 3050 operating-points-v2 = <&cl0_opp_tbl>;
3051 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
3052
a12cf5c3
TR		 3053 i-cache-size = <65536>;
3054 i-cache-line-size = <64>;
3055 i-cache-sets = <256>;
3056 d-cache-size = <65536>;
3057 d-cache-line-size = <64>;
3058 d-cache-sets = <256>;
3059 next-level-cache = <&l2c0_0>;
3060 };
3061
3062 cpu0_1: cpu@100 {
3063 compatible = "arm,cortex-a78";
3064 device_type = "cpu";
3065 reg = <0x00100>;
3066
3067 enable-method = "psci";
3068
1582e1d1
SG		 3069 operating-points-v2 = <&cl0_opp_tbl>;
3070 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
3071
a12cf5c3
TR		 3072 i-cache-size = <65536>;
3073 i-cache-line-size = <64>;
3074 i-cache-sets = <256>;
3075 d-cache-size = <65536>;
3076 d-cache-line-size = <64>;
3077 d-cache-sets = <256>;
3078 next-level-cache = <&l2c0_1>;
63944891 3079 };
a12cf5c3
TR		 3080
3081 cpu0_2: cpu@200 {
3082 compatible = "arm,cortex-a78";
3083 device_type = "cpu";
3084 reg = <0x00200>;
3085
3086 enable-method = "psci";
3087
1582e1d1
SG		 3088 operating-points-v2 = <&cl0_opp_tbl>;
3089 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
3090
a12cf5c3
TR		 3091 i-cache-size = <65536>;
3092 i-cache-line-size = <64>;
3093 i-cache-sets = <256>;
3094 d-cache-size = <65536>;
3095 d-cache-line-size = <64>;
3096 d-cache-sets = <256>;
3097 next-level-cache = <&l2c0_2>;
3098 };
3099
3100 cpu0_3: cpu@300 {
3101 compatible = "arm,cortex-a78";
3102 device_type = "cpu";
3103 reg = <0x00300>;
3104
3105 enable-method = "psci";
3106
1582e1d1
SG		 3107 operating-points-v2 = <&cl0_opp_tbl>;
3108 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER0 &emc>;
3109
a12cf5c3
TR		 3110 i-cache-size = <65536>;
3111 i-cache-line-size = <64>;
3112 i-cache-sets = <256>;
3113 d-cache-size = <65536>;
3114 d-cache-line-size = <64>;
3115 d-cache-sets = <256>;
3116 next-level-cache = <&l2c0_3>;
3117 };
3118
3119 cpu1_0: cpu@10000 {
3120 compatible = "arm,cortex-a78";
3121 device_type = "cpu";
3122 reg = <0x10000>;
3123
3124 enable-method = "psci";
3125
1582e1d1
SG		 3126 operating-points-v2 = <&cl1_opp_tbl>;
3127 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
3128
a12cf5c3
TR		 3129 i-cache-size = <65536>;
3130 i-cache-line-size = <64>;
3131 i-cache-sets = <256>;
3132 d-cache-size = <65536>;
3133 d-cache-line-size = <64>;
3134 d-cache-sets = <256>;
3135 next-level-cache = <&l2c1_0>;
3136 };
3137
3138 cpu1_1: cpu@10100 {
3139 compatible = "arm,cortex-a78";
3140 device_type = "cpu";
3141 reg = <0x10100>;
3142
3143 enable-method = "psci";
3144
1582e1d1
SG		 3145 operating-points-v2 = <&cl1_opp_tbl>;
3146 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
3147
a12cf5c3
TR		 3148 i-cache-size = <65536>;
3149 i-cache-line-size = <64>;
3150 i-cache-sets = <256>;
3151 d-cache-size = <65536>;
3152 d-cache-line-size = <64>;
3153 d-cache-sets = <256>;
3154 next-level-cache = <&l2c1_1>;
3155 };
3156
3157 cpu1_2: cpu@10200 {
3158 compatible = "arm,cortex-a78";
3159 device_type = "cpu";
3160 reg = <0x10200>;
3161
3162 enable-method = "psci";
3163
1582e1d1
SG		 3164 operating-points-v2 = <&cl1_opp_tbl>;
3165 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
3166
a12cf5c3
TR		 3167 i-cache-size = <65536>;
3168 i-cache-line-size = <64>;
3169 i-cache-sets = <256>;
3170 d-cache-size = <65536>;
3171 d-cache-line-size = <64>;
3172 d-cache-sets = <256>;
3173 next-level-cache = <&l2c1_2>;
3174 };
3175
3176 cpu1_3: cpu@10300 {
3177 compatible = "arm,cortex-a78";
3178 device_type = "cpu";
3179 reg = <0x10300>;
3180
3181 enable-method = "psci";
3182
1582e1d1
SG		 3183 operating-points-v2 = <&cl1_opp_tbl>;
3184 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER1 &emc>;
3185
a12cf5c3
TR		 3186 i-cache-size = <65536>;
3187 i-cache-line-size = <64>;
3188 i-cache-sets = <256>;
3189 d-cache-size = <65536>;
3190 d-cache-line-size = <64>;
3191 d-cache-sets = <256>;
3192 next-level-cache = <&l2c1_3>;
3193 };
3194
3195 cpu2_0: cpu@20000 {
3196 compatible = "arm,cortex-a78";
3197 device_type = "cpu";
3198 reg = <0x20000>;
3199
3200 enable-method = "psci";
3201
1582e1d1
SG		 3202 operating-points-v2 = <&cl2_opp_tbl>;
3203 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
3204
a12cf5c3
TR		 3205 i-cache-size = <65536>;
3206 i-cache-line-size = <64>;
3207 i-cache-sets = <256>;
3208 d-cache-size = <65536>;
3209 d-cache-line-size = <64>;
3210 d-cache-sets = <256>;
3211 next-level-cache = <&l2c2_0>;
3212 };
3213
3214 cpu2_1: cpu@20100 {
3215 compatible = "arm,cortex-a78";
3216 device_type = "cpu";
3217 reg = <0x20100>;
3218
3219 enable-method = "psci";
3220
1582e1d1
SG		 3221 operating-points-v2 = <&cl2_opp_tbl>;
3222 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
3223
a12cf5c3
TR		 3224 i-cache-size = <65536>;
3225 i-cache-line-size = <64>;
3226 i-cache-sets = <256>;
3227 d-cache-size = <65536>;
3228 d-cache-line-size = <64>;
3229 d-cache-sets = <256>;
3230 next-level-cache = <&l2c2_1>;
3231 };
3232
3233 cpu2_2: cpu@20200 {
3234 compatible = "arm,cortex-a78";
3235 device_type = "cpu";
3236 reg = <0x20200>;
3237
3238 enable-method = "psci";
3239
1582e1d1
SG		 3240 operating-points-v2 = <&cl2_opp_tbl>;
3241 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
3242
a12cf5c3
TR		 3243 i-cache-size = <65536>;
3244 i-cache-line-size = <64>;
3245 i-cache-sets = <256>;
3246 d-cache-size = <65536>;
3247 d-cache-line-size = <64>;
3248 d-cache-sets = <256>;
3249 next-level-cache = <&l2c2_2>;
3250 };
3251
3252 cpu2_3: cpu@20300 {
3253 compatible = "arm,cortex-a78";
3254 device_type = "cpu";
3255 reg = <0x20300>;
3256
3257 enable-method = "psci";
3258
1582e1d1
SG		 3259 operating-points-v2 = <&cl2_opp_tbl>;
3260 interconnects = <&mc TEGRA_ICC_MC_CPU_CLUSTER2 &emc>;
3261
a12cf5c3
TR		 3262 i-cache-size = <65536>;
3263 i-cache-line-size = <64>;
3264 i-cache-sets = <256>;
3265 d-cache-size = <65536>;
3266 d-cache-line-size = <64>;
3267 d-cache-sets = <256>;
3268 next-level-cache = <&l2c2_3>;
3269 };
3270
3271 cpu-map {
3272 cluster0 {
3273 core0 {
3274 cpu = <&cpu0_0>;
3275 };
3276
3277 core1 {
3278 cpu = <&cpu0_1>;
3279 };
3280
3281 core2 {
3282 cpu = <&cpu0_2>;
3283 };
3284
3285 core3 {
3286 cpu = <&cpu0_3>;
3287 };
3288 };
3289
3290 cluster1 {
3291 core0 {
3292 cpu = <&cpu1_0>;
3293 };
3294
3295 core1 {
3296 cpu = <&cpu1_1>;
3297 };
3298
3299 core2 {
3300 cpu = <&cpu1_2>;
3301 };
3302
3303 core3 {
3304 cpu = <&cpu1_3>;
3305 };
3306 };
3307
3308 cluster2 {
3309 core0 {
3310 cpu = <&cpu2_0>;
3311 };
3312
3313 core1 {
3314 cpu = <&cpu2_1>;
3315 };
3316
3317 core2 {
3318 cpu = <&cpu2_2>;
3319 };
3320
3321 core3 {
3322 cpu = <&cpu2_3>;
3323 };
3324 };
3325 };
3326
3327 l2c0_0: l2-cache00 {
27f1568b 3328 compatible = "cache";
a12cf5c3
TR		 3329 cache-size = <262144>;
3330 cache-line-size = <64>;
3331 cache-sets = <512>;
3332 cache-unified;
27f1568b 3333 cache-level = <2>;
a12cf5c3
TR		 3334 next-level-cache = <&l3c0>;
3335 };
3336
3337 l2c0_1: l2-cache01 {
27f1568b 3338 compatible = "cache";
a12cf5c3
TR		 3339 cache-size = <262144>;
3340 cache-line-size = <64>;
3341 cache-sets = <512>;
3342 cache-unified;
27f1568b 3343 cache-level = <2>;
a12cf5c3
TR		 3344 next-level-cache = <&l3c0>;
3345 };
3346
3347 l2c0_2: l2-cache02 {
27f1568b 3348 compatible = "cache";
a12cf5c3
TR		 3349 cache-size = <262144>;
3350 cache-line-size = <64>;
3351 cache-sets = <512>;
3352 cache-unified;
27f1568b 3353 cache-level = <2>;
a12cf5c3
TR		 3354 next-level-cache = <&l3c0>;
3355 };
3356
3357 l2c0_3: l2-cache03 {
27f1568b 3358 compatible = "cache";
a12cf5c3
TR		 3359 cache-size = <262144>;
3360 cache-line-size = <64>;
3361 cache-sets = <512>;
3362 cache-unified;
27f1568b 3363 cache-level = <2>;
a12cf5c3
TR		 3364 next-level-cache = <&l3c0>;
3365 };
3366
3367 l2c1_0: l2-cache10 {
27f1568b 3368 compatible = "cache";
a12cf5c3
TR		 3369 cache-size = <262144>;
3370 cache-line-size = <64>;
3371 cache-sets = <512>;
3372 cache-unified;
27f1568b 3373 cache-level = <2>;
a12cf5c3
TR		 3374 next-level-cache = <&l3c1>;
3375 };
3376
3377 l2c1_1: l2-cache11 {
27f1568b 3378 compatible = "cache";
a12cf5c3
TR		 3379 cache-size = <262144>;
3380 cache-line-size = <64>;
3381 cache-sets = <512>;
3382 cache-unified;
27f1568b 3383 cache-level = <2>;
a12cf5c3
TR		 3384 next-level-cache = <&l3c1>;
3385 };
3386
3387 l2c1_2: l2-cache12 {
27f1568b 3388 compatible = "cache";
a12cf5c3
TR		 3389 cache-size = <262144>;
3390 cache-line-size = <64>;
3391 cache-sets = <512>;
3392 cache-unified;
27f1568b 3393 cache-level = <2>;
a12cf5c3
TR		 3394 next-level-cache = <&l3c1>;
3395 };
3396
3397 l2c1_3: l2-cache13 {
27f1568b 3398 compatible = "cache";
a12cf5c3
TR		 3399 cache-size = <262144>;
3400 cache-line-size = <64>;
3401 cache-sets = <512>;
3402 cache-unified;
27f1568b 3403 cache-level = <2>;
a12cf5c3
TR		 3404 next-level-cache = <&l3c1>;
3405 };
3406
3407 l2c2_0: l2-cache20 {
27f1568b 3408 compatible = "cache";
a12cf5c3
TR		 3409 cache-size = <262144>;
3410 cache-line-size = <64>;
3411 cache-sets = <512>;
3412 cache-unified;
27f1568b 3413 cache-level = <2>;
a12cf5c3
TR		 3414 next-level-cache = <&l3c2>;
3415 };
3416
3417 l2c2_1: l2-cache21 {
27f1568b 3418 compatible = "cache";
a12cf5c3
TR		 3419 cache-size = <262144>;
3420 cache-line-size = <64>;
3421 cache-sets = <512>;
3422 cache-unified;
27f1568b 3423 cache-level = <2>;
a12cf5c3
TR		 3424 next-level-cache = <&l3c2>;
3425 };
3426
3427 l2c2_2: l2-cache22 {
27f1568b 3428 compatible = "cache";
a12cf5c3
TR		 3429 cache-size = <262144>;
3430 cache-line-size = <64>;
3431 cache-sets = <512>;
3432 cache-unified;
27f1568b 3433 cache-level = <2>;
a12cf5c3
TR		 3434 next-level-cache = <&l3c2>;
3435 };
3436
3437 l2c2_3: l2-cache23 {
27f1568b 3438 compatible = "cache";
a12cf5c3
TR		 3439 cache-size = <262144>;
3440 cache-line-size = <64>;
3441 cache-sets = <512>;
3442 cache-unified;
27f1568b 3443 cache-level = <2>;
a12cf5c3
TR		 3444 next-level-cache = <&l3c2>;
3445 };
3446
3447 l3c0: l3-cache0 {
27f1568b
PG		 3448 compatible = "cache";
3449 cache-unified;
a12cf5c3
TR		 3450 cache-size = <2097152>;
3451 cache-line-size = <64>;
3452 cache-sets = <2048>;
27f1568b 3453 cache-level = <3>;
a12cf5c3
TR		 3454 };
3455
3456 l3c1: l3-cache1 {
27f1568b
PG		 3457 compatible = "cache";
3458 cache-unified;
a12cf5c3
TR		 3459 cache-size = <2097152>;
3460 cache-line-size = <64>;
3461 cache-sets = <2048>;
27f1568b 3462 cache-level = <3>;
a12cf5c3
TR		 3463 };
3464
3465 l3c2: l3-cache2 {
27f1568b
PG		 3466 compatible = "cache";
3467 cache-unified;
a12cf5c3
TR		 3468 cache-size = <2097152>;
3469 cache-line-size = <64>;
3470 cache-sets = <2048>;
27f1568b 3471 cache-level = <3>;
a12cf5c3
TR		 3472 };
3473 };
3474
8e0ae0fb
JH		 3475 dsu-pmu0 {
3476 compatible = "arm,dsu-pmu";
3477 interrupts = <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>;
3478 cpus = <&cpu0_0>, <&cpu0_1>, <&cpu0_2>, <&cpu0_3>;
3479 };
3480
3481 dsu-pmu1 {
3482 compatible = "arm,dsu-pmu";
3483 interrupts = <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
3484 cpus = <&cpu1_0>, <&cpu1_1>, <&cpu1_2>, <&cpu1_3>;
3485 };
3486
3487 dsu-pmu2 {
3488 compatible = "arm,dsu-pmu";
3489 interrupts = <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>;
3490 cpus = <&cpu2_0>, <&cpu2_1>, <&cpu2_2>, <&cpu2_3>;
3491 };
3492
a12cf5c3
TR		 3493 pmu {
3494 compatible = "arm,cortex-a78-pmu";
3495 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
3496 status = "okay";
63944891
TR		 3497 };
3498
3499 psci {
3500 compatible = "arm,psci-1.0";
3501 status = "okay";
3502 method = "smc";
3503 };
3504
06ad2ec4
MP		 3505 tcu: serial {
3506 compatible = "nvidia,tegra234-tcu", "nvidia,tegra194-tcu";
3507 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3508 <&hsp_aon TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(1)>;
3509 mbox-names = "rx", "tx";
3510 status = "disabled";
3511 };
3512
09614acd
SP		 3513 sound {
3514 status = "disabled";
3515
3516 clocks = <&bpmp TEGRA234_CLK_PLLA>,
3517 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3518 clock-names = "pll_a", "plla_out0";
3519 assigned-clocks = <&bpmp TEGRA234_CLK_PLLA>,
3520 <&bpmp TEGRA234_CLK_PLLA_OUT0>,
3521 <&bpmp TEGRA234_CLK_AUD_MCLK>;
3522 assigned-clock-parents = <0>,
3523 <&bpmp TEGRA234_CLK_PLLA>,
3524 <&bpmp TEGRA234_CLK_PLLA_OUT0>;
3525 };
3526
09d99078
TR		 3527 thermal-zones {
3528 cpu-thermal {
3529 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
3530 status = "disabled";
3531 };
3532
3533 gpu-thermal {
3534 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
3535 status = "disabled";
3536 };
3537
3538 cv0-thermal {
3539 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
3540 status = "disabled";
3541 };
3542
3543 cv1-thermal {
3544 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
3545 status = "disabled";
3546 };
3547
3548 cv2-thermal {
3549 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
3550 status = "disabled";
3551 };
3552
3553 soc0-thermal {
3554 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
3555 status = "disabled";
3556 };
3557
3558 soc1-thermal {
3559 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
3560 status = "disabled";
3561 };
3562
3563 soc2-thermal {
3564 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
3565 status = "disabled";
3566 };
3567
3568 tj-thermal {
3569 thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
3570 status = "disabled";
3571 };
3572 };
3573
63944891
TR		 3574 timer {
3575 compatible = "arm,armv8-timer";
3576 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3577 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3578 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3579 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3580 interrupt-parent = <&gic>;
3581 always-on;
3582 };
1582e1d1
SG		 3583
3584 cl0_opp_tbl: opp-table-cluster0 {
3585 compatible = "operating-points-v2";
3586 opp-shared;
3587
3588 cl0_ch1_opp1: opp-115200000 {
3589 opp-hz = /bits/ 64 <115200000>;
3590 opp-peak-kBps = <816000>;
3591 };
3592
3593 cl0_ch1_opp2: opp-268800000 {
3594 opp-hz = /bits/ 64 <268800000>;
3595 opp-peak-kBps = <816000>;
3596 };
3597
3598 cl0_ch1_opp3: opp-422400000 {
3599 opp-hz = /bits/ 64 <422400000>;
3600 opp-peak-kBps = <816000>;
3601 };
3602
3603 cl0_ch1_opp4: opp-576000000 {
3604 opp-hz = /bits/ 64 <576000000>;
3605 opp-peak-kBps = <816000>;
3606 };
3607
3608 cl0_ch1_opp5: opp-729600000 {
3609 opp-hz = /bits/ 64 <729600000>;
3610 opp-peak-kBps = <816000>;
3611 };
3612
3613 cl0_ch1_opp6: opp-883200000 {
3614 opp-hz = /bits/ 64 <883200000>;
3615 opp-peak-kBps = <816000>;
3616 };
3617
3618 cl0_ch1_opp7: opp-1036800000 {
3619 opp-hz = /bits/ 64 <1036800000>;
3620 opp-peak-kBps = <816000>;
3621 };
3622
3623 cl0_ch1_opp8: opp-1190400000 {
3624 opp-hz = /bits/ 64 <1190400000>;
3625 opp-peak-kBps = <816000>;
3626 };
3627
3628 cl0_ch1_opp9: opp-1344000000 {
3629 opp-hz = /bits/ 64 <1344000000>;
3630 opp-peak-kBps = <1632000>;
3631 };
3632
3633 cl0_ch1_opp10: opp-1497600000 {
3634 opp-hz = /bits/ 64 <1497600000>;
3635 opp-peak-kBps = <1632000>;
3636 };
3637
3638 cl0_ch1_opp11: opp-1651200000 {
3639 opp-hz = /bits/ 64 <1651200000>;
3640 opp-peak-kBps = <2660000>;
3641 };
3642
3643 cl0_ch1_opp12: opp-1804800000 {
3644 opp-hz = /bits/ 64 <1804800000>;
3645 opp-peak-kBps = <2660000>;
3646 };
3647
3648 cl0_ch1_opp13: opp-1958400000 {
3649 opp-hz = /bits/ 64 <1958400000>;
3650 opp-peak-kBps = <3200000>;
3651 };
3652
3653 cl0_ch1_opp14: opp-2112000000 {
3654 opp-hz = /bits/ 64 <2112000000>;
3655 opp-peak-kBps = <6400000>;
3656 };
3657
3658 cl0_ch1_opp15: opp-2201600000 {
3659 opp-hz = /bits/ 64 <2201600000>;
3660 opp-peak-kBps = <6400000>;
3661 };
3662 };
3663
3664 cl1_opp_tbl: opp-table-cluster1 {
3665 compatible = "operating-points-v2";
3666 opp-shared;
3667
3668 cl1_ch1_opp1: opp-115200000 {
3669 opp-hz = /bits/ 64 <115200000>;
3670 opp-peak-kBps = <816000>;
3671 };
3672
3673 cl1_ch1_opp2: opp-268800000 {
3674 opp-hz = /bits/ 64 <268800000>;
3675 opp-peak-kBps = <816000>;
3676 };
3677
3678 cl1_ch1_opp3: opp-422400000 {
3679 opp-hz = /bits/ 64 <422400000>;
3680 opp-peak-kBps = <816000>;
3681 };
3682
3683 cl1_ch1_opp4: opp-576000000 {
3684 opp-hz = /bits/ 64 <576000000>;
3685 opp-peak-kBps = <816000>;
3686 };
3687
3688 cl1_ch1_opp5: opp-729600000 {
3689 opp-hz = /bits/ 64 <729600000>;
3690 opp-peak-kBps = <816000>;
3691 };
3692
3693 cl1_ch1_opp6: opp-883200000 {
3694 opp-hz = /bits/ 64 <883200000>;
3695 opp-peak-kBps = <816000>;
3696 };
3697
3698 cl1_ch1_opp7: opp-1036800000 {
3699 opp-hz = /bits/ 64 <1036800000>;
3700 opp-peak-kBps = <816000>;
3701 };
3702
3703 cl1_ch1_opp8: opp-1190400000 {
3704 opp-hz = /bits/ 64 <1190400000>;
3705 opp-peak-kBps = <816000>;
3706 };
3707
3708 cl1_ch1_opp9: opp-1344000000 {
3709 opp-hz = /bits/ 64 <1344000000>;
3710 opp-peak-kBps = <1632000>;
3711 };
3712
3713 cl1_ch1_opp10: opp-1497600000 {
3714 opp-hz = /bits/ 64 <1497600000>;
3715 opp-peak-kBps = <1632000>;
3716 };
3717
3718 cl1_ch1_opp11: opp-1651200000 {
3719 opp-hz = /bits/ 64 <1651200000>;
3720 opp-peak-kBps = <2660000>;
3721 };
3722
3723 cl1_ch1_opp12: opp-1804800000 {
3724 opp-hz = /bits/ 64 <1804800000>;
3725 opp-peak-kBps = <2660000>;
3726 };
3727
3728 cl1_ch1_opp13: opp-1958400000 {
3729 opp-hz = /bits/ 64 <1958400000>;
3730 opp-peak-kBps = <3200000>;
3731 };
3732
3733 cl1_ch1_opp14: opp-2112000000 {
3734 opp-hz = /bits/ 64 <2112000000>;
3735 opp-peak-kBps = <6400000>;
3736 };
3737
3738 cl1_ch1_opp15: opp-2201600000 {
3739 opp-hz = /bits/ 64 <2201600000>;
3740 opp-peak-kBps = <6400000>;
3741 };
3742 };
3743
3744 cl2_opp_tbl: opp-table-cluster2 {
3745 compatible = "operating-points-v2";
3746 opp-shared;
3747
3748 cl2_ch1_opp1: opp-115200000 {
3749 opp-hz = /bits/ 64 <115200000>;
3750 opp-peak-kBps = <816000>;
3751 };
3752
3753 cl2_ch1_opp2: opp-268800000 {
3754 opp-hz = /bits/ 64 <268800000>;
3755 opp-peak-kBps = <816000>;
3756 };
3757
3758 cl2_ch1_opp3: opp-422400000 {
3759 opp-hz = /bits/ 64 <422400000>;
3760 opp-peak-kBps = <816000>;
3761 };
3762
3763 cl2_ch1_opp4: opp-576000000 {
3764 opp-hz = /bits/ 64 <576000000>;
3765 opp-peak-kBps = <816000>;
3766 };
3767
3768 cl2_ch1_opp5: opp-729600000 {
3769 opp-hz = /bits/ 64 <729600000>;
3770 opp-peak-kBps = <816000>;
3771 };
3772
3773 cl2_ch1_opp6: opp-883200000 {
3774 opp-hz = /bits/ 64 <883200000>;
3775 opp-peak-kBps = <816000>;
3776 };
3777
3778 cl2_ch1_opp7: opp-1036800000 {
3779 opp-hz = /bits/ 64 <1036800000>;
3780 opp-peak-kBps = <816000>;
3781 };
3782
3783 cl2_ch1_opp8: opp-1190400000 {
3784 opp-hz = /bits/ 64 <1190400000>;
3785 opp-peak-kBps = <816000>;
3786 };
3787
3788 cl2_ch1_opp9: opp-1344000000 {
3789 opp-hz = /bits/ 64 <1344000000>;
3790 opp-peak-kBps = <1632000>;
3791 };
3792
3793 cl2_ch1_opp10: opp-1497600000 {
3794 opp-hz = /bits/ 64 <1497600000>;
3795 opp-peak-kBps = <1632000>;
3796 };
3797
3798 cl2_ch1_opp11: opp-1651200000 {
3799 opp-hz = /bits/ 64 <1651200000>;
3800 opp-peak-kBps = <2660000>;
3801 };
3802
3803 cl2_ch1_opp12: opp-1804800000 {
3804 opp-hz = /bits/ 64 <1804800000>;
3805 opp-peak-kBps = <2660000>;
3806 };
3807
3808 cl2_ch1_opp13: opp-1958400000 {
3809 opp-hz = /bits/ 64 <1958400000>;
3810 opp-peak-kBps = <3200000>;
3811 };
3812
3813 cl2_ch1_opp14: opp-2112000000 {
3814 opp-hz = /bits/ 64 <2112000000>;
3815 opp-peak-kBps = <6400000>;
3816 };
3817
3818 cl2_ch1_opp15: opp-2201600000 {
3819 opp-hz = /bits/ 64 <2201600000>;
3820 opp-peak-kBps = <6400000>;
3821 };
3822 };
63944891 3823};
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