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97fb5e8d | 1 | // SPDX-License-Identifier: GPL-2.0-only |
4558e9b3 | 2 | /* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. |
4558e9b3 SB |
3 | */ |
4 | ||
5 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
6 | #include <dt-bindings/clock/qcom,gcc-msm8996.h> | |
7 | #include <dt-bindings/clock/qcom,mmcc-msm8996.h> | |
00f8497f | 8 | #include <dt-bindings/clock/qcom,rpmcc.h> |
f3eb39a5 | 9 | #include <dt-bindings/soc/qcom,apr.h> |
4558e9b3 SB |
10 | |
11 | / { | |
4558e9b3 SB |
12 | interrupt-parent = <&intc>; |
13 | ||
14 | #address-cells = <2>; | |
15 | #size-cells = <2>; | |
16 | ||
17 | chosen { }; | |
18 | ||
50aa72cc BA |
19 | clocks { |
20 | xo_board: xo_board { | |
21 | compatible = "fixed-clock"; | |
22 | #clock-cells = <0>; | |
23 | clock-frequency = <19200000>; | |
24 | clock-output-names = "xo_board"; | |
68ae3d0c | 25 | }; |
69cc3114 | 26 | |
50aa72cc BA |
27 | sleep_clk: sleep_clk { |
28 | compatible = "fixed-clock"; | |
29 | #clock-cells = <0>; | |
30 | clock-frequency = <32764>; | |
31 | clock-output-names = "sleep_clk"; | |
69cc3114 | 32 | }; |
ee17692c SJ |
33 | }; |
34 | ||
4558e9b3 SB |
35 | cpus { |
36 | #address-cells = <2>; | |
37 | #size-cells = <0>; | |
38 | ||
39 | CPU0: cpu@0 { | |
40 | device_type = "cpu"; | |
41 | compatible = "qcom,kryo"; | |
42 | reg = <0x0 0x0>; | |
43 | enable-method = "psci"; | |
f6aee7af | 44 | cpu-idle-states = <&CPU_SLEEP_0>; |
2aefca80 | 45 | capacity-dmips-mhz = <1024>; |
4558e9b3 SB |
46 | next-level-cache = <&L2_0>; |
47 | L2_0: l2-cache { | |
48 | compatible = "cache"; | |
49 | cache-level = <2>; | |
50 | }; | |
51 | }; | |
52 | ||
53 | CPU1: cpu@1 { | |
54 | device_type = "cpu"; | |
55 | compatible = "qcom,kryo"; | |
56 | reg = <0x0 0x1>; | |
57 | enable-method = "psci"; | |
f6aee7af | 58 | cpu-idle-states = <&CPU_SLEEP_0>; |
2aefca80 | 59 | capacity-dmips-mhz = <1024>; |
4558e9b3 SB |
60 | next-level-cache = <&L2_0>; |
61 | }; | |
62 | ||
63 | CPU2: cpu@100 { | |
64 | device_type = "cpu"; | |
65 | compatible = "qcom,kryo"; | |
66 | reg = <0x0 0x100>; | |
67 | enable-method = "psci"; | |
f6aee7af | 68 | cpu-idle-states = <&CPU_SLEEP_0>; |
2aefca80 | 69 | capacity-dmips-mhz = <1024>; |
4558e9b3 SB |
70 | next-level-cache = <&L2_1>; |
71 | L2_1: l2-cache { | |
72 | compatible = "cache"; | |
73 | cache-level = <2>; | |
74 | }; | |
75 | }; | |
76 | ||
77 | CPU3: cpu@101 { | |
78 | device_type = "cpu"; | |
79 | compatible = "qcom,kryo"; | |
80 | reg = <0x0 0x101>; | |
81 | enable-method = "psci"; | |
f6aee7af | 82 | cpu-idle-states = <&CPU_SLEEP_0>; |
2aefca80 | 83 | capacity-dmips-mhz = <1024>; |
4558e9b3 SB |
84 | next-level-cache = <&L2_1>; |
85 | }; | |
86 | ||
87 | cpu-map { | |
88 | cluster0 { | |
89 | core0 { | |
90 | cpu = <&CPU0>; | |
91 | }; | |
92 | ||
93 | core1 { | |
94 | cpu = <&CPU1>; | |
95 | }; | |
96 | }; | |
97 | ||
98 | cluster1 { | |
99 | core0 { | |
100 | cpu = <&CPU2>; | |
101 | }; | |
102 | ||
103 | core1 { | |
104 | cpu = <&CPU3>; | |
105 | }; | |
106 | }; | |
107 | }; | |
f6aee7af AK |
108 | |
109 | idle-states { | |
110 | entry-method = "psci"; | |
111 | ||
112 | CPU_SLEEP_0: cpu-sleep-0 { | |
113 | compatible = "arm,idle-state"; | |
114 | idle-state-name = "standalone-power-collapse"; | |
115 | arm,psci-suspend-param = <0x00000004>; | |
73db2714 | 116 | entry-latency-us = <130>; |
f6aee7af AK |
117 | exit-latency-us = <80>; |
118 | min-residency-us = <300>; | |
119 | }; | |
120 | }; | |
4558e9b3 SB |
121 | }; |
122 | ||
50aa72cc BA |
123 | firmware { |
124 | scm { | |
125 | compatible = "qcom,scm-msm8996"; | |
126 | qcom,dload-mode = <&tcsr 0x13000>; | |
127 | }; | |
128 | }; | |
7422ee8e | 129 | |
50aa72cc BA |
130 | tcsr_mutex: hwlock { |
131 | compatible = "qcom,tcsr-mutex"; | |
132 | syscon = <&tcsr_mutex_regs 0 0x1000>; | |
133 | #hwlock-cells = <1>; | |
134 | }; | |
7422ee8e | 135 | |
50aa72cc BA |
136 | memory { |
137 | device_type = "memory"; | |
138 | /* We expect the bootloader to fill in the reg */ | |
139 | reg = <0 0 0 0>; | |
140 | }; | |
7422ee8e | 141 | |
50aa72cc BA |
142 | psci { |
143 | compatible = "arm,psci-1.0"; | |
144 | method = "smc"; | |
145 | }; | |
7422ee8e | 146 | |
50aa72cc BA |
147 | reserved-memory { |
148 | #address-cells = <2>; | |
149 | #size-cells = <2>; | |
150 | ranges; | |
7422ee8e | 151 | |
50aa72cc BA |
152 | mba_region: mba@91500000 { |
153 | reg = <0x0 0x91500000 0x0 0x200000>; | |
154 | no-map; | |
155 | }; | |
7422ee8e | 156 | |
50aa72cc BA |
157 | slpi_region: slpi@90b00000 { |
158 | reg = <0x0 0x90b00000 0x0 0xa00000>; | |
159 | no-map; | |
160 | }; | |
7422ee8e | 161 | |
50aa72cc BA |
162 | venus_region: venus@90400000 { |
163 | reg = <0x0 0x90400000 0x0 0x700000>; | |
164 | no-map; | |
7422ee8e RN |
165 | }; |
166 | ||
50aa72cc BA |
167 | adsp_region: adsp@8ea00000 { |
168 | reg = <0x0 0x8ea00000 0x0 0x1a00000>; | |
169 | no-map; | |
170 | }; | |
7422ee8e | 171 | |
50aa72cc BA |
172 | mpss_region: mpss@88800000 { |
173 | reg = <0x0 0x88800000 0x0 0x6200000>; | |
174 | no-map; | |
175 | }; | |
7422ee8e | 176 | |
50aa72cc BA |
177 | smem_mem: smem-mem@86000000 { |
178 | reg = <0x0 0x86000000 0x0 0x200000>; | |
179 | no-map; | |
180 | }; | |
7422ee8e | 181 | |
50aa72cc BA |
182 | memory@85800000 { |
183 | reg = <0x0 0x85800000 0x0 0x800000>; | |
184 | no-map; | |
7422ee8e RN |
185 | }; |
186 | ||
50aa72cc BA |
187 | memory@86200000 { |
188 | reg = <0x0 0x86200000 0x0 0x2600000>; | |
189 | no-map; | |
190 | }; | |
7422ee8e | 191 | |
50aa72cc BA |
192 | rmtfs@86700000 { |
193 | compatible = "qcom,rmtfs-mem"; | |
7422ee8e | 194 | |
50aa72cc BA |
195 | size = <0x0 0x200000>; |
196 | alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>; | |
197 | no-map; | |
7422ee8e | 198 | |
50aa72cc BA |
199 | qcom,client-id = <1>; |
200 | qcom,vmid = <15>; | |
7422ee8e | 201 | }; |
0f5f91f0 | 202 | |
50aa72cc BA |
203 | zap_shader_region: gpu@8f200000 { |
204 | compatible = "shared-dma-pool"; | |
205 | reg = <0x0 0x90b00000 0x0 0xa00000>; | |
206 | no-map; | |
0f5f91f0 | 207 | }; |
50aa72cc | 208 | }; |
0f5f91f0 | 209 | |
50aa72cc BA |
210 | rpm-glink { |
211 | compatible = "qcom,glink-rpm"; | |
0f5f91f0 | 212 | |
50aa72cc | 213 | interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; |
0f5f91f0 | 214 | |
50aa72cc | 215 | qcom,rpm-msg-ram = <&rpm_msg_ram>; |
0f5f91f0 | 216 | |
50aa72cc | 217 | mboxes = <&apcs_glb 0>; |
0f5f91f0 | 218 | |
50aa72cc BA |
219 | rpm_requests: rpm-requests { |
220 | compatible = "qcom,rpm-msm8996"; | |
221 | qcom,glink-channels = "rpm_requests"; | |
0f5f91f0 | 222 | |
50aa72cc BA |
223 | rpmcc: qcom,rpmcc { |
224 | compatible = "qcom,rpmcc-msm8996"; | |
225 | #clock-cells = <1>; | |
00f8497f RN |
226 | }; |
227 | ||
fae1967f RN |
228 | rpmpd: power-controller { |
229 | compatible = "qcom,msm8996-rpmpd"; | |
230 | #power-domain-cells = <1>; | |
231 | operating-points-v2 = <&rpmpd_opp_table>; | |
232 | ||
233 | rpmpd_opp_table: opp-table { | |
234 | compatible = "operating-points-v2"; | |
235 | ||
236 | rpmpd_opp1: opp1 { | |
237 | opp-level = <1>; | |
238 | }; | |
239 | ||
240 | rpmpd_opp2: opp2 { | |
241 | opp-level = <2>; | |
242 | }; | |
243 | ||
244 | rpmpd_opp3: opp3 { | |
245 | opp-level = <3>; | |
246 | }; | |
247 | ||
248 | rpmpd_opp4: opp4 { | |
249 | opp-level = <4>; | |
250 | }; | |
251 | ||
252 | rpmpd_opp5: opp5 { | |
253 | opp-level = <5>; | |
254 | }; | |
255 | ||
256 | rpmpd_opp6: opp6 { | |
257 | opp-level = <6>; | |
258 | }; | |
259 | }; | |
260 | }; | |
f742f878 BA |
261 | }; |
262 | }; | |
263 | ||
50aa72cc BA |
264 | smem { |
265 | compatible = "qcom,smem"; | |
266 | memory-region = <&smem_mem>; | |
267 | hwlocks = <&tcsr_mutex 3>; | |
268 | }; | |
4558e9b3 | 269 | |
50aa72cc BA |
270 | smp2p-adsp { |
271 | compatible = "qcom,smp2p"; | |
272 | qcom,smem = <443>, <429>; | |
f742f878 | 273 | |
50aa72cc | 274 | interrupts = <0 158 IRQ_TYPE_EDGE_RISING>; |
6e382cc7 | 275 | |
50aa72cc | 276 | mboxes = <&apcs_glb 10>; |
da3d658e | 277 | |
50aa72cc BA |
278 | qcom,local-pid = <0>; |
279 | qcom,remote-pid = <2>; | |
f35c11b0 | 280 | |
50aa72cc BA |
281 | smp2p_adsp_out: master-kernel { |
282 | qcom,entry-name = "master-kernel"; | |
283 | #qcom,smem-state-cells = <1>; | |
f35c11b0 AK |
284 | }; |
285 | ||
50aa72cc BA |
286 | smp2p_adsp_in: slave-kernel { |
287 | qcom,entry-name = "slave-kernel"; | |
1f34d644 | 288 | |
4558e9b3 | 289 | interrupt-controller; |
50aa72cc | 290 | #interrupt-cells = <2>; |
4558e9b3 | 291 | }; |
50aa72cc | 292 | }; |
4558e9b3 | 293 | |
50aa72cc BA |
294 | smp2p-modem { |
295 | compatible = "qcom,smp2p"; | |
296 | qcom,smem = <435>, <428>; | |
f742f878 | 297 | |
50aa72cc | 298 | interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; |
f742f878 | 299 | |
50aa72cc | 300 | mboxes = <&apcs_glb 14>; |
4558e9b3 | 301 | |
50aa72cc BA |
302 | qcom,local-pid = <0>; |
303 | qcom,remote-pid = <1>; | |
d98de8ef | 304 | |
50aa72cc BA |
305 | modem_smp2p_out: master-kernel { |
306 | qcom,entry-name = "master-kernel"; | |
307 | #qcom,smem-state-cells = <1>; | |
d98de8ef VG |
308 | }; |
309 | ||
50aa72cc BA |
310 | modem_smp2p_in: slave-kernel { |
311 | qcom,entry-name = "slave-kernel"; | |
d98de8ef | 312 | |
50aa72cc BA |
313 | interrupt-controller; |
314 | #interrupt-cells = <2>; | |
d98de8ef | 315 | }; |
50aa72cc | 316 | }; |
d98de8ef | 317 | |
50aa72cc BA |
318 | smp2p-slpi { |
319 | compatible = "qcom,smp2p"; | |
320 | qcom,smem = <481>, <430>; | |
d98de8ef | 321 | |
50aa72cc | 322 | interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; |
d98de8ef | 323 | |
50aa72cc | 324 | mboxes = <&apcs_glb 26>; |
d98de8ef | 325 | |
50aa72cc BA |
326 | qcom,local-pid = <0>; |
327 | qcom,remote-pid = <3>; | |
d98de8ef | 328 | |
50aa72cc BA |
329 | smp2p_slpi_in: slave-kernel { |
330 | qcom,entry-name = "slave-kernel"; | |
331 | interrupt-controller; | |
332 | #interrupt-cells = <2>; | |
d98de8ef VG |
333 | }; |
334 | ||
50aa72cc BA |
335 | smp2p_slpi_out: master-kernel { |
336 | qcom,entry-name = "master-kernel"; | |
337 | #qcom,smem-state-cells = <1>; | |
338 | }; | |
339 | }; | |
d98de8ef | 340 | |
50aa72cc BA |
341 | soc: soc { |
342 | #address-cells = <1>; | |
343 | #size-cells = <1>; | |
344 | ranges = <0 0 0 0xffffffff>; | |
345 | compatible = "simple-bus"; | |
d98de8ef | 346 | |
50aa72cc BA |
347 | pcie_phy: phy@34000 { |
348 | compatible = "qcom,msm8996-qmp-pcie-phy"; | |
349 | reg = <0x00034000 0x488>; | |
350 | #clock-cells = <1>; | |
351 | #address-cells = <1>; | |
352 | #size-cells = <1>; | |
353 | ranges; | |
d98de8ef | 354 | |
50aa72cc BA |
355 | clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, |
356 | <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>, | |
357 | <&gcc GCC_PCIE_CLKREF_CLK>; | |
358 | clock-names = "aux", "cfg_ahb", "ref"; | |
d98de8ef | 359 | |
50aa72cc BA |
360 | resets = <&gcc GCC_PCIE_PHY_BCR>, |
361 | <&gcc GCC_PCIE_PHY_COM_BCR>, | |
362 | <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>; | |
363 | reset-names = "phy", "common", "cfg"; | |
364 | status = "disabled"; | |
d98de8ef | 365 | |
50aa72cc BA |
366 | pciephy_0: lane@35000 { |
367 | reg = <0x00035000 0x130>, | |
368 | <0x00035200 0x200>, | |
369 | <0x00035400 0x1dc>; | |
370 | #phy-cells = <0>; | |
d98de8ef | 371 | |
50aa72cc BA |
372 | clock-output-names = "pcie_0_pipe_clk_src"; |
373 | clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; | |
374 | clock-names = "pipe0"; | |
375 | resets = <&gcc GCC_PCIE_0_PHY_BCR>; | |
376 | reset-names = "lane0"; | |
377 | }; | |
d98de8ef | 378 | |
50aa72cc BA |
379 | pciephy_1: lane@36000 { |
380 | reg = <0x00036000 0x130>, | |
381 | <0x00036200 0x200>, | |
382 | <0x00036400 0x1dc>; | |
383 | #phy-cells = <0>; | |
d98de8ef | 384 | |
50aa72cc BA |
385 | clock-output-names = "pcie_1_pipe_clk_src"; |
386 | clocks = <&gcc GCC_PCIE_1_PIPE_CLK>; | |
387 | clock-names = "pipe1"; | |
388 | resets = <&gcc GCC_PCIE_1_PHY_BCR>; | |
389 | reset-names = "lane1"; | |
d98de8ef | 390 | }; |
d98de8ef | 391 | |
50aa72cc BA |
392 | pciephy_2: lane@37000 { |
393 | reg = <0x00037000 0x130>, | |
394 | <0x00037200 0x200>, | |
395 | <0x00037400 0x1dc>; | |
396 | #phy-cells = <0>; | |
d98de8ef | 397 | |
50aa72cc BA |
398 | clock-output-names = "pcie_2_pipe_clk_src"; |
399 | clocks = <&gcc GCC_PCIE_2_PIPE_CLK>; | |
400 | clock-names = "pipe2"; | |
401 | resets = <&gcc GCC_PCIE_2_PHY_BCR>; | |
402 | reset-names = "lane2"; | |
403 | }; | |
404 | }; | |
d98de8ef | 405 | |
50aa72cc BA |
406 | rpm_msg_ram: memory@68000 { |
407 | compatible = "qcom,rpm-msg-ram"; | |
408 | reg = <0x00068000 0x6000>; | |
409 | }; | |
d98de8ef | 410 | |
50aa72cc BA |
411 | qfprom@74000 { |
412 | compatible = "qcom,qfprom"; | |
413 | reg = <0x00074000 0x8ff>; | |
414 | #address-cells = <1>; | |
415 | #size-cells = <1>; | |
d98de8ef | 416 | |
50aa72cc BA |
417 | qusb2p_hstx_trim: hstx_trim@24e { |
418 | reg = <0x24e 0x2>; | |
419 | bits = <5 4>; | |
420 | }; | |
d98de8ef | 421 | |
50aa72cc BA |
422 | qusb2s_hstx_trim: hstx_trim@24f { |
423 | reg = <0x24f 0x1>; | |
424 | bits = <1 4>; | |
d98de8ef VG |
425 | }; |
426 | ||
50aa72cc BA |
427 | gpu_speed_bin: gpu_speed_bin@133 { |
428 | reg = <0x133 0x1>; | |
429 | bits = <5 3>; | |
d98de8ef VG |
430 | }; |
431 | }; | |
432 | ||
50aa72cc BA |
433 | rng: rng@83000 { |
434 | compatible = "qcom,prng-ee"; | |
435 | reg = <0x00083000 0x1000>; | |
436 | clocks = <&gcc GCC_PRNG_AHB_CLK>; | |
437 | clock-names = "core"; | |
438 | }; | |
d98de8ef | 439 | |
50aa72cc BA |
440 | gcc: clock-controller@300000 { |
441 | compatible = "qcom,gcc-msm8996"; | |
442 | #clock-cells = <1>; | |
443 | #reset-cells = <1>; | |
444 | #power-domain-cells = <1>; | |
445 | reg = <0x00300000 0x90000>; | |
950d3fb6 BA |
446 | |
447 | clocks = <&rpmcc RPM_SMD_LN_BB_CLK>; | |
448 | clock-names = "cxo2"; | |
50aa72cc | 449 | }; |
d98de8ef | 450 | |
50aa72cc | 451 | tsens0: thermal-sensor@4a9000 { |
946f8007 | 452 | compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; |
50aa72cc BA |
453 | reg = <0x004a9000 0x1000>, /* TM */ |
454 | <0x004a8000 0x1000>; /* SROT */ | |
455 | #qcom,sensors = <13>; | |
1246f782 AK |
456 | interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, |
457 | <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; | |
458 | interrupt-names = "uplow", "critical"; | |
50aa72cc BA |
459 | #thermal-sensor-cells = <1>; |
460 | }; | |
d98de8ef | 461 | |
50aa72cc | 462 | tsens1: thermal-sensor@4ad000 { |
946f8007 | 463 | compatible = "qcom,msm8996-tsens", "qcom,tsens-v2"; |
50aa72cc BA |
464 | reg = <0x004ad000 0x1000>, /* TM */ |
465 | <0x004ac000 0x1000>; /* SROT */ | |
466 | #qcom,sensors = <8>; | |
1246f782 AK |
467 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, |
468 | <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; | |
469 | interrupt-names = "uplow", "critical"; | |
50aa72cc BA |
470 | #thermal-sensor-cells = <1>; |
471 | }; | |
d98de8ef | 472 | |
50aa72cc BA |
473 | tcsr_mutex_regs: syscon@740000 { |
474 | compatible = "syscon"; | |
475 | reg = <0x00740000 0x20000>; | |
d98de8ef VG |
476 | }; |
477 | ||
50aa72cc BA |
478 | tcsr: syscon@7a0000 { |
479 | compatible = "qcom,tcsr-msm8996", "syscon"; | |
480 | reg = <0x007a0000 0x18000>; | |
481 | }; | |
d98de8ef | 482 | |
50aa72cc BA |
483 | mmcc: clock-controller@8c0000 { |
484 | compatible = "qcom,mmcc-msm8996"; | |
485 | #clock-cells = <1>; | |
486 | #reset-cells = <1>; | |
487 | #power-domain-cells = <1>; | |
488 | reg = <0x008c0000 0x40000>; | |
489 | assigned-clocks = <&mmcc MMPLL9_PLL>, | |
490 | <&mmcc MMPLL1_PLL>, | |
491 | <&mmcc MMPLL3_PLL>, | |
492 | <&mmcc MMPLL4_PLL>, | |
493 | <&mmcc MMPLL5_PLL>; | |
494 | assigned-clock-rates = <624000000>, | |
495 | <810000000>, | |
496 | <980000000>, | |
497 | <960000000>, | |
498 | <825000000>; | |
499 | }; | |
d98de8ef | 500 | |
50aa72cc BA |
501 | mdss: mdss@900000 { |
502 | compatible = "qcom,mdss"; | |
d98de8ef | 503 | |
50aa72cc BA |
504 | reg = <0x00900000 0x1000>, |
505 | <0x009b0000 0x1040>, | |
506 | <0x009b8000 0x1040>; | |
507 | reg-names = "mdss_phys", | |
508 | "vbif_phys", | |
509 | "vbif_nrt_phys"; | |
d98de8ef | 510 | |
50aa72cc BA |
511 | power-domains = <&mmcc MDSS_GDSC>; |
512 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; | |
d98de8ef | 513 | |
50aa72cc BA |
514 | interrupt-controller; |
515 | #interrupt-cells = <1>; | |
d98de8ef | 516 | |
50aa72cc BA |
517 | clocks = <&mmcc MDSS_AHB_CLK>; |
518 | clock-names = "iface"; | |
d98de8ef | 519 | |
50aa72cc BA |
520 | #address-cells = <1>; |
521 | #size-cells = <1>; | |
522 | ranges; | |
d98de8ef | 523 | |
50aa72cc BA |
524 | mdp: mdp@901000 { |
525 | compatible = "qcom,mdp5"; | |
526 | reg = <0x00901000 0x90000>; | |
527 | reg-names = "mdp_phys"; | |
d98de8ef | 528 | |
50aa72cc BA |
529 | interrupt-parent = <&mdss>; |
530 | interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; | |
d98de8ef | 531 | |
50aa72cc BA |
532 | clocks = <&mmcc MDSS_AHB_CLK>, |
533 | <&mmcc MDSS_AXI_CLK>, | |
534 | <&mmcc MDSS_MDP_CLK>, | |
535 | <&mmcc SMMU_MDP_AXI_CLK>, | |
536 | <&mmcc MDSS_VSYNC_CLK>; | |
537 | clock-names = "iface", | |
538 | "bus", | |
539 | "core", | |
540 | "iommu", | |
541 | "vsync"; | |
d98de8ef | 542 | |
50aa72cc | 543 | iommus = <&mdp_smmu 0>; |
d98de8ef | 544 | |
50aa72cc BA |
545 | ports { |
546 | #address-cells = <1>; | |
547 | #size-cells = <0>; | |
d98de8ef | 548 | |
50aa72cc BA |
549 | port@0 { |
550 | reg = <0>; | |
551 | mdp5_intf3_out: endpoint { | |
552 | remote-endpoint = <&hdmi_in>; | |
553 | }; | |
d98de8ef VG |
554 | }; |
555 | }; | |
556 | }; | |
d98de8ef | 557 | |
50aa72cc BA |
558 | hdmi: hdmi-tx@9a0000 { |
559 | compatible = "qcom,hdmi-tx-8996"; | |
560 | reg = <0x009a0000 0x50c>, | |
561 | <0x00070000 0x6158>, | |
562 | <0x009e0000 0xfff>; | |
563 | reg-names = "core_physical", | |
564 | "qfprom_physical", | |
565 | "hdcp_physical"; | |
d98de8ef | 566 | |
50aa72cc BA |
567 | interrupt-parent = <&mdss>; |
568 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; | |
d98de8ef | 569 | |
50aa72cc BA |
570 | clocks = <&mmcc MDSS_MDP_CLK>, |
571 | <&mmcc MDSS_AHB_CLK>, | |
572 | <&mmcc MDSS_HDMI_CLK>, | |
573 | <&mmcc MDSS_HDMI_AHB_CLK>, | |
574 | <&mmcc MDSS_EXTPCLK_CLK>; | |
575 | clock-names = | |
576 | "mdp_core", | |
577 | "iface", | |
578 | "core", | |
579 | "alt_iface", | |
580 | "extp"; | |
d98de8ef | 581 | |
50aa72cc BA |
582 | phys = <&hdmi_phy>; |
583 | phy-names = "hdmi_phy"; | |
584 | #sound-dai-cells = <1>; | |
d98de8ef | 585 | |
50aa72cc BA |
586 | ports { |
587 | #address-cells = <1>; | |
588 | #size-cells = <0>; | |
d98de8ef | 589 | |
50aa72cc BA |
590 | port@0 { |
591 | reg = <0>; | |
592 | hdmi_in: endpoint { | |
593 | remote-endpoint = <&mdp5_intf3_out>; | |
594 | }; | |
d98de8ef VG |
595 | }; |
596 | }; | |
597 | }; | |
d98de8ef | 598 | |
50aa72cc BA |
599 | hdmi_phy: hdmi-phy@9a0600 { |
600 | #phy-cells = <0>; | |
601 | compatible = "qcom,hdmi-phy-8996"; | |
602 | reg = <0x009a0600 0x1c4>, | |
603 | <0x009a0a00 0x124>, | |
604 | <0x009a0c00 0x124>, | |
605 | <0x009a0e00 0x124>, | |
606 | <0x009a1000 0x124>, | |
607 | <0x009a1200 0x0c8>; | |
608 | reg-names = "hdmi_pll", | |
609 | "hdmi_tx_l0", | |
610 | "hdmi_tx_l1", | |
611 | "hdmi_tx_l2", | |
612 | "hdmi_tx_l3", | |
613 | "hdmi_phy"; | |
d98de8ef | 614 | |
50aa72cc BA |
615 | clocks = <&mmcc MDSS_AHB_CLK>, |
616 | <&gcc GCC_HDMI_CLKREF_CLK>; | |
617 | clock-names = "iface", | |
618 | "ref"; | |
619 | }; | |
620 | }; | |
621 | gpu@b00000 { | |
622 | compatible = "qcom,adreno-530.2", "qcom,adreno"; | |
623 | #stream-id-cells = <16>; | |
d98de8ef | 624 | |
50aa72cc BA |
625 | reg = <0x00b00000 0x3f000>; |
626 | reg-names = "kgsl_3d0_reg_memory"; | |
d98de8ef | 627 | |
50aa72cc | 628 | interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>; |
d98de8ef | 629 | |
50aa72cc BA |
630 | clocks = <&mmcc GPU_GX_GFX3D_CLK>, |
631 | <&mmcc GPU_AHB_CLK>, | |
632 | <&mmcc GPU_GX_RBBMTIMER_CLK>, | |
633 | <&gcc GCC_BIMC_GFX_CLK>, | |
634 | <&gcc GCC_MMSS_BIMC_GFX_CLK>; | |
d98de8ef | 635 | |
50aa72cc BA |
636 | clock-names = "core", |
637 | "iface", | |
638 | "rbbmtimer", | |
639 | "mem", | |
640 | "mem_iface"; | |
d98de8ef | 641 | |
50aa72cc BA |
642 | power-domains = <&mmcc GPU_GDSC>; |
643 | iommus = <&adreno_smmu 0>; | |
d98de8ef | 644 | |
50aa72cc BA |
645 | nvmem-cells = <&gpu_speed_bin>; |
646 | nvmem-cell-names = "speed_bin"; | |
d98de8ef | 647 | |
50aa72cc BA |
648 | qcom,gpu-quirk-two-pass-use-wfi; |
649 | qcom,gpu-quirk-fault-detect-mask; | |
d98de8ef | 650 | |
50aa72cc | 651 | operating-points-v2 = <&gpu_opp_table>; |
d98de8ef | 652 | |
50aa72cc BA |
653 | gpu_opp_table: opp-table { |
654 | compatible ="operating-points-v2"; | |
d98de8ef | 655 | |
50aa72cc BA |
656 | /* |
657 | * 624Mhz and 560Mhz are only available on speed | |
658 | * bin (1 << 0). All the rest are available on | |
659 | * all bins of the hardware | |
660 | */ | |
661 | opp-624000000 { | |
662 | opp-hz = /bits/ 64 <624000000>; | |
663 | opp-supported-hw = <0x01>; | |
664 | }; | |
665 | opp-560000000 { | |
666 | opp-hz = /bits/ 64 <560000000>; | |
667 | opp-supported-hw = <0x01>; | |
668 | }; | |
669 | opp-510000000 { | |
670 | opp-hz = /bits/ 64 <510000000>; | |
671 | opp-supported-hw = <0xFF>; | |
672 | }; | |
673 | opp-401800000 { | |
674 | opp-hz = /bits/ 64 <401800000>; | |
675 | opp-supported-hw = <0xFF>; | |
676 | }; | |
677 | opp-315000000 { | |
678 | opp-hz = /bits/ 64 <315000000>; | |
679 | opp-supported-hw = <0xFF>; | |
680 | }; | |
681 | opp-214000000 { | |
682 | opp-hz = /bits/ 64 <214000000>; | |
683 | opp-supported-hw = <0xFF>; | |
684 | }; | |
685 | opp-133000000 { | |
686 | opp-hz = /bits/ 64 <133000000>; | |
687 | opp-supported-hw = <0xFF>; | |
d98de8ef VG |
688 | }; |
689 | }; | |
d98de8ef | 690 | |
50aa72cc BA |
691 | zap-shader { |
692 | memory-region = <&zap_shader_region>; | |
693 | }; | |
694 | }; | |
d98de8ef | 695 | |
50aa72cc BA |
696 | msmgpio: pinctrl@1010000 { |
697 | compatible = "qcom,msm8996-pinctrl"; | |
698 | reg = <0x01010000 0x300000>; | |
699 | interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; | |
700 | gpio-controller; | |
297177a4 | 701 | gpio-ranges = <&msmgpio 0 0 150>; |
50aa72cc BA |
702 | #gpio-cells = <2>; |
703 | interrupt-controller; | |
704 | #interrupt-cells = <2>; | |
705 | }; | |
d98de8ef | 706 | |
50aa72cc BA |
707 | spmi_bus: qcom,spmi@400f000 { |
708 | compatible = "qcom,spmi-pmic-arb"; | |
709 | reg = <0x0400f000 0x1000>, | |
710 | <0x04400000 0x800000>, | |
711 | <0x04c00000 0x800000>, | |
712 | <0x05800000 0x200000>, | |
713 | <0x0400a000 0x002100>; | |
714 | reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; | |
715 | interrupt-names = "periph_irq"; | |
716 | interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; | |
717 | qcom,ee = <0>; | |
718 | qcom,channel = <0>; | |
719 | #address-cells = <2>; | |
720 | #size-cells = <0>; | |
721 | interrupt-controller; | |
722 | #interrupt-cells = <4>; | |
d98de8ef VG |
723 | }; |
724 | ||
50aa72cc BA |
725 | agnoc@0 { |
726 | power-domains = <&gcc AGGRE0_NOC_GDSC>; | |
727 | compatible = "simple-pm-bus"; | |
728 | #address-cells = <1>; | |
729 | #size-cells = <1>; | |
730 | ranges; | |
d98de8ef | 731 | |
50aa72cc BA |
732 | pcie0: pcie@600000 { |
733 | compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; | |
734 | status = "disabled"; | |
735 | power-domains = <&gcc PCIE0_GDSC>; | |
736 | bus-range = <0x00 0xff>; | |
737 | num-lanes = <1>; | |
d98de8ef | 738 | |
50aa72cc BA |
739 | reg = <0x00600000 0x2000>, |
740 | <0x0c000000 0xf1d>, | |
741 | <0x0c000f20 0xa8>, | |
742 | <0x0c100000 0x100000>; | |
743 | reg-names = "parf", "dbi", "elbi","config"; | |
d98de8ef | 744 | |
50aa72cc BA |
745 | phys = <&pciephy_0>; |
746 | phy-names = "pciephy"; | |
d98de8ef | 747 | |
50aa72cc BA |
748 | #address-cells = <3>; |
749 | #size-cells = <2>; | |
750 | ranges = <0x01000000 0x0 0x0c200000 0x0c200000 0x0 0x100000>, | |
751 | <0x02000000 0x0 0x0c300000 0x0c300000 0x0 0xd00000>; | |
d98de8ef | 752 | |
50aa72cc BA |
753 | interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; |
754 | interrupt-names = "msi"; | |
755 | #interrupt-cells = <1>; | |
756 | interrupt-map-mask = <0 0 0 0x7>; | |
757 | interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
758 | <0 0 0 2 &intc 0 245 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
759 | <0 0 0 3 &intc 0 247 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
760 | <0 0 0 4 &intc 0 248 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
d98de8ef | 761 | |
50aa72cc BA |
762 | pinctrl-names = "default", "sleep"; |
763 | pinctrl-0 = <&pcie0_clkreq_default &pcie0_perst_default &pcie0_wake_default>; | |
764 | pinctrl-1 = <&pcie0_clkreq_sleep &pcie0_perst_default &pcie0_wake_sleep>; | |
d98de8ef | 765 | |
50aa72cc | 766 | linux,pci-domain = <0>; |
d98de8ef | 767 | |
50aa72cc BA |
768 | clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, |
769 | <&gcc GCC_PCIE_0_AUX_CLK>, | |
770 | <&gcc GCC_PCIE_0_CFG_AHB_CLK>, | |
771 | <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, | |
772 | <&gcc GCC_PCIE_0_SLV_AXI_CLK>; | |
d98de8ef | 773 | |
50aa72cc BA |
774 | clock-names = "pipe", |
775 | "aux", | |
776 | "cfg", | |
777 | "bus_master", | |
778 | "bus_slave"; | |
d98de8ef | 779 | |
50aa72cc | 780 | }; |
d98de8ef | 781 | |
50aa72cc BA |
782 | pcie1: pcie@608000 { |
783 | compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; | |
784 | power-domains = <&gcc PCIE1_GDSC>; | |
785 | bus-range = <0x00 0xff>; | |
786 | num-lanes = <1>; | |
d98de8ef | 787 | |
50aa72cc | 788 | status = "disabled"; |
d98de8ef | 789 | |
50aa72cc BA |
790 | reg = <0x00608000 0x2000>, |
791 | <0x0d000000 0xf1d>, | |
792 | <0x0d000f20 0xa8>, | |
793 | <0x0d100000 0x100000>; | |
d98de8ef | 794 | |
50aa72cc | 795 | reg-names = "parf", "dbi", "elbi","config"; |
d98de8ef | 796 | |
50aa72cc BA |
797 | phys = <&pciephy_1>; |
798 | phy-names = "pciephy"; | |
d98de8ef | 799 | |
50aa72cc BA |
800 | #address-cells = <3>; |
801 | #size-cells = <2>; | |
802 | ranges = <0x01000000 0x0 0x0d200000 0x0d200000 0x0 0x100000>, | |
803 | <0x02000000 0x0 0x0d300000 0x0d300000 0x0 0xd00000>; | |
99c3334d | 804 | |
50aa72cc BA |
805 | interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; |
806 | interrupt-names = "msi"; | |
807 | #interrupt-cells = <1>; | |
808 | interrupt-map-mask = <0 0 0 0x7>; | |
809 | interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
810 | <0 0 0 2 &intc 0 273 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
811 | <0 0 0 3 &intc 0 274 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
812 | <0 0 0 4 &intc 0 275 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
813 | ||
814 | pinctrl-names = "default", "sleep"; | |
815 | pinctrl-0 = <&pcie1_clkreq_default &pcie1_perst_default &pcie1_wake_default>; | |
816 | pinctrl-1 = <&pcie1_clkreq_sleep &pcie1_perst_default &pcie1_wake_sleep>; | |
817 | ||
818 | linux,pci-domain = <1>; | |
819 | ||
820 | clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, | |
821 | <&gcc GCC_PCIE_1_AUX_CLK>, | |
822 | <&gcc GCC_PCIE_1_CFG_AHB_CLK>, | |
823 | <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, | |
824 | <&gcc GCC_PCIE_1_SLV_AXI_CLK>; | |
825 | ||
826 | clock-names = "pipe", | |
827 | "aux", | |
828 | "cfg", | |
829 | "bus_master", | |
830 | "bus_slave"; | |
831 | }; | |
832 | ||
833 | pcie2: pcie@610000 { | |
834 | compatible = "qcom,pcie-msm8996", "snps,dw-pcie"; | |
835 | power-domains = <&gcc PCIE2_GDSC>; | |
836 | bus-range = <0x00 0xff>; | |
837 | num-lanes = <1>; | |
838 | status = "disabled"; | |
839 | reg = <0x00610000 0x2000>, | |
840 | <0x0e000000 0xf1d>, | |
841 | <0x0e000f20 0xa8>, | |
842 | <0x0e100000 0x100000>; | |
843 | ||
844 | reg-names = "parf", "dbi", "elbi","config"; | |
845 | ||
846 | phys = <&pciephy_2>; | |
847 | phy-names = "pciephy"; | |
848 | ||
849 | #address-cells = <3>; | |
850 | #size-cells = <2>; | |
851 | ranges = <0x01000000 0x0 0x0e200000 0x0e200000 0x0 0x100000>, | |
852 | <0x02000000 0x0 0x0e300000 0x0e300000 0x0 0x1d00000>; | |
853 | ||
854 | device_type = "pci"; | |
855 | ||
856 | interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; | |
857 | interrupt-names = "msi"; | |
858 | #interrupt-cells = <1>; | |
859 | interrupt-map-mask = <0 0 0 0x7>; | |
860 | interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ | |
861 | <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ | |
862 | <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ | |
863 | <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ | |
864 | ||
865 | pinctrl-names = "default", "sleep"; | |
866 | pinctrl-0 = <&pcie2_clkreq_default &pcie2_perst_default &pcie2_wake_default>; | |
867 | pinctrl-1 = <&pcie2_clkreq_sleep &pcie2_perst_default &pcie2_wake_sleep >; | |
868 | ||
869 | linux,pci-domain = <2>; | |
870 | clocks = <&gcc GCC_PCIE_2_PIPE_CLK>, | |
871 | <&gcc GCC_PCIE_2_AUX_CLK>, | |
872 | <&gcc GCC_PCIE_2_CFG_AHB_CLK>, | |
873 | <&gcc GCC_PCIE_2_MSTR_AXI_CLK>, | |
874 | <&gcc GCC_PCIE_2_SLV_AXI_CLK>; | |
875 | ||
876 | clock-names = "pipe", | |
877 | "aux", | |
878 | "cfg", | |
879 | "bus_master", | |
880 | "bus_slave"; | |
881 | }; | |
882 | }; | |
883 | ||
884 | ufshc: ufshc@624000 { | |
885 | compatible = "qcom,ufshc"; | |
886 | reg = <0x00624000 0x2500>; | |
887 | interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; | |
888 | ||
27520210 | 889 | phys = <&ufsphy_lane>; |
50aa72cc BA |
890 | phy-names = "ufsphy"; |
891 | ||
892 | power-domains = <&gcc UFS_GDSC>; | |
893 | ||
894 | clock-names = | |
895 | "core_clk_src", | |
896 | "core_clk", | |
897 | "bus_clk", | |
898 | "bus_aggr_clk", | |
899 | "iface_clk", | |
900 | "core_clk_unipro_src", | |
901 | "core_clk_unipro", | |
902 | "core_clk_ice", | |
903 | "ref_clk", | |
904 | "tx_lane0_sync_clk", | |
905 | "rx_lane0_sync_clk"; | |
906 | clocks = | |
907 | <&gcc UFS_AXI_CLK_SRC>, | |
908 | <&gcc GCC_UFS_AXI_CLK>, | |
909 | <&gcc GCC_SYS_NOC_UFS_AXI_CLK>, | |
910 | <&gcc GCC_AGGRE2_UFS_AXI_CLK>, | |
911 | <&gcc GCC_UFS_AHB_CLK>, | |
912 | <&gcc UFS_ICE_CORE_CLK_SRC>, | |
913 | <&gcc GCC_UFS_UNIPRO_CORE_CLK>, | |
914 | <&gcc GCC_UFS_ICE_CORE_CLK>, | |
915 | <&rpmcc RPM_SMD_LN_BB_CLK>, | |
916 | <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, | |
917 | <&gcc GCC_UFS_RX_SYMBOL_0_CLK>; | |
918 | freq-table-hz = | |
919 | <100000000 200000000>, | |
920 | <0 0>, | |
921 | <0 0>, | |
922 | <0 0>, | |
923 | <0 0>, | |
924 | <150000000 300000000>, | |
925 | <0 0>, | |
926 | <0 0>, | |
927 | <0 0>, | |
928 | <0 0>, | |
929 | <0 0>; | |
930 | ||
931 | lanes-per-direction = <1>; | |
932 | #reset-cells = <1>; | |
3e4cb730 | 933 | status = "disabled"; |
50aa72cc BA |
934 | |
935 | ufs_variant { | |
936 | compatible = "qcom,ufs_variant"; | |
937 | }; | |
938 | }; | |
939 | ||
940 | ufsphy: phy@627000 { | |
27520210 BA |
941 | compatible = "qcom,msm8996-qmp-ufs-phy"; |
942 | reg = <0x00627000 0x1c4>; | |
943 | #address-cells = <1>; | |
944 | #size-cells = <1>; | |
945 | ranges; | |
946 | ||
947 | clocks = <&gcc GCC_UFS_CLKREF_CLK>; | |
948 | clock-names = "ref"; | |
949 | ||
50aa72cc | 950 | resets = <&ufshc 0>; |
27520210 | 951 | reset-names = "ufsphy"; |
50aa72cc | 952 | status = "disabled"; |
27520210 BA |
953 | |
954 | ufsphy_lane: lanes@627400 { | |
955 | reg = <0x627400 0x12c>, | |
956 | <0x627600 0x200>, | |
957 | <0x627c00 0x1b4>; | |
958 | #phy-cells = <0>; | |
959 | }; | |
50aa72cc BA |
960 | }; |
961 | ||
962 | camss: camss@a00000 { | |
963 | compatible = "qcom,msm8996-camss"; | |
964 | reg = <0x00a34000 0x1000>, | |
965 | <0x00a00030 0x4>, | |
966 | <0x00a35000 0x1000>, | |
967 | <0x00a00038 0x4>, | |
968 | <0x00a36000 0x1000>, | |
969 | <0x00a00040 0x4>, | |
970 | <0x00a30000 0x100>, | |
971 | <0x00a30400 0x100>, | |
972 | <0x00a30800 0x100>, | |
973 | <0x00a30c00 0x100>, | |
974 | <0x00a31000 0x500>, | |
975 | <0x00a00020 0x10>, | |
976 | <0x00a10000 0x1000>, | |
977 | <0x00a14000 0x1000>; | |
978 | reg-names = "csiphy0", | |
979 | "csiphy0_clk_mux", | |
980 | "csiphy1", | |
981 | "csiphy1_clk_mux", | |
982 | "csiphy2", | |
983 | "csiphy2_clk_mux", | |
984 | "csid0", | |
985 | "csid1", | |
986 | "csid2", | |
987 | "csid3", | |
988 | "ispif", | |
989 | "csi_clk_mux", | |
990 | "vfe0", | |
991 | "vfe1"; | |
992 | interrupts = <GIC_SPI 78 0>, | |
993 | <GIC_SPI 79 0>, | |
994 | <GIC_SPI 80 0>, | |
995 | <GIC_SPI 296 0>, | |
996 | <GIC_SPI 297 0>, | |
997 | <GIC_SPI 298 0>, | |
998 | <GIC_SPI 299 0>, | |
999 | <GIC_SPI 309 0>, | |
1000 | <GIC_SPI 314 0>, | |
1001 | <GIC_SPI 315 0>; | |
1002 | interrupt-names = "csiphy0", | |
1003 | "csiphy1", | |
1004 | "csiphy2", | |
1005 | "csid0", | |
1006 | "csid1", | |
1007 | "csid2", | |
1008 | "csid3", | |
1009 | "ispif", | |
1010 | "vfe0", | |
1011 | "vfe1"; | |
1012 | power-domains = <&mmcc VFE0_GDSC>; | |
1013 | clocks = <&mmcc CAMSS_TOP_AHB_CLK>, | |
1014 | <&mmcc CAMSS_ISPIF_AHB_CLK>, | |
1015 | <&mmcc CAMSS_CSI0PHYTIMER_CLK>, | |
1016 | <&mmcc CAMSS_CSI1PHYTIMER_CLK>, | |
1017 | <&mmcc CAMSS_CSI2PHYTIMER_CLK>, | |
1018 | <&mmcc CAMSS_CSI0_AHB_CLK>, | |
1019 | <&mmcc CAMSS_CSI0_CLK>, | |
1020 | <&mmcc CAMSS_CSI0PHY_CLK>, | |
1021 | <&mmcc CAMSS_CSI0PIX_CLK>, | |
1022 | <&mmcc CAMSS_CSI0RDI_CLK>, | |
1023 | <&mmcc CAMSS_CSI1_AHB_CLK>, | |
1024 | <&mmcc CAMSS_CSI1_CLK>, | |
1025 | <&mmcc CAMSS_CSI1PHY_CLK>, | |
1026 | <&mmcc CAMSS_CSI1PIX_CLK>, | |
1027 | <&mmcc CAMSS_CSI1RDI_CLK>, | |
1028 | <&mmcc CAMSS_CSI2_AHB_CLK>, | |
1029 | <&mmcc CAMSS_CSI2_CLK>, | |
1030 | <&mmcc CAMSS_CSI2PHY_CLK>, | |
1031 | <&mmcc CAMSS_CSI2PIX_CLK>, | |
1032 | <&mmcc CAMSS_CSI2RDI_CLK>, | |
1033 | <&mmcc CAMSS_CSI3_AHB_CLK>, | |
1034 | <&mmcc CAMSS_CSI3_CLK>, | |
1035 | <&mmcc CAMSS_CSI3PHY_CLK>, | |
1036 | <&mmcc CAMSS_CSI3PIX_CLK>, | |
1037 | <&mmcc CAMSS_CSI3RDI_CLK>, | |
1038 | <&mmcc CAMSS_AHB_CLK>, | |
1039 | <&mmcc CAMSS_VFE0_CLK>, | |
1040 | <&mmcc CAMSS_CSI_VFE0_CLK>, | |
1041 | <&mmcc CAMSS_VFE0_AHB_CLK>, | |
1042 | <&mmcc CAMSS_VFE0_STREAM_CLK>, | |
1043 | <&mmcc CAMSS_VFE1_CLK>, | |
1044 | <&mmcc CAMSS_CSI_VFE1_CLK>, | |
1045 | <&mmcc CAMSS_VFE1_AHB_CLK>, | |
1046 | <&mmcc CAMSS_VFE1_STREAM_CLK>, | |
1047 | <&mmcc CAMSS_VFE_AHB_CLK>, | |
1048 | <&mmcc CAMSS_VFE_AXI_CLK>; | |
1049 | clock-names = "top_ahb", | |
1050 | "ispif_ahb", | |
1051 | "csiphy0_timer", | |
1052 | "csiphy1_timer", | |
1053 | "csiphy2_timer", | |
1054 | "csi0_ahb", | |
1055 | "csi0", | |
1056 | "csi0_phy", | |
1057 | "csi0_pix", | |
1058 | "csi0_rdi", | |
1059 | "csi1_ahb", | |
1060 | "csi1", | |
1061 | "csi1_phy", | |
1062 | "csi1_pix", | |
1063 | "csi1_rdi", | |
1064 | "csi2_ahb", | |
1065 | "csi2", | |
1066 | "csi2_phy", | |
1067 | "csi2_pix", | |
1068 | "csi2_rdi", | |
1069 | "csi3_ahb", | |
1070 | "csi3", | |
1071 | "csi3_phy", | |
1072 | "csi3_pix", | |
1073 | "csi3_rdi", | |
1074 | "ahb", | |
1075 | "vfe0", | |
1076 | "csi_vfe0", | |
1077 | "vfe0_ahb", | |
1078 | "vfe0_stream", | |
1079 | "vfe1", | |
1080 | "csi_vfe1", | |
1081 | "vfe1_ahb", | |
1082 | "vfe1_stream", | |
1083 | "vfe_ahb", | |
1084 | "vfe_axi"; | |
1085 | iommus = <&vfe_smmu 0>, | |
1086 | <&vfe_smmu 1>, | |
1087 | <&vfe_smmu 2>, | |
1088 | <&vfe_smmu 3>; | |
1089 | status = "disabled"; | |
1090 | ports { | |
1091 | #address-cells = <1>; | |
1092 | #size-cells = <0>; | |
1093 | }; | |
3e4cb730 TE |
1094 | }; |
1095 | ||
50aa72cc BA |
1096 | adreno_smmu: iommu@b40000 { |
1097 | compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; | |
1098 | reg = <0x00b40000 0x10000>; | |
1099 | ||
1100 | #global-interrupts = <1>; | |
1101 | interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
1102 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
1103 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; | |
1104 | #iommu-cells = <1>; | |
1105 | ||
1106 | clocks = <&mmcc GPU_AHB_CLK>, | |
1107 | <&gcc GCC_MMSS_BIMC_GFX_CLK>; | |
1108 | clock-names = "iface", "bus"; | |
1109 | ||
1110 | power-domains = <&mmcc GPU_GDSC>; | |
604677b4 SK |
1111 | }; |
1112 | ||
50aa72cc BA |
1113 | video-codec@c00000 { |
1114 | compatible = "qcom,msm8996-venus"; | |
1115 | reg = <0x00c00000 0xff000>; | |
1116 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
1117 | power-domains = <&mmcc VENUS_GDSC>; | |
1118 | clocks = <&mmcc VIDEO_CORE_CLK>, | |
1119 | <&mmcc VIDEO_AHB_CLK>, | |
1120 | <&mmcc VIDEO_AXI_CLK>, | |
1121 | <&mmcc VIDEO_MAXI_CLK>; | |
1122 | clock-names = "core", "iface", "bus", "mbus"; | |
1123 | iommus = <&venus_smmu 0x00>, | |
1124 | <&venus_smmu 0x01>, | |
1125 | <&venus_smmu 0x0a>, | |
1126 | <&venus_smmu 0x07>, | |
1127 | <&venus_smmu 0x0e>, | |
1128 | <&venus_smmu 0x0f>, | |
1129 | <&venus_smmu 0x08>, | |
1130 | <&venus_smmu 0x09>, | |
1131 | <&venus_smmu 0x0b>, | |
1132 | <&venus_smmu 0x0c>, | |
1133 | <&venus_smmu 0x0d>, | |
1134 | <&venus_smmu 0x10>, | |
1135 | <&venus_smmu 0x11>, | |
1136 | <&venus_smmu 0x21>, | |
1137 | <&venus_smmu 0x28>, | |
1138 | <&venus_smmu 0x29>, | |
1139 | <&venus_smmu 0x2b>, | |
1140 | <&venus_smmu 0x2c>, | |
1141 | <&venus_smmu 0x2d>, | |
1142 | <&venus_smmu 0x31>; | |
1143 | memory-region = <&venus_region>; | |
1144 | status = "okay"; | |
1145 | ||
1146 | video-decoder { | |
1147 | compatible = "venus-decoder"; | |
1148 | clocks = <&mmcc VIDEO_SUBCORE0_CLK>; | |
1149 | clock-names = "core"; | |
1150 | power-domains = <&mmcc VENUS_CORE0_GDSC>; | |
1151 | }; | |
1152 | ||
1153 | video-encoder { | |
1154 | compatible = "venus-encoder"; | |
1155 | clocks = <&mmcc VIDEO_SUBCORE1_CLK>; | |
1156 | clock-names = "core"; | |
1157 | power-domains = <&mmcc VENUS_CORE1_GDSC>; | |
1158 | }; | |
bf5443bc SK |
1159 | }; |
1160 | ||
50aa72cc BA |
1161 | mdp_smmu: iommu@d00000 { |
1162 | compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; | |
1163 | reg = <0x00d00000 0x10000>; | |
1164 | ||
1165 | #global-interrupts = <1>; | |
1166 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, | |
1167 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
1168 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; | |
1169 | #iommu-cells = <1>; | |
1170 | clocks = <&mmcc SMMU_MDP_AHB_CLK>, | |
1171 | <&mmcc SMMU_MDP_AXI_CLK>; | |
1172 | clock-names = "iface", "bus"; | |
1173 | ||
1174 | power-domains = <&mmcc MDSS_GDSC>; | |
4558e9b3 SB |
1175 | }; |
1176 | ||
277a13b5 | 1177 | venus_smmu: iommu@d40000 { |
50aa72cc | 1178 | compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; |
277a13b5 | 1179 | reg = <0x00d40000 0x20000>; |
50aa72cc BA |
1180 | #global-interrupts = <1>; |
1181 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, | |
1182 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, | |
1183 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
1184 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
1185 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
1186 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
1187 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
1188 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; | |
1189 | power-domains = <&mmcc MMAGIC_VIDEO_GDSC>; | |
1190 | clocks = <&mmcc SMMU_VIDEO_AHB_CLK>, | |
1191 | <&mmcc SMMU_VIDEO_AXI_CLK>; | |
1192 | clock-names = "iface", "bus"; | |
1193 | #iommu-cells = <1>; | |
1194 | status = "okay"; | |
d41d0cee SK |
1195 | }; |
1196 | ||
50aa72cc BA |
1197 | vfe_smmu: iommu@da0000 { |
1198 | compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; | |
1199 | reg = <0x00da0000 0x10000>; | |
1200 | ||
1201 | #global-interrupts = <1>; | |
1202 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, | |
1203 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, | |
1204 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; | |
1205 | power-domains = <&mmcc MMAGIC_CAMSS_GDSC>; | |
1206 | clocks = <&mmcc SMMU_VFE_AHB_CLK>, | |
1207 | <&mmcc SMMU_VFE_AXI_CLK>; | |
1208 | clock-names = "iface", | |
1209 | "bus"; | |
1210 | #iommu-cells = <1>; | |
fda48e61 SK |
1211 | }; |
1212 | ||
50aa72cc BA |
1213 | lpass_q6_smmu: iommu@1600000 { |
1214 | compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2"; | |
1215 | reg = <0x01600000 0x20000>; | |
1216 | #iommu-cells = <1>; | |
1217 | power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>; | |
1218 | ||
1219 | #global-interrupts = <1>; | |
1220 | interrupts = <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
1221 | <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, | |
1222 | <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, | |
1223 | <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, | |
1224 | <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, | |
1225 | <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, | |
1226 | <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, | |
1227 | <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
1228 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
1229 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
1230 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
1231 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
1232 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>; | |
1233 | ||
1234 | clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>, | |
1235 | <&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; | |
1236 | clock-names = "iface", "bus"; | |
21a40384 SK |
1237 | }; |
1238 | ||
50aa72cc BA |
1239 | stm@3002000 { |
1240 | compatible = "arm,coresight-stm", "arm,primecell"; | |
1241 | reg = <0x3002000 0x1000>, | |
1242 | <0x8280000 0x180000>; | |
1243 | reg-names = "stm-base", "stm-stimulus-base"; | |
1244 | ||
1245 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; | |
1246 | clock-names = "apb_pclk", "atclk"; | |
1247 | ||
1248 | out-ports { | |
1249 | port { | |
1250 | stm_out: endpoint { | |
1251 | remote-endpoint = | |
1252 | <&funnel0_in>; | |
1253 | }; | |
1254 | }; | |
1255 | }; | |
db6c8c83 SK |
1256 | }; |
1257 | ||
50aa72cc BA |
1258 | tpiu@3020000 { |
1259 | compatible = "arm,coresight-tpiu", "arm,primecell"; | |
1260 | reg = <0x3020000 0x1000>; | |
1261 | ||
1262 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; | |
1263 | clock-names = "apb_pclk", "atclk"; | |
1264 | ||
1265 | in-ports { | |
1266 | port { | |
1267 | tpiu_in: endpoint { | |
1268 | remote-endpoint = | |
1269 | <&replicator_out1>; | |
1270 | }; | |
1271 | }; | |
1272 | }; | |
1273 | }; | |
1274 | ||
1275 | funnel@3021000 { | |
1276 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
1277 | reg = <0x3021000 0x1000>; | |
1278 | ||
1279 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; | |
1280 | clock-names = "apb_pclk", "atclk"; | |
a6702798 | 1281 | |
50aa72cc BA |
1282 | in-ports { |
1283 | #address-cells = <1>; | |
1284 | #size-cells = <0>; | |
a6702798 | 1285 | |
50aa72cc BA |
1286 | port@7 { |
1287 | reg = <7>; | |
1288 | funnel0_in: endpoint { | |
1289 | remote-endpoint = | |
1290 | <&stm_out>; | |
1291 | }; | |
1292 | }; | |
1293 | }; | |
a6702798 | 1294 | |
50aa72cc BA |
1295 | out-ports { |
1296 | port { | |
1297 | funnel0_out: endpoint { | |
1298 | remote-endpoint = | |
1299 | <&merge_funnel_in0>; | |
1300 | }; | |
1301 | }; | |
1302 | }; | |
4558e9b3 SB |
1303 | }; |
1304 | ||
50aa72cc BA |
1305 | funnel@3022000 { |
1306 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
1307 | reg = <0x3022000 0x1000>; | |
4558e9b3 | 1308 | |
50aa72cc BA |
1309 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1310 | clock-names = "apb_pclk", "atclk"; | |
4558e9b3 | 1311 | |
50aa72cc BA |
1312 | in-ports { |
1313 | #address-cells = <1>; | |
1314 | #size-cells = <0>; | |
4558e9b3 | 1315 | |
50aa72cc BA |
1316 | port@6 { |
1317 | reg = <6>; | |
1318 | funnel1_in: endpoint { | |
1319 | remote-endpoint = | |
1320 | <&apss_merge_funnel_out>; | |
1321 | }; | |
1322 | }; | |
4558e9b3 SB |
1323 | }; |
1324 | ||
50aa72cc BA |
1325 | out-ports { |
1326 | port { | |
1327 | funnel1_out: endpoint { | |
1328 | remote-endpoint = | |
1329 | <&merge_funnel_in1>; | |
1330 | }; | |
1331 | }; | |
4558e9b3 | 1332 | }; |
50aa72cc | 1333 | }; |
4558e9b3 | 1334 | |
50aa72cc BA |
1335 | funnel@3023000 { |
1336 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
1337 | reg = <0x3023000 0x1000>; | |
4558e9b3 | 1338 | |
50aa72cc BA |
1339 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1340 | clock-names = "apb_pclk", "atclk"; | |
4558e9b3 | 1341 | |
50aa72cc BA |
1342 | |
1343 | out-ports { | |
1344 | port { | |
1345 | funnel2_out: endpoint { | |
1346 | remote-endpoint = | |
1347 | <&merge_funnel_in2>; | |
1348 | }; | |
1349 | }; | |
4558e9b3 SB |
1350 | }; |
1351 | }; | |
1352 | ||
50aa72cc BA |
1353 | funnel@3025000 { |
1354 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
1355 | reg = <0x3025000 0x1000>; | |
4558e9b3 | 1356 | |
50aa72cc BA |
1357 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1358 | clock-names = "apb_pclk", "atclk"; | |
57fc67ef | 1359 | |
50aa72cc BA |
1360 | in-ports { |
1361 | #address-cells = <1>; | |
1362 | #size-cells = <0>; | |
1363 | ||
1364 | port@0 { | |
1365 | reg = <0>; | |
1366 | merge_funnel_in0: endpoint { | |
1367 | remote-endpoint = | |
1368 | <&funnel0_out>; | |
1369 | }; | |
1370 | }; | |
1371 | ||
1372 | port@1 { | |
1373 | reg = <1>; | |
1374 | merge_funnel_in1: endpoint { | |
1375 | remote-endpoint = | |
1376 | <&funnel1_out>; | |
1377 | }; | |
1378 | }; | |
1379 | ||
1380 | port@2 { | |
1381 | reg = <2>; | |
1382 | merge_funnel_in2: endpoint { | |
1383 | remote-endpoint = | |
1384 | <&funnel2_out>; | |
1385 | }; | |
1386 | }; | |
1387 | }; | |
1388 | ||
1389 | out-ports { | |
1390 | port { | |
1391 | merge_funnel_out: endpoint { | |
1392 | remote-endpoint = | |
1393 | <&etf_in>; | |
1394 | }; | |
1395 | }; | |
1396 | }; | |
57fc67ef BA |
1397 | }; |
1398 | ||
50aa72cc BA |
1399 | replicator@3026000 { |
1400 | compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; | |
1401 | reg = <0x3026000 0x1000>; | |
57fc67ef | 1402 | |
50aa72cc BA |
1403 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1404 | clock-names = "apb_pclk", "atclk"; | |
57fc67ef | 1405 | |
50aa72cc BA |
1406 | in-ports { |
1407 | port { | |
1408 | replicator_in: endpoint { | |
1409 | remote-endpoint = | |
1410 | <&etf_out>; | |
1411 | }; | |
1412 | }; | |
1413 | }; | |
94dc9f48 | 1414 | |
50aa72cc BA |
1415 | out-ports { |
1416 | #address-cells = <1>; | |
1417 | #size-cells = <0>; | |
57fc67ef | 1418 | |
50aa72cc BA |
1419 | port@0 { |
1420 | reg = <0>; | |
1421 | replicator_out0: endpoint { | |
1422 | remote-endpoint = | |
1423 | <&etr_in>; | |
1424 | }; | |
1425 | }; | |
57fc67ef | 1426 | |
50aa72cc BA |
1427 | port@1 { |
1428 | reg = <1>; | |
1429 | replicator_out1: endpoint { | |
1430 | remote-endpoint = | |
1431 | <&tpiu_in>; | |
1432 | }; | |
1433 | }; | |
57fc67ef BA |
1434 | }; |
1435 | }; | |
1436 | ||
50aa72cc BA |
1437 | etf@3027000 { |
1438 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
1439 | reg = <0x3027000 0x1000>; | |
6785fa95 | 1440 | |
50aa72cc BA |
1441 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1442 | clock-names = "apb_pclk", "atclk"; | |
6785fa95 | 1443 | |
50aa72cc BA |
1444 | in-ports { |
1445 | port { | |
1446 | etf_in: endpoint { | |
1447 | remote-endpoint = | |
1448 | <&merge_funnel_out>; | |
1449 | }; | |
1450 | }; | |
6785fa95 VG |
1451 | }; |
1452 | ||
50aa72cc BA |
1453 | out-ports { |
1454 | port { | |
1455 | etf_out: endpoint { | |
1456 | remote-endpoint = | |
1457 | <&replicator_in>; | |
1458 | }; | |
1459 | }; | |
6785fa95 | 1460 | }; |
50aa72cc | 1461 | }; |
69cc3114 | 1462 | |
50aa72cc BA |
1463 | etr@3028000 { |
1464 | compatible = "arm,coresight-tmc", "arm,primecell"; | |
1465 | reg = <0x3028000 0x1000>; | |
1466 | ||
1467 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; | |
1468 | clock-names = "apb_pclk", "atclk"; | |
1469 | arm,scatter-gather; | |
1470 | ||
1471 | in-ports { | |
1472 | port { | |
1473 | etr_in: endpoint { | |
1474 | remote-endpoint = | |
1475 | <&replicator_out0>; | |
1476 | }; | |
1477 | }; | |
69cc3114 | 1478 | }; |
6785fa95 VG |
1479 | }; |
1480 | ||
50aa72cc BA |
1481 | debug@3810000 { |
1482 | compatible = "arm,coresight-cpu-debug", "arm,primecell"; | |
1483 | reg = <0x3810000 0x1000>; | |
12c67fe6 | 1484 | |
50aa72cc BA |
1485 | clocks = <&rpmcc RPM_QDSS_CLK>; |
1486 | clock-names = "apb_pclk"; | |
12c67fe6 | 1487 | |
50aa72cc BA |
1488 | cpu = <&CPU0>; |
1489 | }; | |
12c67fe6 | 1490 | |
50aa72cc BA |
1491 | etm@3840000 { |
1492 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
1493 | reg = <0x3840000 0x1000>; | |
12c67fe6 | 1494 | |
50aa72cc BA |
1495 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1496 | clock-names = "apb_pclk", "atclk"; | |
12c67fe6 | 1497 | |
50aa72cc | 1498 | cpu = <&CPU0>; |
12c67fe6 | 1499 | |
50aa72cc BA |
1500 | out-ports { |
1501 | port { | |
1502 | etm0_out: endpoint { | |
1503 | remote-endpoint = | |
1504 | <&apss_funnel0_in0>; | |
1505 | }; | |
1506 | }; | |
12c67fe6 | 1507 | }; |
50aa72cc | 1508 | }; |
12c67fe6 | 1509 | |
50aa72cc BA |
1510 | debug@3910000 { |
1511 | compatible = "arm,coresight-cpu-debug", "arm,primecell"; | |
1512 | reg = <0x3910000 0x1000>; | |
12c67fe6 | 1513 | |
50aa72cc BA |
1514 | clocks = <&rpmcc RPM_QDSS_CLK>; |
1515 | clock-names = "apb_pclk"; | |
12c67fe6 | 1516 | |
50aa72cc BA |
1517 | cpu = <&CPU1>; |
1518 | }; | |
42bd0544 | 1519 | |
50aa72cc BA |
1520 | etm@3940000 { |
1521 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
1522 | reg = <0x3940000 0x1000>; | |
42bd0544 | 1523 | |
50aa72cc BA |
1524 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1525 | clock-names = "apb_pclk", "atclk"; | |
42bd0544 | 1526 | |
50aa72cc | 1527 | cpu = <&CPU1>; |
42bd0544 | 1528 | |
50aa72cc BA |
1529 | out-ports { |
1530 | port { | |
1531 | etm1_out: endpoint { | |
1532 | remote-endpoint = | |
1533 | <&apss_funnel0_in1>; | |
1534 | }; | |
1535 | }; | |
42bd0544 VG |
1536 | }; |
1537 | }; | |
1538 | ||
50aa72cc BA |
1539 | funnel@39b0000 { /* APSS Funnel 0 */ |
1540 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
1541 | reg = <0x39b0000 0x1000>; | |
6785fa95 | 1542 | |
50aa72cc BA |
1543 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1544 | clock-names = "apb_pclk", "atclk"; | |
6785fa95 | 1545 | |
50aa72cc BA |
1546 | in-ports { |
1547 | #address-cells = <1>; | |
1548 | #size-cells = <0>; | |
6785fa95 | 1549 | |
50aa72cc BA |
1550 | port@0 { |
1551 | reg = <0>; | |
1552 | apss_funnel0_in0: endpoint { | |
1553 | remote-endpoint = <&etm0_out>; | |
1554 | }; | |
1555 | }; | |
6785fa95 | 1556 | |
50aa72cc BA |
1557 | port@1 { |
1558 | reg = <1>; | |
1559 | apss_funnel0_in1: endpoint { | |
1560 | remote-endpoint = <&etm1_out>; | |
1561 | }; | |
1562 | }; | |
1563 | }; | |
6785fa95 | 1564 | |
50aa72cc BA |
1565 | out-ports { |
1566 | port { | |
1567 | apss_funnel0_out: endpoint { | |
1568 | remote-endpoint = | |
1569 | <&apss_merge_funnel_in0>; | |
1570 | }; | |
1571 | }; | |
1572 | }; | |
6785fa95 | 1573 | }; |
1e39255e | 1574 | |
50aa72cc BA |
1575 | debug@3a10000 { |
1576 | compatible = "arm,coresight-cpu-debug", "arm,primecell"; | |
1577 | reg = <0x3a10000 0x1000>; | |
1578 | ||
1579 | clocks = <&rpmcc RPM_QDSS_CLK>; | |
1580 | clock-names = "apb_pclk"; | |
1581 | ||
1582 | cpu = <&CPU2>; | |
1583 | }; | |
1e39255e | 1584 | |
50aa72cc BA |
1585 | etm@3a40000 { |
1586 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
1587 | reg = <0x3a40000 0x1000>; | |
1e39255e | 1588 | |
50aa72cc BA |
1589 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1590 | clock-names = "apb_pclk", "atclk"; | |
1e39255e | 1591 | |
50aa72cc | 1592 | cpu = <&CPU2>; |
1e39255e | 1593 | |
50aa72cc BA |
1594 | out-ports { |
1595 | port { | |
1596 | etm2_out: endpoint { | |
1597 | remote-endpoint = | |
1598 | <&apss_funnel1_in0>; | |
1599 | }; | |
1600 | }; | |
1e39255e VG |
1601 | }; |
1602 | }; | |
1603 | ||
50aa72cc BA |
1604 | debug@3b10000 { |
1605 | compatible = "arm,coresight-cpu-debug", "arm,primecell"; | |
1606 | reg = <0x3b10000 0x1000>; | |
1e39255e | 1607 | |
50aa72cc BA |
1608 | clocks = <&rpmcc RPM_QDSS_CLK>; |
1609 | clock-names = "apb_pclk"; | |
1e39255e | 1610 | |
50aa72cc BA |
1611 | cpu = <&CPU3>; |
1612 | }; | |
1e39255e | 1613 | |
50aa72cc BA |
1614 | etm@3b40000 { |
1615 | compatible = "arm,coresight-etm4x", "arm,primecell"; | |
1616 | reg = <0x3b40000 0x1000>; | |
1e39255e | 1617 | |
50aa72cc BA |
1618 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1619 | clock-names = "apb_pclk", "atclk"; | |
1620 | ||
1621 | cpu = <&CPU3>; | |
1622 | ||
1623 | out-ports { | |
1624 | port { | |
1625 | etm3_out: endpoint { | |
1626 | remote-endpoint = | |
1627 | <&apss_funnel1_in1>; | |
1628 | }; | |
1629 | }; | |
1e39255e VG |
1630 | }; |
1631 | }; | |
ed965ef8 | 1632 | |
50aa72cc BA |
1633 | funnel@3bb0000 { /* APSS Funnel 1 */ |
1634 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
1635 | reg = <0x3bb0000 0x1000>; | |
f3442ab9 | 1636 | |
50aa72cc BA |
1637 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1638 | clock-names = "apb_pclk", "atclk"; | |
f3442ab9 | 1639 | |
50aa72cc | 1640 | in-ports { |
e0531312 TT |
1641 | #address-cells = <1>; |
1642 | #size-cells = <0>; | |
d26c474d | 1643 | |
50aa72cc BA |
1644 | port@0 { |
1645 | reg = <0>; | |
1646 | apss_funnel1_in0: endpoint { | |
1647 | remote-endpoint = <&etm2_out>; | |
1648 | }; | |
1649 | }; | |
d26c474d | 1650 | |
50aa72cc BA |
1651 | port@1 { |
1652 | reg = <1>; | |
1653 | apss_funnel1_in1: endpoint { | |
1654 | remote-endpoint = <&etm3_out>; | |
1655 | }; | |
1656 | }; | |
1657 | }; | |
d26c474d | 1658 | |
50aa72cc BA |
1659 | out-ports { |
1660 | port { | |
1661 | apss_funnel1_out: endpoint { | |
1662 | remote-endpoint = | |
1663 | <&apss_merge_funnel_in1>; | |
1664 | }; | |
1665 | }; | |
1666 | }; | |
d26c474d JC |
1667 | }; |
1668 | ||
50aa72cc BA |
1669 | funnel@3bc0000 { |
1670 | compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; | |
1671 | reg = <0x3bc0000 0x1000>; | |
953f6573 | 1672 | |
50aa72cc BA |
1673 | clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>; |
1674 | clock-names = "apb_pclk", "atclk"; | |
953f6573 | 1675 | |
50aa72cc BA |
1676 | in-ports { |
1677 | #address-cells = <1>; | |
1678 | #size-cells = <0>; | |
953f6573 | 1679 | |
50aa72cc BA |
1680 | port@0 { |
1681 | reg = <0>; | |
1682 | apss_merge_funnel_in0: endpoint { | |
1683 | remote-endpoint = | |
1684 | <&apss_funnel0_out>; | |
1685 | }; | |
1686 | }; | |
f3eb39a5 | 1687 | |
50aa72cc BA |
1688 | port@1 { |
1689 | reg = <1>; | |
1690 | apss_merge_funnel_in1: endpoint { | |
1691 | remote-endpoint = | |
1692 | <&apss_funnel1_out>; | |
1693 | }; | |
1694 | }; | |
1695 | }; | |
f3eb39a5 | 1696 | |
50aa72cc BA |
1697 | out-ports { |
1698 | port { | |
1699 | apss_merge_funnel_out: endpoint { | |
1700 | remote-endpoint = | |
1701 | <&funnel1_in>; | |
1702 | }; | |
1703 | }; | |
1704 | }; | |
1705 | }; | |
1706 | kryocc: clock-controller@6400000 { | |
1707 | compatible = "qcom,apcc-msm8996"; | |
1708 | reg = <0x06400000 0x90000>; | |
1709 | #clock-cells = <1>; | |
f3eb39a5 SK |
1710 | }; |
1711 | ||
50aa72cc BA |
1712 | usb3: usb@6af8800 { |
1713 | compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; | |
1714 | reg = <0x06af8800 0x400>; | |
ed965ef8 SK |
1715 | #address-cells = <1>; |
1716 | #size-cells = <1>; | |
1717 | ranges; | |
1718 | ||
50aa72cc BA |
1719 | clocks = <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, |
1720 | <&gcc GCC_USB30_MASTER_CLK>, | |
1721 | <&gcc GCC_AGGRE2_USB3_AXI_CLK>, | |
1722 | <&gcc GCC_USB30_MOCK_UTMI_CLK>, | |
1723 | <&gcc GCC_USB30_SLEEP_CLK>, | |
1724 | <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; | |
ed965ef8 | 1725 | |
50aa72cc BA |
1726 | assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, |
1727 | <&gcc GCC_USB30_MASTER_CLK>; | |
1728 | assigned-clock-rates = <19200000>, <120000000>; | |
ed965ef8 | 1729 | |
50aa72cc BA |
1730 | power-domains = <&gcc USB30_GDSC>; |
1731 | status = "disabled"; | |
ed965ef8 | 1732 | |
50aa72cc BA |
1733 | dwc3@6a00000 { |
1734 | compatible = "snps,dwc3"; | |
1735 | reg = <0x06a00000 0xcc00>; | |
1736 | interrupts = <0 131 IRQ_TYPE_LEVEL_HIGH>; | |
1737 | phys = <&hsusb_phy1>, <&ssusb_phy_0>; | |
1738 | phy-names = "usb2-phy", "usb3-phy"; | |
1739 | snps,dis_u2_susphy_quirk; | |
1740 | snps,dis_enblslpm_quirk; | |
1741 | }; | |
1742 | }; | |
ed965ef8 | 1743 | |
50aa72cc BA |
1744 | usb3phy: phy@7410000 { |
1745 | compatible = "qcom,msm8996-qmp-usb3-phy"; | |
1746 | reg = <0x07410000 0x1c4>; | |
1747 | #clock-cells = <1>; | |
1748 | #address-cells = <1>; | |
1749 | #size-cells = <1>; | |
1750 | ranges; | |
ed965ef8 | 1751 | |
50aa72cc BA |
1752 | clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, |
1753 | <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, | |
1754 | <&gcc GCC_USB3_CLKREF_CLK>; | |
1755 | clock-names = "aux", "cfg_ahb", "ref"; | |
ed965ef8 | 1756 | |
50aa72cc BA |
1757 | resets = <&gcc GCC_USB3_PHY_BCR>, |
1758 | <&gcc GCC_USB3PHY_PHY_BCR>; | |
1759 | reset-names = "phy", "common"; | |
1760 | status = "disabled"; | |
ed965ef8 | 1761 | |
50aa72cc BA |
1762 | ssusb_phy_0: lane@7410200 { |
1763 | reg = <0x07410200 0x200>, | |
1764 | <0x07410400 0x130>, | |
1765 | <0x07410600 0x1a8>; | |
1766 | #phy-cells = <0>; | |
ed965ef8 | 1767 | |
50aa72cc BA |
1768 | clock-output-names = "usb3_phy_pipe_clk_src"; |
1769 | clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>; | |
1770 | clock-names = "pipe0"; | |
ed965ef8 | 1771 | }; |
50aa72cc | 1772 | }; |
ed965ef8 | 1773 | |
50aa72cc BA |
1774 | hsusb_phy1: phy@7411000 { |
1775 | compatible = "qcom,msm8996-qusb2-phy"; | |
1776 | reg = <0x07411000 0x180>; | |
1777 | #phy-cells = <0>; | |
ed965ef8 | 1778 | |
50aa72cc BA |
1779 | clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
1780 | <&gcc GCC_RX1_USB2_CLKREF_CLK>; | |
1781 | clock-names = "cfg_ahb", "ref"; | |
ed965ef8 | 1782 | |
50aa72cc BA |
1783 | resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
1784 | nvmem-cells = <&qusb2p_hstx_trim>; | |
1785 | status = "disabled"; | |
1786 | }; | |
ed965ef8 | 1787 | |
50aa72cc BA |
1788 | hsusb_phy2: phy@7412000 { |
1789 | compatible = "qcom,msm8996-qusb2-phy"; | |
1790 | reg = <0x07412000 0x180>; | |
1791 | #phy-cells = <0>; | |
ed965ef8 | 1792 | |
50aa72cc BA |
1793 | clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, |
1794 | <&gcc GCC_RX2_USB2_CLKREF_CLK>; | |
1795 | clock-names = "cfg_ahb", "ref"; | |
ed965ef8 | 1796 | |
50aa72cc BA |
1797 | resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; |
1798 | nvmem-cells = <&qusb2s_hstx_trim>; | |
1799 | status = "disabled"; | |
1800 | }; | |
ed965ef8 | 1801 | |
50aa72cc BA |
1802 | sdhc2: sdhci@74a4900 { |
1803 | status = "disabled"; | |
1804 | compatible = "qcom,sdhci-msm-v4"; | |
1805 | reg = <0x074a4900 0x314>, <0x074a4000 0x800>; | |
1806 | reg-names = "hc_mem", "core_mem"; | |
ed965ef8 | 1807 | |
50aa72cc BA |
1808 | interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>, |
1809 | <0 221 IRQ_TYPE_LEVEL_HIGH>; | |
1810 | interrupt-names = "hc_irq", "pwr_irq"; | |
ed965ef8 | 1811 | |
50aa72cc BA |
1812 | clock-names = "iface", "core", "xo"; |
1813 | clocks = <&gcc GCC_SDCC2_AHB_CLK>, | |
1814 | <&gcc GCC_SDCC2_APPS_CLK>, | |
1815 | <&xo_board>; | |
1816 | bus-width = <4>; | |
1817 | }; | |
1818 | ||
1819 | blsp1_uart1: serial@7570000 { | |
1820 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
1821 | reg = <0x07570000 0x1000>; | |
1822 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; | |
1823 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, | |
1824 | <&gcc GCC_BLSP1_AHB_CLK>; | |
1825 | clock-names = "core", "iface"; | |
1826 | status = "disabled"; | |
1827 | }; | |
1828 | ||
1829 | blsp1_spi0: spi@7575000 { | |
1830 | compatible = "qcom,spi-qup-v2.2.1"; | |
1831 | reg = <0x07575000 0x600>; | |
1832 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; | |
1833 | clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, | |
1834 | <&gcc GCC_BLSP1_AHB_CLK>; | |
1835 | clock-names = "core", "iface"; | |
1836 | pinctrl-names = "default", "sleep"; | |
1837 | pinctrl-0 = <&blsp1_spi0_default>; | |
1838 | pinctrl-1 = <&blsp1_spi0_sleep>; | |
1839 | #address-cells = <1>; | |
1840 | #size-cells = <0>; | |
1841 | status = "disabled"; | |
1842 | }; | |
ed965ef8 | 1843 | |
50aa72cc BA |
1844 | blsp1_i2c2: i2c@7577000 { |
1845 | compatible = "qcom,i2c-qup-v2.2.1"; | |
1846 | reg = <0x07577000 0x1000>; | |
1847 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
1848 | clocks = <&gcc GCC_BLSP1_AHB_CLK>, | |
1849 | <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; | |
1850 | clock-names = "iface", "core"; | |
1851 | pinctrl-names = "default", "sleep"; | |
1852 | pinctrl-0 = <&blsp1_i2c2_default>; | |
1853 | pinctrl-1 = <&blsp1_i2c2_sleep>; | |
1854 | #address-cells = <1>; | |
1855 | #size-cells = <0>; | |
1856 | status = "disabled"; | |
1857 | }; | |
ed965ef8 | 1858 | |
50aa72cc BA |
1859 | blsp2_uart1: serial@75b0000 { |
1860 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
1861 | reg = <0x075b0000 0x1000>; | |
1862 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
1863 | clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, | |
1864 | <&gcc GCC_BLSP2_AHB_CLK>; | |
1865 | clock-names = "core", "iface"; | |
1866 | status = "disabled"; | |
1867 | }; | |
ed965ef8 | 1868 | |
50aa72cc BA |
1869 | blsp2_uart2: serial@75b1000 { |
1870 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
1871 | reg = <0x075b1000 0x1000>; | |
1872 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
1873 | clocks = <&gcc GCC_BLSP2_UART3_APPS_CLK>, | |
1874 | <&gcc GCC_BLSP2_AHB_CLK>; | |
1875 | clock-names = "core", "iface"; | |
1876 | status = "disabled"; | |
1877 | }; | |
ed965ef8 | 1878 | |
50aa72cc BA |
1879 | blsp2_i2c0: i2c@75b5000 { |
1880 | compatible = "qcom,i2c-qup-v2.2.1"; | |
1881 | reg = <0x075b5000 0x1000>; | |
1882 | interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
1883 | clocks = <&gcc GCC_BLSP2_AHB_CLK>, | |
1884 | <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>; | |
1885 | clock-names = "iface", "core"; | |
1886 | pinctrl-names = "default", "sleep"; | |
1887 | pinctrl-0 = <&blsp2_i2c0_default>; | |
1888 | pinctrl-1 = <&blsp2_i2c0_sleep>; | |
1889 | #address-cells = <1>; | |
1890 | #size-cells = <0>; | |
1891 | status = "disabled"; | |
1892 | }; | |
ed965ef8 | 1893 | |
50aa72cc BA |
1894 | blsp2_i2c1: i2c@75b6000 { |
1895 | compatible = "qcom,i2c-qup-v2.2.1"; | |
1896 | reg = <0x075b6000 0x1000>; | |
1897 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; | |
1898 | clocks = <&gcc GCC_BLSP2_AHB_CLK>, | |
1899 | <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>; | |
1900 | clock-names = "iface", "core"; | |
1901 | pinctrl-names = "default", "sleep"; | |
1902 | pinctrl-0 = <&blsp2_i2c1_default>; | |
1903 | pinctrl-1 = <&blsp2_i2c1_sleep>; | |
1904 | #address-cells = <1>; | |
1905 | #size-cells = <0>; | |
1906 | status = "disabled"; | |
1907 | }; | |
ed965ef8 | 1908 | |
50aa72cc BA |
1909 | blsp2_spi5: spi@75ba000{ |
1910 | compatible = "qcom,spi-qup-v2.2.1"; | |
1911 | reg = <0x075ba000 0x600>; | |
1912 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
1913 | clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, | |
1914 | <&gcc GCC_BLSP2_AHB_CLK>; | |
1915 | clock-names = "core", "iface"; | |
1916 | pinctrl-names = "default", "sleep"; | |
1917 | pinctrl-0 = <&blsp2_spi5_default>; | |
1918 | pinctrl-1 = <&blsp2_spi5_sleep>; | |
1919 | #address-cells = <1>; | |
1920 | #size-cells = <0>; | |
1921 | status = "disabled"; | |
1922 | }; | |
ed965ef8 | 1923 | |
50aa72cc BA |
1924 | usb2: usb@76f8800 { |
1925 | compatible = "qcom,msm8996-dwc3", "qcom,dwc3"; | |
1926 | reg = <0x076f8800 0x400>; | |
1927 | #address-cells = <1>; | |
1928 | #size-cells = <1>; | |
1929 | ranges; | |
ed965ef8 | 1930 | |
50aa72cc BA |
1931 | clocks = <&gcc GCC_PERIPH_NOC_USB20_AHB_CLK>, |
1932 | <&gcc GCC_USB20_MASTER_CLK>, | |
1933 | <&gcc GCC_USB20_MOCK_UTMI_CLK>, | |
1934 | <&gcc GCC_USB20_SLEEP_CLK>, | |
1935 | <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; | |
ed965ef8 | 1936 | |
50aa72cc BA |
1937 | assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, |
1938 | <&gcc GCC_USB20_MASTER_CLK>; | |
1939 | assigned-clock-rates = <19200000>, <60000000>; | |
ed965ef8 | 1940 | |
50aa72cc BA |
1941 | power-domains = <&gcc USB30_GDSC>; |
1942 | status = "disabled"; | |
ed965ef8 | 1943 | |
50aa72cc BA |
1944 | dwc3@7600000 { |
1945 | compatible = "snps,dwc3"; | |
1946 | reg = <0x07600000 0xcc00>; | |
1947 | interrupts = <0 138 IRQ_TYPE_LEVEL_HIGH>; | |
1948 | phys = <&hsusb_phy2>; | |
1949 | phy-names = "usb2-phy"; | |
1950 | snps,dis_u2_susphy_quirk; | |
1951 | snps,dis_enblslpm_quirk; | |
ed965ef8 SK |
1952 | }; |
1953 | }; | |
3a4547c1 | 1954 | |
50aa72cc | 1955 | slimbam: dma@9184000 { |
f3eb39a5 SK |
1956 | compatible = "qcom,bam-v1.7.0"; |
1957 | qcom,controlled-remotely; | |
86f6d622 | 1958 | reg = <0x09184000 0x32000>; |
f3eb39a5 SK |
1959 | num-channels = <31>; |
1960 | interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>; | |
1961 | #dma-cells = <1>; | |
1962 | qcom,ee = <1>; | |
1963 | qcom,num-ees = <2>; | |
1964 | }; | |
1965 | ||
1966 | slim_msm: slim@91c0000 { | |
1967 | compatible = "qcom,slim-ngd-v1.5.0"; | |
86f6d622 | 1968 | reg = <0x091c0000 0x2C000>; |
f3eb39a5 SK |
1969 | reg-names = "ctrl"; |
1970 | interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>; | |
50aa72cc BA |
1971 | dmas = <&slimbam 3>, <&slimbam 4>, |
1972 | <&slimbam 5>, <&slimbam 6>; | |
1973 | dma-names = "rx", "tx", "tx2", "rx2"; | |
1974 | #address-cells = <1>; | |
1975 | #size-cells = <0>; | |
1976 | ngd@1 { | |
1977 | reg = <1>; | |
1978 | #address-cells = <1>; | |
1979 | #size-cells = <1>; | |
1980 | ||
1981 | tasha_ifd: tas-ifd { | |
1982 | compatible = "slim217,1a0"; | |
1983 | reg = <0 0>; | |
69cc3114 | 1984 | }; |
69cc3114 | 1985 | |
50aa72cc BA |
1986 | wcd9335: codec@1{ |
1987 | pinctrl-0 = <&cdc_reset_active &wcd_intr_default>; | |
1988 | pinctrl-names = "default"; | |
69cc3114 | 1989 | |
50aa72cc BA |
1990 | compatible = "slim217,1a0"; |
1991 | reg = <1 0>; | |
3a4547c1 | 1992 | |
50aa72cc BA |
1993 | interrupt-parent = <&msmgpio>; |
1994 | interrupts = <54 IRQ_TYPE_LEVEL_HIGH>, | |
1995 | <53 IRQ_TYPE_LEVEL_HIGH>; | |
1996 | interrupt-names = "intr1", "intr2"; | |
1997 | interrupt-controller; | |
1998 | #interrupt-cells = <1>; | |
1999 | reset-gpios = <&msmgpio 64 0>; | |
3a4547c1 | 2000 | |
50aa72cc | 2001 | slim-ifc-dev = <&tasha_ifd>; |
3a4547c1 | 2002 | |
50aa72cc BA |
2003 | #sound-dai-cells = <1>; |
2004 | }; | |
2005 | }; | |
2006 | }; | |
3a4547c1 | 2007 | |
50aa72cc BA |
2008 | adsp_pil: remoteproc@9300000 { |
2009 | compatible = "qcom,msm8996-adsp-pil"; | |
2010 | reg = <0x09300000 0x80000>; | |
3a4547c1 | 2011 | |
50aa72cc BA |
2012 | interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>, |
2013 | <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, | |
2014 | <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, | |
2015 | <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, | |
2016 | <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; | |
2017 | interrupt-names = "wdog", "fatal", "ready", | |
2018 | "handover", "stop-ack"; | |
3a4547c1 | 2019 | |
50aa72cc BA |
2020 | clocks = <&xo_board>; |
2021 | clock-names = "xo"; | |
3a4547c1 | 2022 | |
50aa72cc | 2023 | memory-region = <&adsp_region>; |
3a4547c1 | 2024 | |
50aa72cc BA |
2025 | qcom,smem-states = <&smp2p_adsp_out 0>; |
2026 | qcom,smem-state-names = "stop"; | |
3a4547c1 | 2027 | |
50aa72cc BA |
2028 | smd-edge { |
2029 | interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; | |
3a4547c1 | 2030 | |
50aa72cc BA |
2031 | label = "lpass"; |
2032 | mboxes = <&apcs_glb 8>; | |
2033 | qcom,smd-edge = <1>; | |
2034 | qcom,remote-pid = <2>; | |
2035 | #address-cells = <1>; | |
2036 | #size-cells = <0>; | |
2037 | apr { | |
2038 | power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>; | |
2039 | compatible = "qcom,apr-v2"; | |
2040 | qcom,smd-channels = "apr_audio_svc"; | |
2041 | qcom,apr-domain = <APR_DOMAIN_ADSP>; | |
3a4547c1 AT |
2042 | #address-cells = <1>; |
2043 | #size-cells = <0>; | |
2044 | ||
50aa72cc BA |
2045 | q6core { |
2046 | reg = <APR_SVC_ADSP_CORE>; | |
2047 | compatible = "qcom,q6core"; | |
2048 | }; | |
2049 | ||
2050 | q6afe: q6afe { | |
2051 | compatible = "qcom,q6afe"; | |
2052 | reg = <APR_SVC_AFE>; | |
2053 | q6afedai: dais { | |
2054 | compatible = "qcom,q6afe-dais"; | |
2055 | #address-cells = <1>; | |
2056 | #size-cells = <0>; | |
2057 | #sound-dai-cells = <1>; | |
2058 | hdmi@1 { | |
2059 | reg = <1>; | |
2060 | }; | |
3a4547c1 AT |
2061 | }; |
2062 | }; | |
3a4547c1 | 2063 | |
50aa72cc BA |
2064 | q6asm: q6asm { |
2065 | compatible = "qcom,q6asm"; | |
2066 | reg = <APR_SVC_ASM>; | |
2067 | q6asmdai: dais { | |
2068 | compatible = "qcom,q6asm-dais"; | |
7710f80e SK |
2069 | #address-cells = <1>; |
2070 | #size-cells = <0>; | |
50aa72cc BA |
2071 | #sound-dai-cells = <1>; |
2072 | iommus = <&lpass_q6_smmu 1>; | |
2073 | }; | |
2074 | }; | |
3a4547c1 | 2075 | |
50aa72cc BA |
2076 | q6adm: q6adm { |
2077 | compatible = "qcom,q6adm"; | |
2078 | reg = <APR_SVC_ADM>; | |
2079 | q6routing: routing { | |
2080 | compatible = "qcom,q6adm-routing"; | |
2081 | #sound-dai-cells = <0>; | |
2082 | }; | |
2083 | }; | |
2084 | }; | |
3a4547c1 | 2085 | |
50aa72cc BA |
2086 | }; |
2087 | }; | |
3a4547c1 | 2088 | |
50aa72cc BA |
2089 | apcs_glb: mailbox@9820000 { |
2090 | compatible = "qcom,msm8996-apcs-hmss-global"; | |
2091 | reg = <0x09820000 0x1000>; | |
3a4547c1 | 2092 | |
50aa72cc BA |
2093 | #mbox-cells = <1>; |
2094 | }; | |
3a4547c1 | 2095 | |
50aa72cc BA |
2096 | timer@9840000 { |
2097 | #address-cells = <1>; | |
2098 | #size-cells = <1>; | |
2099 | ranges; | |
2100 | compatible = "arm,armv7-timer-mem"; | |
2101 | reg = <0x09840000 0x1000>; | |
2102 | clock-frequency = <19200000>; | |
2103 | ||
2104 | frame@9850000 { | |
2105 | frame-number = <0>; | |
2106 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, | |
2107 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
2108 | reg = <0x09850000 0x1000>, | |
2109 | <0x09860000 0x1000>; | |
3a4547c1 AT |
2110 | }; |
2111 | ||
50aa72cc BA |
2112 | frame@9870000 { |
2113 | frame-number = <1>; | |
2114 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
2115 | reg = <0x09870000 0x1000>; | |
2116 | status = "disabled"; | |
2117 | }; | |
3a4547c1 | 2118 | |
50aa72cc BA |
2119 | frame@9880000 { |
2120 | frame-number = <2>; | |
2121 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
2122 | reg = <0x09880000 0x1000>; | |
2123 | status = "disabled"; | |
3a4547c1 | 2124 | }; |
4e300e43 | 2125 | |
50aa72cc BA |
2126 | frame@9890000 { |
2127 | frame-number = <3>; | |
2128 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
2129 | reg = <0x09890000 0x1000>; | |
2130 | status = "disabled"; | |
2131 | }; | |
4e300e43 | 2132 | |
50aa72cc BA |
2133 | frame@98a0000 { |
2134 | frame-number = <4>; | |
2135 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
2136 | reg = <0x098a0000 0x1000>; | |
2137 | status = "disabled"; | |
2138 | }; | |
4e300e43 | 2139 | |
50aa72cc BA |
2140 | frame@98b0000 { |
2141 | frame-number = <5>; | |
2142 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
2143 | reg = <0x098b0000 0x1000>; | |
2144 | status = "disabled"; | |
4e300e43 SV |
2145 | }; |
2146 | ||
50aa72cc BA |
2147 | frame@98c0000 { |
2148 | frame-number = <6>; | |
2149 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
2150 | reg = <0x098c0000 0x1000>; | |
2151 | status = "disabled"; | |
4e300e43 SV |
2152 | }; |
2153 | }; | |
50aa72cc | 2154 | |
7a2a2231 LP |
2155 | saw3: syscon@9a10000 { |
2156 | compatible = "syscon"; | |
2157 | reg = <0x09a10000 0x1000>; | |
2158 | }; | |
2159 | ||
50aa72cc BA |
2160 | intc: interrupt-controller@9bc0000 { |
2161 | compatible = "qcom,msm8996-gic-v3", "arm,gic-v3"; | |
2162 | #interrupt-cells = <3>; | |
2163 | interrupt-controller; | |
2164 | #redistributor-regions = <1>; | |
2165 | redistributor-stride = <0x0 0x40000>; | |
2166 | reg = <0x09bc0000 0x10000>, | |
2167 | <0x09c00000 0x100000>; | |
2168 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; | |
2169 | }; | |
4558e9b3 | 2170 | }; |
2f45d9fc | 2171 | |
f3eb39a5 SK |
2172 | sound: sound { |
2173 | }; | |
2174 | ||
50aa72cc BA |
2175 | thermal-zones { |
2176 | cpu0-thermal { | |
2177 | polling-delay-passive = <250>; | |
2178 | polling-delay = <1000>; | |
6c8583d6 | 2179 | |
50aa72cc | 2180 | thermal-sensors = <&tsens0 3>; |
6c8583d6 | 2181 | |
50aa72cc BA |
2182 | trips { |
2183 | cpu0_alert0: trip-point@0 { | |
2184 | temperature = <75000>; | |
2185 | hysteresis = <2000>; | |
2186 | type = "passive"; | |
2187 | }; | |
6c8583d6 | 2188 | |
50aa72cc BA |
2189 | cpu0_crit: cpu_crit { |
2190 | temperature = <110000>; | |
2191 | hysteresis = <2000>; | |
2192 | type = "critical"; | |
2193 | }; | |
2194 | }; | |
2195 | }; | |
6c8583d6 | 2196 | |
50aa72cc BA |
2197 | cpu1-thermal { |
2198 | polling-delay-passive = <250>; | |
2199 | polling-delay = <1000>; | |
cadcd35f | 2200 | |
50aa72cc | 2201 | thermal-sensors = <&tsens0 5>; |
cadcd35f | 2202 | |
50aa72cc BA |
2203 | trips { |
2204 | cpu1_alert0: trip-point@0 { | |
2205 | temperature = <75000>; | |
2206 | hysteresis = <2000>; | |
2207 | type = "passive"; | |
2208 | }; | |
f3eb39a5 | 2209 | |
50aa72cc BA |
2210 | cpu1_crit: cpu_crit { |
2211 | temperature = <110000>; | |
2212 | hysteresis = <2000>; | |
2213 | type = "critical"; | |
f3eb39a5 | 2214 | }; |
50aa72cc BA |
2215 | }; |
2216 | }; | |
f3eb39a5 | 2217 | |
50aa72cc BA |
2218 | cpu2-thermal { |
2219 | polling-delay-passive = <250>; | |
2220 | polling-delay = <1000>; | |
2221 | ||
2222 | thermal-sensors = <&tsens0 8>; | |
2223 | ||
2224 | trips { | |
2225 | cpu2_alert0: trip-point@0 { | |
2226 | temperature = <75000>; | |
2227 | hysteresis = <2000>; | |
2228 | type = "passive"; | |
f3eb39a5 SK |
2229 | }; |
2230 | ||
50aa72cc BA |
2231 | cpu2_crit: cpu_crit { |
2232 | temperature = <110000>; | |
2233 | hysteresis = <2000>; | |
2234 | type = "critical"; | |
f3eb39a5 SK |
2235 | }; |
2236 | }; | |
50aa72cc BA |
2237 | }; |
2238 | ||
2239 | cpu3-thermal { | |
2240 | polling-delay-passive = <250>; | |
2241 | polling-delay = <1000>; | |
2242 | ||
2243 | thermal-sensors = <&tsens0 10>; | |
2244 | ||
2245 | trips { | |
2246 | cpu3_alert0: trip-point@0 { | |
2247 | temperature = <75000>; | |
2248 | hysteresis = <2000>; | |
2249 | type = "passive"; | |
2250 | }; | |
f3eb39a5 | 2251 | |
50aa72cc BA |
2252 | cpu3_crit: cpu_crit { |
2253 | temperature = <110000>; | |
2254 | hysteresis = <2000>; | |
2255 | type = "critical"; | |
2256 | }; | |
2257 | }; | |
cadcd35f | 2258 | }; |
6c8583d6 | 2259 | |
50aa72cc BA |
2260 | gpu-thermal-top { |
2261 | polling-delay-passive = <250>; | |
2262 | polling-delay = <1000>; | |
2f45d9fc | 2263 | |
50aa72cc | 2264 | thermal-sensors = <&tsens1 6>; |
2f45d9fc | 2265 | |
50aa72cc BA |
2266 | trips { |
2267 | gpu1_alert0: trip-point@0 { | |
2268 | temperature = <90000>; | |
2269 | hysteresis = <2000>; | |
2270 | type = "hot"; | |
2271 | }; | |
2272 | }; | |
2273 | }; | |
2f45d9fc | 2274 | |
50aa72cc BA |
2275 | gpu-thermal-bottom { |
2276 | polling-delay-passive = <250>; | |
2277 | polling-delay = <1000>; | |
2f45d9fc | 2278 | |
50aa72cc BA |
2279 | thermal-sensors = <&tsens1 7>; |
2280 | ||
2281 | trips { | |
2282 | gpu2_alert0: trip-point@0 { | |
2283 | temperature = <90000>; | |
2284 | hysteresis = <2000>; | |
2285 | type = "hot"; | |
2286 | }; | |
2287 | }; | |
2f45d9fc SJ |
2288 | }; |
2289 | ||
50aa72cc BA |
2290 | m4m-thermal { |
2291 | polling-delay-passive = <250>; | |
2292 | polling-delay = <1000>; | |
2f45d9fc | 2293 | |
50aa72cc BA |
2294 | thermal-sensors = <&tsens0 1>; |
2295 | ||
2296 | trips { | |
2297 | m4m_alert0: trip-point@0 { | |
2298 | temperature = <90000>; | |
2299 | hysteresis = <2000>; | |
2300 | type = "hot"; | |
2301 | }; | |
2302 | }; | |
2f45d9fc | 2303 | }; |
3f1802f8 | 2304 | |
50aa72cc BA |
2305 | l3-or-venus-thermal { |
2306 | polling-delay-passive = <250>; | |
2307 | polling-delay = <1000>; | |
a147eda7 | 2308 | |
50aa72cc | 2309 | thermal-sensors = <&tsens0 2>; |
a147eda7 | 2310 | |
50aa72cc BA |
2311 | trips { |
2312 | l3_or_venus_alert0: trip-point@0 { | |
2313 | temperature = <90000>; | |
2314 | hysteresis = <2000>; | |
2315 | type = "hot"; | |
2316 | }; | |
2317 | }; | |
2318 | }; | |
a147eda7 | 2319 | |
50aa72cc BA |
2320 | cluster0-l2-thermal { |
2321 | polling-delay-passive = <250>; | |
2322 | polling-delay = <1000>; | |
a147eda7 | 2323 | |
50aa72cc BA |
2324 | thermal-sensors = <&tsens0 7>; |
2325 | ||
2326 | trips { | |
2327 | cluster0_l2_alert0: trip-point@0 { | |
2328 | temperature = <90000>; | |
2329 | hysteresis = <2000>; | |
2330 | type = "hot"; | |
2331 | }; | |
2332 | }; | |
a147eda7 BA |
2333 | }; |
2334 | ||
50aa72cc BA |
2335 | cluster1-l2-thermal { |
2336 | polling-delay-passive = <250>; | |
2337 | polling-delay = <1000>; | |
a147eda7 | 2338 | |
50aa72cc BA |
2339 | thermal-sensors = <&tsens0 12>; |
2340 | ||
2341 | trips { | |
2342 | cluster1_l2_alert0: trip-point@0 { | |
2343 | temperature = <90000>; | |
2344 | hysteresis = <2000>; | |
2345 | type = "hot"; | |
2346 | }; | |
2347 | }; | |
a147eda7 | 2348 | }; |
a147eda7 | 2349 | |
50aa72cc BA |
2350 | camera-thermal { |
2351 | polling-delay-passive = <250>; | |
2352 | polling-delay = <1000>; | |
3f1802f8 | 2353 | |
50aa72cc | 2354 | thermal-sensors = <&tsens1 1>; |
3f1802f8 | 2355 | |
50aa72cc BA |
2356 | trips { |
2357 | camera_alert0: trip-point@0 { | |
2358 | temperature = <90000>; | |
2359 | hysteresis = <2000>; | |
2360 | type = "hot"; | |
2361 | }; | |
2362 | }; | |
2363 | }; | |
3f1802f8 | 2364 | |
50aa72cc BA |
2365 | q6-dsp-thermal { |
2366 | polling-delay-passive = <250>; | |
2367 | polling-delay = <1000>; | |
3f1802f8 | 2368 | |
50aa72cc BA |
2369 | thermal-sensors = <&tsens1 2>; |
2370 | ||
2371 | trips { | |
2372 | q6_dsp_alert0: trip-point@0 { | |
2373 | temperature = <90000>; | |
2374 | hysteresis = <2000>; | |
2375 | type = "hot"; | |
2376 | }; | |
2377 | }; | |
3f1802f8 AKD |
2378 | }; |
2379 | ||
50aa72cc BA |
2380 | mem-thermal { |
2381 | polling-delay-passive = <250>; | |
2382 | polling-delay = <1000>; | |
2383 | ||
2384 | thermal-sensors = <&tsens1 3>; | |
2385 | ||
2386 | trips { | |
2387 | mem_alert0: trip-point@0 { | |
2388 | temperature = <90000>; | |
2389 | hysteresis = <2000>; | |
2390 | type = "hot"; | |
2391 | }; | |
2392 | }; | |
2393 | }; | |
2394 | ||
2395 | modemtx-thermal { | |
2396 | polling-delay-passive = <250>; | |
2397 | polling-delay = <1000>; | |
2398 | ||
2399 | thermal-sensors = <&tsens1 4>; | |
2400 | ||
2401 | trips { | |
2402 | modemtx_alert0: trip-point@0 { | |
2403 | temperature = <90000>; | |
2404 | hysteresis = <2000>; | |
2405 | type = "hot"; | |
2406 | }; | |
2407 | }; | |
3f1802f8 AKD |
2408 | }; |
2409 | }; | |
2410 | ||
50aa72cc BA |
2411 | timer { |
2412 | compatible = "arm,armv8-timer"; | |
2413 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, | |
2414 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, | |
2415 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, | |
2416 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; | |
2417 | }; | |
4558e9b3 | 2418 | }; |
22e6789f | 2419 | #include "msm8996-pins.dtsi" |