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9b33e300 BD |
1 | // SPDX-License-Identifier: GPL-2.0 |
2 | /* | |
3 | * Device Tree Source for the r8a774b1 SoC | |
4 | * | |
5 | * Copyright (C) 2019 Renesas Electronics Corp. | |
6 | */ | |
7 | ||
8 | #include <dt-bindings/interrupt-controller/irq.h> | |
9 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
10 | #include <dt-bindings/clock/r8a774b1-cpg-mssr.h> | |
11 | #include <dt-bindings/power/r8a774b1-sysc.h> | |
12 | ||
13 | / { | |
14 | compatible = "renesas,r8a774b1"; | |
15 | #address-cells = <2>; | |
16 | #size-cells = <2>; | |
17 | ||
18 | /* | |
19 | * The external audio clocks are configured as 0 Hz fixed frequency | |
20 | * clocks by default. | |
21 | * Boards that provide audio clocks should override them. | |
22 | */ | |
23 | audio_clk_a: audio_clk_a { | |
24 | compatible = "fixed-clock"; | |
25 | #clock-cells = <0>; | |
26 | clock-frequency = <0>; | |
27 | }; | |
28 | ||
29 | audio_clk_b: audio_clk_b { | |
30 | compatible = "fixed-clock"; | |
31 | #clock-cells = <0>; | |
32 | clock-frequency = <0>; | |
33 | }; | |
34 | ||
35 | audio_clk_c: audio_clk_c { | |
36 | compatible = "fixed-clock"; | |
37 | #clock-cells = <0>; | |
38 | clock-frequency = <0>; | |
39 | }; | |
40 | ||
41 | /* External CAN clock - to be overridden by boards that provide it */ | |
42 | can_clk: can { | |
43 | compatible = "fixed-clock"; | |
44 | #clock-cells = <0>; | |
45 | clock-frequency = <0>; | |
46 | }; | |
47 | ||
7744b393 | 48 | cluster0_opp: opp-table-0 { |
ce21f290 BD |
49 | compatible = "operating-points-v2"; |
50 | opp-shared; | |
51 | ||
52 | opp-500000000 { | |
53 | opp-hz = /bits/ 64 <500000000>; | |
54 | opp-microvolt = <830000>; | |
55 | clock-latency-ns = <300000>; | |
56 | }; | |
57 | opp-1000000000 { | |
58 | opp-hz = /bits/ 64 <1000000000>; | |
59 | opp-microvolt = <830000>; | |
60 | clock-latency-ns = <300000>; | |
61 | }; | |
62 | opp-1500000000 { | |
63 | opp-hz = /bits/ 64 <1500000000>; | |
64 | opp-microvolt = <830000>; | |
65 | clock-latency-ns = <300000>; | |
66 | opp-suspend; | |
67 | }; | |
68 | }; | |
69 | ||
9b33e300 BD |
70 | cpus { |
71 | #address-cells = <1>; | |
72 | #size-cells = <0>; | |
73 | ||
74 | a57_0: cpu@0 { | |
75 | compatible = "arm,cortex-a57"; | |
76 | reg = <0x0>; | |
77 | device_type = "cpu"; | |
78 | power-domains = <&sysc R8A774B1_PD_CA57_CPU0>; | |
79 | next-level-cache = <&L2_CA57>; | |
80 | enable-method = "psci"; | |
81 | #cooling-cells = <2>; | |
82 | dynamic-power-coefficient = <854>; | |
83 | clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; | |
ce21f290 | 84 | operating-points-v2 = <&cluster0_opp>; |
9b33e300 BD |
85 | }; |
86 | ||
87 | a57_1: cpu@1 { | |
88 | compatible = "arm,cortex-a57"; | |
89 | reg = <0x1>; | |
90 | device_type = "cpu"; | |
91 | power-domains = <&sysc R8A774B1_PD_CA57_CPU1>; | |
92 | next-level-cache = <&L2_CA57>; | |
93 | enable-method = "psci"; | |
94 | clocks = <&cpg CPG_CORE R8A774B1_CLK_Z>; | |
ce21f290 | 95 | operating-points-v2 = <&cluster0_opp>; |
9b33e300 BD |
96 | }; |
97 | ||
98 | L2_CA57: cache-controller-0 { | |
99 | compatible = "cache"; | |
100 | power-domains = <&sysc R8A774B1_PD_CA57_SCU>; | |
101 | cache-unified; | |
102 | cache-level = <2>; | |
103 | }; | |
104 | }; | |
105 | ||
106 | extal_clk: extal { | |
107 | compatible = "fixed-clock"; | |
108 | #clock-cells = <0>; | |
109 | /* This value must be overridden by the board */ | |
110 | clock-frequency = <0>; | |
111 | }; | |
112 | ||
113 | extalr_clk: extalr { | |
114 | compatible = "fixed-clock"; | |
115 | #clock-cells = <0>; | |
116 | /* This value must be overridden by the board */ | |
117 | clock-frequency = <0>; | |
118 | }; | |
119 | ||
120 | /* External PCIe clock - can be overridden by the board */ | |
121 | pcie_bus_clk: pcie_bus { | |
122 | compatible = "fixed-clock"; | |
123 | #clock-cells = <0>; | |
124 | clock-frequency = <0>; | |
125 | }; | |
126 | ||
127 | pmu_a57 { | |
128 | compatible = "arm,cortex-a57-pmu"; | |
129 | interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
130 | <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
131 | interrupt-affinity = <&a57_0>, <&a57_1>; | |
132 | }; | |
133 | ||
134 | psci { | |
135 | compatible = "arm,psci-1.0", "arm,psci-0.2"; | |
136 | method = "smc"; | |
137 | }; | |
138 | ||
139 | /* External SCIF clock - to be overridden by boards that provide it */ | |
140 | scif_clk: scif { | |
141 | compatible = "fixed-clock"; | |
142 | #clock-cells = <0>; | |
143 | clock-frequency = <0>; | |
144 | }; | |
145 | ||
146 | soc { | |
147 | compatible = "simple-bus"; | |
148 | interrupt-parent = <&gic>; | |
149 | #address-cells = <2>; | |
150 | #size-cells = <2>; | |
151 | ranges; | |
152 | ||
153 | rwdt: watchdog@e6020000 { | |
7213aea4 FC |
154 | compatible = "renesas,r8a774b1-wdt", |
155 | "renesas,rcar-gen3-wdt"; | |
9b33e300 | 156 | reg = <0 0xe6020000 0 0x0c>; |
7ac8afba | 157 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
7213aea4 FC |
158 | clocks = <&cpg CPG_MOD 402>; |
159 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
160 | resets = <&cpg 402>; | |
161 | status = "disabled"; | |
9b33e300 BD |
162 | }; |
163 | ||
164 | gpio0: gpio@e6050000 { | |
bbbb919f BD |
165 | compatible = "renesas,gpio-r8a774b1", |
166 | "renesas,rcar-gen3-gpio"; | |
9b33e300 | 167 | reg = <0 0xe6050000 0 0x50>; |
bbbb919f | 168 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
9b33e300 BD |
169 | #gpio-cells = <2>; |
170 | gpio-controller; | |
bbbb919f | 171 | gpio-ranges = <&pfc 0 0 16>; |
9b33e300 BD |
172 | #interrupt-cells = <2>; |
173 | interrupt-controller; | |
bbbb919f BD |
174 | clocks = <&cpg CPG_MOD 912>; |
175 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
176 | resets = <&cpg 912>; | |
9b33e300 BD |
177 | }; |
178 | ||
179 | gpio1: gpio@e6051000 { | |
bbbb919f BD |
180 | compatible = "renesas,gpio-r8a774b1", |
181 | "renesas,rcar-gen3-gpio"; | |
9b33e300 | 182 | reg = <0 0xe6051000 0 0x50>; |
bbbb919f | 183 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
9b33e300 BD |
184 | #gpio-cells = <2>; |
185 | gpio-controller; | |
bbbb919f | 186 | gpio-ranges = <&pfc 0 32 29>; |
9b33e300 BD |
187 | #interrupt-cells = <2>; |
188 | interrupt-controller; | |
bbbb919f BD |
189 | clocks = <&cpg CPG_MOD 911>; |
190 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
191 | resets = <&cpg 911>; | |
9b33e300 BD |
192 | }; |
193 | ||
194 | gpio2: gpio@e6052000 { | |
bbbb919f BD |
195 | compatible = "renesas,gpio-r8a774b1", |
196 | "renesas,rcar-gen3-gpio"; | |
9b33e300 | 197 | reg = <0 0xe6052000 0 0x50>; |
bbbb919f | 198 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
9b33e300 BD |
199 | #gpio-cells = <2>; |
200 | gpio-controller; | |
bbbb919f | 201 | gpio-ranges = <&pfc 0 64 15>; |
9b33e300 BD |
202 | #interrupt-cells = <2>; |
203 | interrupt-controller; | |
bbbb919f BD |
204 | clocks = <&cpg CPG_MOD 910>; |
205 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
206 | resets = <&cpg 910>; | |
9b33e300 BD |
207 | }; |
208 | ||
209 | gpio3: gpio@e6053000 { | |
bbbb919f BD |
210 | compatible = "renesas,gpio-r8a774b1", |
211 | "renesas,rcar-gen3-gpio"; | |
9b33e300 | 212 | reg = <0 0xe6053000 0 0x50>; |
bbbb919f | 213 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
9b33e300 BD |
214 | #gpio-cells = <2>; |
215 | gpio-controller; | |
bbbb919f | 216 | gpio-ranges = <&pfc 0 96 16>; |
9b33e300 BD |
217 | #interrupt-cells = <2>; |
218 | interrupt-controller; | |
bbbb919f BD |
219 | clocks = <&cpg CPG_MOD 909>; |
220 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
221 | resets = <&cpg 909>; | |
9b33e300 BD |
222 | }; |
223 | ||
224 | gpio4: gpio@e6054000 { | |
bbbb919f BD |
225 | compatible = "renesas,gpio-r8a774b1", |
226 | "renesas,rcar-gen3-gpio"; | |
9b33e300 | 227 | reg = <0 0xe6054000 0 0x50>; |
bbbb919f | 228 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
9b33e300 BD |
229 | #gpio-cells = <2>; |
230 | gpio-controller; | |
bbbb919f | 231 | gpio-ranges = <&pfc 0 128 18>; |
9b33e300 BD |
232 | #interrupt-cells = <2>; |
233 | interrupt-controller; | |
bbbb919f BD |
234 | clocks = <&cpg CPG_MOD 908>; |
235 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
236 | resets = <&cpg 908>; | |
9b33e300 BD |
237 | }; |
238 | ||
239 | gpio5: gpio@e6055000 { | |
bbbb919f BD |
240 | compatible = "renesas,gpio-r8a774b1", |
241 | "renesas,rcar-gen3-gpio"; | |
9b33e300 | 242 | reg = <0 0xe6055000 0 0x50>; |
bbbb919f | 243 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
9b33e300 BD |
244 | #gpio-cells = <2>; |
245 | gpio-controller; | |
bbbb919f | 246 | gpio-ranges = <&pfc 0 160 26>; |
9b33e300 BD |
247 | #interrupt-cells = <2>; |
248 | interrupt-controller; | |
bbbb919f BD |
249 | clocks = <&cpg CPG_MOD 907>; |
250 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
251 | resets = <&cpg 907>; | |
9b33e300 BD |
252 | }; |
253 | ||
254 | gpio6: gpio@e6055400 { | |
bbbb919f BD |
255 | compatible = "renesas,gpio-r8a774b1", |
256 | "renesas,rcar-gen3-gpio"; | |
9b33e300 | 257 | reg = <0 0xe6055400 0 0x50>; |
bbbb919f | 258 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
9b33e300 BD |
259 | #gpio-cells = <2>; |
260 | gpio-controller; | |
bbbb919f | 261 | gpio-ranges = <&pfc 0 192 32>; |
9b33e300 BD |
262 | #interrupt-cells = <2>; |
263 | interrupt-controller; | |
bbbb919f BD |
264 | clocks = <&cpg CPG_MOD 906>; |
265 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
266 | resets = <&cpg 906>; | |
9b33e300 BD |
267 | }; |
268 | ||
269 | gpio7: gpio@e6055800 { | |
bbbb919f BD |
270 | compatible = "renesas,gpio-r8a774b1", |
271 | "renesas,rcar-gen3-gpio"; | |
9b33e300 | 272 | reg = <0 0xe6055800 0 0x50>; |
bbbb919f | 273 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
9b33e300 BD |
274 | #gpio-cells = <2>; |
275 | gpio-controller; | |
bbbb919f | 276 | gpio-ranges = <&pfc 0 224 4>; |
9b33e300 BD |
277 | #interrupt-cells = <2>; |
278 | interrupt-controller; | |
bbbb919f BD |
279 | clocks = <&cpg CPG_MOD 905>; |
280 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
281 | resets = <&cpg 905>; | |
9b33e300 BD |
282 | }; |
283 | ||
a2053990 | 284 | pfc: pinctrl@e6060000 { |
9b33e300 BD |
285 | compatible = "renesas,pfc-r8a774b1"; |
286 | reg = <0 0xe6060000 0 0x50c>; | |
287 | }; | |
288 | ||
39040e87 BD |
289 | cmt0: timer@e60f0000 { |
290 | compatible = "renesas,r8a774b1-cmt0", | |
291 | "renesas,rcar-gen3-cmt0"; | |
292 | reg = <0 0xe60f0000 0 0x1004>; | |
293 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
294 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
295 | clocks = <&cpg CPG_MOD 303>; | |
296 | clock-names = "fck"; | |
297 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
298 | resets = <&cpg 303>; | |
299 | status = "disabled"; | |
300 | }; | |
301 | ||
302 | cmt1: timer@e6130000 { | |
303 | compatible = "renesas,r8a774b1-cmt1", | |
304 | "renesas,rcar-gen3-cmt1"; | |
305 | reg = <0 0xe6130000 0 0x1004>; | |
306 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, | |
307 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
308 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
309 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
310 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
311 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
312 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
313 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
314 | clocks = <&cpg CPG_MOD 302>; | |
315 | clock-names = "fck"; | |
316 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
317 | resets = <&cpg 302>; | |
318 | status = "disabled"; | |
319 | }; | |
320 | ||
321 | cmt2: timer@e6140000 { | |
322 | compatible = "renesas,r8a774b1-cmt1", | |
323 | "renesas,rcar-gen3-cmt1"; | |
324 | reg = <0 0xe6140000 0 0x1004>; | |
325 | interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, | |
326 | <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, | |
327 | <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, | |
328 | <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, | |
329 | <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, | |
330 | <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, | |
331 | <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, | |
332 | <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; | |
333 | clocks = <&cpg CPG_MOD 301>; | |
334 | clock-names = "fck"; | |
335 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
336 | resets = <&cpg 301>; | |
337 | status = "disabled"; | |
338 | }; | |
339 | ||
340 | cmt3: timer@e6148000 { | |
341 | compatible = "renesas,r8a774b1-cmt1", | |
342 | "renesas,rcar-gen3-cmt1"; | |
343 | reg = <0 0xe6148000 0 0x1004>; | |
344 | interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, | |
345 | <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, | |
346 | <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, | |
347 | <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, | |
348 | <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, | |
349 | <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, | |
350 | <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, | |
351 | <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>; | |
352 | clocks = <&cpg CPG_MOD 300>; | |
353 | clock-names = "fck"; | |
354 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
355 | resets = <&cpg 300>; | |
356 | status = "disabled"; | |
357 | }; | |
358 | ||
9b33e300 BD |
359 | cpg: clock-controller@e6150000 { |
360 | compatible = "renesas,r8a774b1-cpg-mssr"; | |
361 | reg = <0 0xe6150000 0 0x1000>; | |
362 | clocks = <&extal_clk>, <&extalr_clk>; | |
363 | clock-names = "extal", "extalr"; | |
364 | #clock-cells = <2>; | |
365 | #power-domain-cells = <0>; | |
366 | #reset-cells = <1>; | |
367 | }; | |
368 | ||
369 | rst: reset-controller@e6160000 { | |
370 | compatible = "renesas,r8a774b1-rst"; | |
371 | reg = <0 0xe6160000 0 0x0200>; | |
372 | }; | |
373 | ||
374 | sysc: system-controller@e6180000 { | |
375 | compatible = "renesas,r8a774b1-sysc"; | |
376 | reg = <0 0xe6180000 0 0x0400>; | |
377 | #power-domain-cells = <1>; | |
378 | }; | |
379 | ||
95b3547f BD |
380 | tsc: thermal@e6198000 { |
381 | compatible = "renesas,r8a774b1-thermal"; | |
382 | reg = <0 0xe6198000 0 0x100>, | |
383 | <0 0xe61a0000 0 0x100>, | |
384 | <0 0xe61a8000 0 0x100>; | |
385 | interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, | |
386 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
387 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
388 | clocks = <&cpg CPG_MOD 522>; | |
389 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
390 | resets = <&cpg 522>; | |
391 | #thermal-sensor-cells = <1>; | |
392 | }; | |
393 | ||
04360e41 FC |
394 | intc_ex: interrupt-controller@e61c0000 { |
395 | compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc"; | |
396 | #interrupt-cells = <2>; | |
397 | interrupt-controller; | |
398 | reg = <0 0xe61c0000 0 0x200>; | |
0aab5b91 GU |
399 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
400 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
401 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
402 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
403 | <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, | |
404 | <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; | |
04360e41 FC |
405 | clocks = <&cpg CPG_MOD 407>; |
406 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
407 | resets = <&cpg 407>; | |
408 | }; | |
409 | ||
928249b7 BD |
410 | tmu0: timer@e61e0000 { |
411 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; | |
412 | reg = <0 0xe61e0000 0 0x30>; | |
413 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
414 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
415 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; | |
c53866cb | 416 | interrupt-names = "tuni0", "tuni1", "tuni2"; |
928249b7 BD |
417 | clocks = <&cpg CPG_MOD 125>; |
418 | clock-names = "fck"; | |
419 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
420 | resets = <&cpg 125>; | |
421 | status = "disabled"; | |
422 | }; | |
423 | ||
424 | tmu1: timer@e6fc0000 { | |
425 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; | |
426 | reg = <0 0xe6fc0000 0 0x30>; | |
427 | interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
428 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
c53866cb GU |
429 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, |
430 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
431 | interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; | |
928249b7 BD |
432 | clocks = <&cpg CPG_MOD 124>; |
433 | clock-names = "fck"; | |
434 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
435 | resets = <&cpg 124>; | |
436 | status = "disabled"; | |
437 | }; | |
438 | ||
439 | tmu2: timer@e6fd0000 { | |
440 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; | |
441 | reg = <0 0xe6fd0000 0 0x30>; | |
442 | interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, | |
443 | <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, | |
c53866cb GU |
444 | <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, |
445 | <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; | |
446 | interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; | |
928249b7 BD |
447 | clocks = <&cpg CPG_MOD 123>; |
448 | clock-names = "fck"; | |
449 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
450 | resets = <&cpg 123>; | |
451 | status = "disabled"; | |
452 | }; | |
453 | ||
454 | tmu3: timer@e6fe0000 { | |
455 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; | |
456 | reg = <0 0xe6fe0000 0 0x30>; | |
457 | interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
458 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
459 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; | |
c53866cb | 460 | interrupt-names = "tuni0", "tuni1", "tuni2"; |
928249b7 BD |
461 | clocks = <&cpg CPG_MOD 122>; |
462 | clock-names = "fck"; | |
463 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
464 | resets = <&cpg 122>; | |
465 | status = "disabled"; | |
466 | }; | |
467 | ||
468 | tmu4: timer@ffc00000 { | |
469 | compatible = "renesas,tmu-r8a774b1", "renesas,tmu"; | |
470 | reg = <0 0xffc00000 0 0x30>; | |
471 | interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, | |
472 | <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, | |
473 | <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; | |
c53866cb | 474 | interrupt-names = "tuni0", "tuni1", "tuni2"; |
928249b7 BD |
475 | clocks = <&cpg CPG_MOD 121>; |
476 | clock-names = "fck"; | |
477 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
478 | resets = <&cpg 121>; | |
479 | status = "disabled"; | |
480 | }; | |
481 | ||
070302d4 BD |
482 | i2c0: i2c@e6500000 { |
483 | #address-cells = <1>; | |
484 | #size-cells = <0>; | |
485 | compatible = "renesas,i2c-r8a774b1", | |
486 | "renesas,rcar-gen3-i2c"; | |
487 | reg = <0 0xe6500000 0 0x40>; | |
488 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; | |
489 | clocks = <&cpg CPG_MOD 931>; | |
490 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
491 | resets = <&cpg 931>; | |
492 | dmas = <&dmac1 0x91>, <&dmac1 0x90>, | |
493 | <&dmac2 0x91>, <&dmac2 0x90>; | |
494 | dma-names = "tx", "rx", "tx", "rx"; | |
495 | i2c-scl-internal-delay-ns = <110>; | |
496 | status = "disabled"; | |
497 | }; | |
498 | ||
499 | i2c1: i2c@e6508000 { | |
500 | #address-cells = <1>; | |
501 | #size-cells = <0>; | |
502 | compatible = "renesas,i2c-r8a774b1", | |
503 | "renesas,rcar-gen3-i2c"; | |
504 | reg = <0 0xe6508000 0 0x40>; | |
505 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; | |
506 | clocks = <&cpg CPG_MOD 930>; | |
507 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
508 | resets = <&cpg 930>; | |
509 | dmas = <&dmac1 0x93>, <&dmac1 0x92>, | |
510 | <&dmac2 0x93>, <&dmac2 0x92>; | |
511 | dma-names = "tx", "rx", "tx", "rx"; | |
512 | i2c-scl-internal-delay-ns = <6>; | |
513 | status = "disabled"; | |
514 | }; | |
515 | ||
516 | i2c2: i2c@e6510000 { | |
517 | #address-cells = <1>; | |
518 | #size-cells = <0>; | |
519 | compatible = "renesas,i2c-r8a774b1", | |
520 | "renesas,rcar-gen3-i2c"; | |
521 | reg = <0 0xe6510000 0 0x40>; | |
522 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; | |
523 | clocks = <&cpg CPG_MOD 929>; | |
524 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
525 | resets = <&cpg 929>; | |
526 | dmas = <&dmac1 0x95>, <&dmac1 0x94>, | |
527 | <&dmac2 0x95>, <&dmac2 0x94>; | |
528 | dma-names = "tx", "rx", "tx", "rx"; | |
529 | i2c-scl-internal-delay-ns = <6>; | |
530 | status = "disabled"; | |
531 | }; | |
532 | ||
533 | i2c3: i2c@e66d0000 { | |
534 | #address-cells = <1>; | |
535 | #size-cells = <0>; | |
536 | compatible = "renesas,i2c-r8a774b1", | |
537 | "renesas,rcar-gen3-i2c"; | |
538 | reg = <0 0xe66d0000 0 0x40>; | |
539 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; | |
540 | clocks = <&cpg CPG_MOD 928>; | |
541 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
542 | resets = <&cpg 928>; | |
543 | dmas = <&dmac0 0x97>, <&dmac0 0x96>; | |
544 | dma-names = "tx", "rx"; | |
545 | i2c-scl-internal-delay-ns = <110>; | |
546 | status = "disabled"; | |
547 | }; | |
548 | ||
9b33e300 BD |
549 | i2c4: i2c@e66d8000 { |
550 | #address-cells = <1>; | |
551 | #size-cells = <0>; | |
070302d4 BD |
552 | compatible = "renesas,i2c-r8a774b1", |
553 | "renesas,rcar-gen3-i2c"; | |
9b33e300 | 554 | reg = <0 0xe66d8000 0 0x40>; |
070302d4 BD |
555 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
556 | clocks = <&cpg CPG_MOD 927>; | |
557 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
558 | resets = <&cpg 927>; | |
559 | dmas = <&dmac0 0x99>, <&dmac0 0x98>; | |
560 | dma-names = "tx", "rx"; | |
561 | i2c-scl-internal-delay-ns = <110>; | |
562 | status = "disabled"; | |
563 | }; | |
564 | ||
565 | i2c5: i2c@e66e0000 { | |
566 | #address-cells = <1>; | |
567 | #size-cells = <0>; | |
568 | compatible = "renesas,i2c-r8a774b1", | |
569 | "renesas,rcar-gen3-i2c"; | |
570 | reg = <0 0xe66e0000 0 0x40>; | |
571 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
572 | clocks = <&cpg CPG_MOD 919>; | |
573 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
574 | resets = <&cpg 919>; | |
575 | dmas = <&dmac0 0x9b>, <&dmac0 0x9a>; | |
576 | dma-names = "tx", "rx"; | |
577 | i2c-scl-internal-delay-ns = <110>; | |
578 | status = "disabled"; | |
579 | }; | |
580 | ||
581 | i2c6: i2c@e66e8000 { | |
582 | #address-cells = <1>; | |
583 | #size-cells = <0>; | |
584 | compatible = "renesas,i2c-r8a774b1", | |
585 | "renesas,rcar-gen3-i2c"; | |
586 | reg = <0 0xe66e8000 0 0x40>; | |
587 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
588 | clocks = <&cpg CPG_MOD 918>; | |
589 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
590 | resets = <&cpg 918>; | |
591 | dmas = <&dmac0 0x9d>, <&dmac0 0x9c>; | |
592 | dma-names = "tx", "rx"; | |
593 | i2c-scl-internal-delay-ns = <6>; | |
594 | status = "disabled"; | |
595 | }; | |
596 | ||
a636d803 | 597 | iic_pmic: i2c@e60b0000 { |
070302d4 BD |
598 | #address-cells = <1>; |
599 | #size-cells = <0>; | |
600 | compatible = "renesas,iic-r8a774b1", | |
601 | "renesas,rcar-gen3-iic", | |
602 | "renesas,rmobile-iic"; | |
603 | reg = <0 0xe60b0000 0 0x425>; | |
604 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; | |
605 | clocks = <&cpg CPG_MOD 926>; | |
606 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
607 | resets = <&cpg 926>; | |
608 | dmas = <&dmac0 0x11>, <&dmac0 0x10>; | |
609 | dma-names = "tx", "rx"; | |
610 | status = "disabled"; | |
9b33e300 BD |
611 | }; |
612 | ||
613 | hscif0: serial@e6540000 { | |
83e7620a BD |
614 | compatible = "renesas,hscif-r8a774b1", |
615 | "renesas,rcar-gen3-hscif", | |
616 | "renesas,hscif"; | |
9b33e300 | 617 | reg = <0 0xe6540000 0 0x60>; |
83e7620a BD |
618 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
619 | clocks = <&cpg CPG_MOD 520>, | |
620 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
621 | <&scif_clk>; | |
622 | clock-names = "fck", "brg_int", "scif_clk"; | |
623 | dmas = <&dmac1 0x31>, <&dmac1 0x30>, | |
624 | <&dmac2 0x31>, <&dmac2 0x30>; | |
625 | dma-names = "tx", "rx", "tx", "rx"; | |
626 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
627 | resets = <&cpg 520>; | |
628 | status = "disabled"; | |
629 | }; | |
630 | ||
631 | hscif1: serial@e6550000 { | |
632 | compatible = "renesas,hscif-r8a774b1", | |
633 | "renesas,rcar-gen3-hscif", | |
634 | "renesas,hscif"; | |
635 | reg = <0 0xe6550000 0 0x60>; | |
636 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; | |
637 | clocks = <&cpg CPG_MOD 519>, | |
638 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
639 | <&scif_clk>; | |
640 | clock-names = "fck", "brg_int", "scif_clk"; | |
641 | dmas = <&dmac1 0x33>, <&dmac1 0x32>, | |
642 | <&dmac2 0x33>, <&dmac2 0x32>; | |
643 | dma-names = "tx", "rx", "tx", "rx"; | |
644 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
645 | resets = <&cpg 519>; | |
646 | status = "disabled"; | |
647 | }; | |
648 | ||
649 | hscif2: serial@e6560000 { | |
650 | compatible = "renesas,hscif-r8a774b1", | |
651 | "renesas,rcar-gen3-hscif", | |
652 | "renesas,hscif"; | |
653 | reg = <0 0xe6560000 0 0x60>; | |
654 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; | |
655 | clocks = <&cpg CPG_MOD 518>, | |
656 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
657 | <&scif_clk>; | |
658 | clock-names = "fck", "brg_int", "scif_clk"; | |
659 | dmas = <&dmac1 0x35>, <&dmac1 0x34>, | |
660 | <&dmac2 0x35>, <&dmac2 0x34>; | |
661 | dma-names = "tx", "rx", "tx", "rx"; | |
662 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
663 | resets = <&cpg 518>; | |
664 | status = "disabled"; | |
665 | }; | |
666 | ||
667 | hscif3: serial@e66a0000 { | |
668 | compatible = "renesas,hscif-r8a774b1", | |
669 | "renesas,rcar-gen3-hscif", | |
670 | "renesas,hscif"; | |
671 | reg = <0 0xe66a0000 0 0x60>; | |
672 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; | |
673 | clocks = <&cpg CPG_MOD 517>, | |
674 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
675 | <&scif_clk>; | |
676 | clock-names = "fck", "brg_int", "scif_clk"; | |
677 | dmas = <&dmac0 0x37>, <&dmac0 0x36>; | |
678 | dma-names = "tx", "rx"; | |
679 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
680 | resets = <&cpg 517>; | |
681 | status = "disabled"; | |
682 | }; | |
683 | ||
684 | hscif4: serial@e66b0000 { | |
685 | compatible = "renesas,hscif-r8a774b1", | |
686 | "renesas,rcar-gen3-hscif", | |
687 | "renesas,hscif"; | |
688 | reg = <0 0xe66b0000 0 0x60>; | |
689 | interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; | |
690 | clocks = <&cpg CPG_MOD 516>, | |
691 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
692 | <&scif_clk>; | |
693 | clock-names = "fck", "brg_int", "scif_clk"; | |
694 | dmas = <&dmac0 0x39>, <&dmac0 0x38>; | |
695 | dma-names = "tx", "rx"; | |
696 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
697 | resets = <&cpg 516>; | |
698 | status = "disabled"; | |
9b33e300 BD |
699 | }; |
700 | ||
701 | hsusb: usb@e6590000 { | |
34560ef3 FC |
702 | compatible = "renesas,usbhs-r8a774b1", |
703 | "renesas,rcar-gen3-usbhs"; | |
9b33e300 | 704 | reg = <0 0xe6590000 0 0x200>; |
34560ef3 FC |
705 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; |
706 | clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>; | |
707 | dmas = <&usb_dmac0 0>, <&usb_dmac0 1>, | |
708 | <&usb_dmac1 0>, <&usb_dmac1 1>; | |
709 | dma-names = "ch0", "ch1", "ch2", "ch3"; | |
710 | renesas,buswait = <11>; | |
711 | phys = <&usb2_phy0 3>; | |
712 | phy-names = "usb"; | |
713 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
714 | resets = <&cpg 704>, <&cpg 703>; | |
715 | status = "disabled"; | |
716 | }; | |
717 | ||
e1076ce0 AF |
718 | usb2_clksel: clock-controller@e6590630 { |
719 | compatible = "renesas,r8a774b1-rcar-usb2-clock-sel", | |
720 | "renesas,rcar-gen3-usb2-clock-sel"; | |
721 | reg = <0 0xe6590630 0 0x02>; | |
722 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>, | |
723 | <&usb_extal_clk>, <&usb3s0_clk>; | |
724 | clock-names = "ehci_ohci", "hs-usb-if", | |
725 | "usb_extal", "usb_xtal"; | |
726 | #clock-cells = <0>; | |
727 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
728 | resets = <&cpg 703>, <&cpg 704>; | |
729 | reset-names = "ehci_ohci", "hs-usb-if"; | |
730 | status = "disabled"; | |
731 | }; | |
732 | ||
34560ef3 FC |
733 | usb_dmac0: dma-controller@e65a0000 { |
734 | compatible = "renesas,r8a774b1-usb-dmac", | |
735 | "renesas,usb-dmac"; | |
736 | reg = <0 0xe65a0000 0 0x100>; | |
0aab5b91 GU |
737 | interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, |
738 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
34560ef3 FC |
739 | interrupt-names = "ch0", "ch1"; |
740 | clocks = <&cpg CPG_MOD 330>; | |
741 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
742 | resets = <&cpg 330>; | |
743 | #dma-cells = <1>; | |
744 | dma-channels = <2>; | |
745 | }; | |
746 | ||
747 | usb_dmac1: dma-controller@e65b0000 { | |
748 | compatible = "renesas,r8a774b1-usb-dmac", | |
749 | "renesas,usb-dmac"; | |
750 | reg = <0 0xe65b0000 0 0x100>; | |
0aab5b91 GU |
751 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, |
752 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
34560ef3 FC |
753 | interrupt-names = "ch0", "ch1"; |
754 | clocks = <&cpg CPG_MOD 331>; | |
755 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
756 | resets = <&cpg 331>; | |
757 | #dma-cells = <1>; | |
758 | dma-channels = <2>; | |
9b33e300 BD |
759 | }; |
760 | ||
761 | usb3_phy0: usb-phy@e65ee000 { | |
4ec25b30 FC |
762 | compatible = "renesas,r8a774b1-usb3-phy", |
763 | "renesas,rcar-gen3-usb3-phy"; | |
9b33e300 | 764 | reg = <0 0xe65ee000 0 0x90>; |
4ec25b30 FC |
765 | clocks = <&cpg CPG_MOD 328>, <&usb3s0_clk>, |
766 | <&usb_extal_clk>; | |
767 | clock-names = "usb3-if", "usb3s_clk", "usb_extal"; | |
768 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
769 | resets = <&cpg 328>; | |
9b33e300 | 770 | #phy-cells = <0>; |
4ec25b30 | 771 | status = "disabled"; |
9b33e300 BD |
772 | }; |
773 | ||
fd863e58 BD |
774 | dmac0: dma-controller@e6700000 { |
775 | compatible = "renesas,dmac-r8a774b1", | |
776 | "renesas,rcar-dmac"; | |
777 | reg = <0 0xe6700000 0 0x10000>; | |
0aab5b91 GU |
778 | interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, |
779 | <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, | |
780 | <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, | |
781 | <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, | |
782 | <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, | |
783 | <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, | |
784 | <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, | |
785 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, | |
786 | <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, | |
787 | <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, | |
788 | <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>, | |
789 | <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, | |
790 | <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, | |
791 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, | |
792 | <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, | |
793 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, | |
794 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; | |
fd863e58 BD |
795 | interrupt-names = "error", |
796 | "ch0", "ch1", "ch2", "ch3", | |
797 | "ch4", "ch5", "ch6", "ch7", | |
798 | "ch8", "ch9", "ch10", "ch11", | |
799 | "ch12", "ch13", "ch14", "ch15"; | |
800 | clocks = <&cpg CPG_MOD 219>; | |
801 | clock-names = "fck"; | |
802 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
803 | resets = <&cpg 219>; | |
804 | #dma-cells = <1>; | |
805 | dma-channels = <16>; | |
c6558893 BD |
806 | iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, |
807 | <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, | |
808 | <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, | |
809 | <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, | |
810 | <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, | |
811 | <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, | |
812 | <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, | |
813 | <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; | |
fd863e58 BD |
814 | }; |
815 | ||
816 | dmac1: dma-controller@e7300000 { | |
817 | compatible = "renesas,dmac-r8a774b1", | |
818 | "renesas,rcar-dmac"; | |
819 | reg = <0 0xe7300000 0 0x10000>; | |
0aab5b91 GU |
820 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, |
821 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, | |
822 | <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, | |
823 | <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, | |
824 | <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, | |
825 | <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, | |
826 | <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, | |
827 | <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, | |
828 | <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, | |
829 | <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, | |
830 | <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, | |
831 | <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, | |
832 | <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, | |
833 | <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, | |
834 | <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, | |
835 | <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, | |
836 | <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; | |
fd863e58 BD |
837 | interrupt-names = "error", |
838 | "ch0", "ch1", "ch2", "ch3", | |
839 | "ch4", "ch5", "ch6", "ch7", | |
840 | "ch8", "ch9", "ch10", "ch11", | |
841 | "ch12", "ch13", "ch14", "ch15"; | |
842 | clocks = <&cpg CPG_MOD 218>; | |
843 | clock-names = "fck"; | |
844 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
845 | resets = <&cpg 218>; | |
846 | #dma-cells = <1>; | |
847 | dma-channels = <16>; | |
c6558893 BD |
848 | iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, |
849 | <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, | |
850 | <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, | |
851 | <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, | |
852 | <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, | |
853 | <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, | |
854 | <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, | |
855 | <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; | |
fd863e58 BD |
856 | }; |
857 | ||
858 | dmac2: dma-controller@e7310000 { | |
859 | compatible = "renesas,dmac-r8a774b1", | |
860 | "renesas,rcar-dmac"; | |
861 | reg = <0 0xe7310000 0 0x10000>; | |
0aab5b91 GU |
862 | interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, |
863 | <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, | |
864 | <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, | |
865 | <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, | |
866 | <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, | |
867 | <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, | |
868 | <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, | |
869 | <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, | |
870 | <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, | |
871 | <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, | |
872 | <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, | |
873 | <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, | |
874 | <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, | |
875 | <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, | |
876 | <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, | |
877 | <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, | |
878 | <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>; | |
fd863e58 BD |
879 | interrupt-names = "error", |
880 | "ch0", "ch1", "ch2", "ch3", | |
881 | "ch4", "ch5", "ch6", "ch7", | |
882 | "ch8", "ch9", "ch10", "ch11", | |
883 | "ch12", "ch13", "ch14", "ch15"; | |
884 | clocks = <&cpg CPG_MOD 217>; | |
885 | clock-names = "fck"; | |
886 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
887 | resets = <&cpg 217>; | |
888 | #dma-cells = <1>; | |
889 | dma-channels = <16>; | |
c6558893 BD |
890 | iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, |
891 | <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, | |
892 | <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, | |
893 | <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, | |
894 | <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, | |
895 | <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, | |
896 | <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, | |
897 | <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; | |
fd863e58 BD |
898 | }; |
899 | ||
cf8ae446 | 900 | ipmmu_ds0: iommu@e6740000 { |
63093a8e BD |
901 | compatible = "renesas,ipmmu-r8a774b1"; |
902 | reg = <0 0xe6740000 0 0x1000>; | |
903 | renesas,ipmmu-main = <&ipmmu_mm 0>; | |
904 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
905 | #iommu-cells = <1>; | |
906 | }; | |
907 | ||
cf8ae446 | 908 | ipmmu_ds1: iommu@e7740000 { |
63093a8e BD |
909 | compatible = "renesas,ipmmu-r8a774b1"; |
910 | reg = <0 0xe7740000 0 0x1000>; | |
911 | renesas,ipmmu-main = <&ipmmu_mm 1>; | |
912 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
913 | #iommu-cells = <1>; | |
914 | }; | |
915 | ||
cf8ae446 | 916 | ipmmu_hc: iommu@e6570000 { |
63093a8e BD |
917 | compatible = "renesas,ipmmu-r8a774b1"; |
918 | reg = <0 0xe6570000 0 0x1000>; | |
919 | renesas,ipmmu-main = <&ipmmu_mm 2>; | |
920 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
921 | #iommu-cells = <1>; | |
922 | }; | |
923 | ||
cf8ae446 | 924 | ipmmu_mm: iommu@e67b0000 { |
63093a8e BD |
925 | compatible = "renesas,ipmmu-r8a774b1"; |
926 | reg = <0 0xe67b0000 0 0x1000>; | |
927 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, | |
928 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; | |
929 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
930 | #iommu-cells = <1>; | |
931 | }; | |
932 | ||
cf8ae446 | 933 | ipmmu_mp: iommu@ec670000 { |
63093a8e BD |
934 | compatible = "renesas,ipmmu-r8a774b1"; |
935 | reg = <0 0xec670000 0 0x1000>; | |
936 | renesas,ipmmu-main = <&ipmmu_mm 4>; | |
937 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
938 | #iommu-cells = <1>; | |
939 | }; | |
940 | ||
cf8ae446 | 941 | ipmmu_pv0: iommu@fd800000 { |
63093a8e BD |
942 | compatible = "renesas,ipmmu-r8a774b1"; |
943 | reg = <0 0xfd800000 0 0x1000>; | |
944 | renesas,ipmmu-main = <&ipmmu_mm 6>; | |
945 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
946 | #iommu-cells = <1>; | |
947 | }; | |
948 | ||
cf8ae446 | 949 | ipmmu_vc0: iommu@fe6b0000 { |
63093a8e BD |
950 | compatible = "renesas,ipmmu-r8a774b1"; |
951 | reg = <0 0xfe6b0000 0 0x1000>; | |
952 | renesas,ipmmu-main = <&ipmmu_mm 12>; | |
953 | power-domains = <&sysc R8A774B1_PD_A3VC>; | |
954 | #iommu-cells = <1>; | |
955 | }; | |
956 | ||
cf8ae446 | 957 | ipmmu_vi0: iommu@febd0000 { |
63093a8e BD |
958 | compatible = "renesas,ipmmu-r8a774b1"; |
959 | reg = <0 0xfebd0000 0 0x1000>; | |
960 | renesas,ipmmu-main = <&ipmmu_mm 14>; | |
961 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
962 | #iommu-cells = <1>; | |
963 | }; | |
964 | ||
cf8ae446 | 965 | ipmmu_vp0: iommu@fe990000 { |
63093a8e BD |
966 | compatible = "renesas,ipmmu-r8a774b1"; |
967 | reg = <0 0xfe990000 0 0x1000>; | |
968 | renesas,ipmmu-main = <&ipmmu_mm 16>; | |
969 | power-domains = <&sysc R8A774B1_PD_A3VP>; | |
970 | #iommu-cells = <1>; | |
971 | }; | |
972 | ||
9b33e300 | 973 | avb: ethernet@e6800000 { |
c722d900 BD |
974 | compatible = "renesas,etheravb-r8a774b1", |
975 | "renesas,etheravb-rcar-gen3"; | |
9b33e300 | 976 | reg = <0 0xe6800000 0 0x800>; |
c722d900 BD |
977 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, |
978 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
979 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
980 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
981 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
982 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
983 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
984 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
985 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
986 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
987 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
988 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
989 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
990 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
991 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
992 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
993 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
994 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
995 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, | |
996 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, | |
997 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, | |
998 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, | |
999 | <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, | |
1000 | <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, | |
1001 | <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; | |
1002 | interrupt-names = "ch0", "ch1", "ch2", "ch3", | |
1003 | "ch4", "ch5", "ch6", "ch7", | |
1004 | "ch8", "ch9", "ch10", "ch11", | |
1005 | "ch12", "ch13", "ch14", "ch15", | |
1006 | "ch16", "ch17", "ch18", "ch19", | |
1007 | "ch20", "ch21", "ch22", "ch23", | |
1008 | "ch24"; | |
1009 | clocks = <&cpg CPG_MOD 812>; | |
56ed0b3b | 1010 | clock-names = "fck"; |
c722d900 BD |
1011 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
1012 | resets = <&cpg 812>; | |
1013 | phy-mode = "rgmii"; | |
a5200e63 GU |
1014 | rx-internal-delay-ps = <0>; |
1015 | tx-internal-delay-ps = <0>; | |
79718f9d | 1016 | iommus = <&ipmmu_ds0 16>; |
c722d900 BD |
1017 | #address-cells = <1>; |
1018 | #size-cells = <0>; | |
1019 | status = "disabled"; | |
9b33e300 BD |
1020 | }; |
1021 | ||
1022 | can0: can@e6c30000 { | |
3fa08cbb FC |
1023 | compatible = "renesas,can-r8a774b1", |
1024 | "renesas,rcar-gen3-can"; | |
9b33e300 | 1025 | reg = <0 0xe6c30000 0 0x1000>; |
3fa08cbb FC |
1026 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
1027 | clocks = <&cpg CPG_MOD 916>, | |
1028 | <&cpg CPG_CORE R8A774B1_CLK_CANFD>, | |
1029 | <&can_clk>; | |
1030 | clock-names = "clkp1", "clkp2", "can_clk"; | |
1031 | assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; | |
1032 | assigned-clock-rates = <40000000>; | |
1033 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1034 | resets = <&cpg 916>; | |
1035 | status = "disabled"; | |
9b33e300 BD |
1036 | }; |
1037 | ||
1038 | can1: can@e6c38000 { | |
3fa08cbb FC |
1039 | compatible = "renesas,can-r8a774b1", |
1040 | "renesas,rcar-gen3-can"; | |
9b33e300 | 1041 | reg = <0 0xe6c38000 0 0x1000>; |
3fa08cbb FC |
1042 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
1043 | clocks = <&cpg CPG_MOD 915>, | |
1044 | <&cpg CPG_CORE R8A774B1_CLK_CANFD>, | |
1045 | <&can_clk>; | |
1046 | clock-names = "clkp1", "clkp2", "can_clk"; | |
1047 | assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; | |
1048 | assigned-clock-rates = <40000000>; | |
1049 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1050 | resets = <&cpg 915>; | |
1051 | status = "disabled"; | |
9b33e300 BD |
1052 | }; |
1053 | ||
1054 | canfd: can@e66c0000 { | |
3fa08cbb FC |
1055 | compatible = "renesas,r8a774b1-canfd", |
1056 | "renesas,rcar-gen3-canfd"; | |
9b33e300 | 1057 | reg = <0 0xe66c0000 0 0x8000>; |
3fa08cbb FC |
1058 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, |
1059 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
6af663af | 1060 | interrupt-names = "ch_int", "g_int"; |
3fa08cbb FC |
1061 | clocks = <&cpg CPG_MOD 914>, |
1062 | <&cpg CPG_CORE R8A774B1_CLK_CANFD>, | |
1063 | <&can_clk>; | |
1064 | clock-names = "fck", "canfd", "can_clk"; | |
1065 | assigned-clocks = <&cpg CPG_CORE R8A774B1_CLK_CANFD>; | |
1066 | assigned-clock-rates = <40000000>; | |
1067 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1068 | resets = <&cpg 914>; | |
1069 | status = "disabled"; | |
1070 | ||
1071 | channel0 { | |
1072 | status = "disabled"; | |
1073 | }; | |
1074 | ||
1075 | channel1 { | |
1076 | status = "disabled"; | |
1077 | }; | |
9b33e300 BD |
1078 | }; |
1079 | ||
68f62751 BD |
1080 | pwm0: pwm@e6e30000 { |
1081 | compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; | |
1082 | reg = <0 0xe6e30000 0 0x8>; | |
1083 | #pwm-cells = <2>; | |
1084 | clocks = <&cpg CPG_MOD 523>; | |
1085 | resets = <&cpg 523>; | |
1086 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1087 | status = "disabled"; | |
1088 | }; | |
1089 | ||
1090 | pwm1: pwm@e6e31000 { | |
1091 | compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; | |
1092 | reg = <0 0xe6e31000 0 0x8>; | |
1093 | #pwm-cells = <2>; | |
1094 | clocks = <&cpg CPG_MOD 523>; | |
1095 | resets = <&cpg 523>; | |
1096 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1097 | status = "disabled"; | |
1098 | }; | |
1099 | ||
1100 | pwm2: pwm@e6e32000 { | |
1101 | compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; | |
1102 | reg = <0 0xe6e32000 0 0x8>; | |
1103 | #pwm-cells = <2>; | |
1104 | clocks = <&cpg CPG_MOD 523>; | |
1105 | resets = <&cpg 523>; | |
1106 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1107 | status = "disabled"; | |
1108 | }; | |
1109 | ||
1110 | pwm3: pwm@e6e33000 { | |
1111 | compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; | |
1112 | reg = <0 0xe6e33000 0 0x8>; | |
1113 | #pwm-cells = <2>; | |
1114 | clocks = <&cpg CPG_MOD 523>; | |
1115 | resets = <&cpg 523>; | |
1116 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1117 | status = "disabled"; | |
1118 | }; | |
1119 | ||
1120 | pwm4: pwm@e6e34000 { | |
1121 | compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; | |
1122 | reg = <0 0xe6e34000 0 0x8>; | |
1123 | #pwm-cells = <2>; | |
1124 | clocks = <&cpg CPG_MOD 523>; | |
1125 | resets = <&cpg 523>; | |
1126 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1127 | status = "disabled"; | |
1128 | }; | |
1129 | ||
1130 | pwm5: pwm@e6e35000 { | |
1131 | compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; | |
1132 | reg = <0 0xe6e35000 0 0x8>; | |
1133 | #pwm-cells = <2>; | |
1134 | clocks = <&cpg CPG_MOD 523>; | |
1135 | resets = <&cpg 523>; | |
1136 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1137 | status = "disabled"; | |
1138 | }; | |
1139 | ||
1140 | pwm6: pwm@e6e36000 { | |
1141 | compatible = "renesas,pwm-r8a774b1", "renesas,pwm-rcar"; | |
1142 | reg = <0 0xe6e36000 0 0x8>; | |
1143 | #pwm-cells = <2>; | |
1144 | clocks = <&cpg CPG_MOD 523>; | |
1145 | resets = <&cpg 523>; | |
1146 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1147 | status = "disabled"; | |
1148 | }; | |
1149 | ||
83e7620a BD |
1150 | scif0: serial@e6e60000 { |
1151 | compatible = "renesas,scif-r8a774b1", | |
1152 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1153 | reg = <0 0xe6e60000 0 0x40>; | |
1154 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; | |
1155 | clocks = <&cpg CPG_MOD 207>, | |
1156 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
1157 | <&scif_clk>; | |
1158 | clock-names = "fck", "brg_int", "scif_clk"; | |
1159 | dmas = <&dmac1 0x51>, <&dmac1 0x50>, | |
1160 | <&dmac2 0x51>, <&dmac2 0x50>; | |
1161 | dma-names = "tx", "rx", "tx", "rx"; | |
1162 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1163 | resets = <&cpg 207>; | |
1164 | status = "disabled"; | |
1165 | }; | |
1166 | ||
1167 | scif1: serial@e6e68000 { | |
1168 | compatible = "renesas,scif-r8a774b1", | |
1169 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1170 | reg = <0 0xe6e68000 0 0x40>; | |
1171 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; | |
1172 | clocks = <&cpg CPG_MOD 206>, | |
1173 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
1174 | <&scif_clk>; | |
1175 | clock-names = "fck", "brg_int", "scif_clk"; | |
1176 | dmas = <&dmac1 0x53>, <&dmac1 0x52>, | |
1177 | <&dmac2 0x53>, <&dmac2 0x52>; | |
1178 | dma-names = "tx", "rx", "tx", "rx"; | |
1179 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1180 | resets = <&cpg 206>; | |
1181 | status = "disabled"; | |
1182 | }; | |
1183 | ||
9b33e300 BD |
1184 | scif2: serial@e6e88000 { |
1185 | compatible = "renesas,scif-r8a774b1", | |
1186 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
83e7620a | 1187 | reg = <0 0xe6e88000 0 0x40>; |
9b33e300 BD |
1188 | interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; |
1189 | clocks = <&cpg CPG_MOD 310>, | |
1190 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
1191 | <&scif_clk>; | |
1192 | clock-names = "fck", "brg_int", "scif_clk"; | |
83e7620a BD |
1193 | dmas = <&dmac1 0x13>, <&dmac1 0x12>, |
1194 | <&dmac2 0x13>, <&dmac2 0x12>; | |
1195 | dma-names = "tx", "rx", "tx", "rx"; | |
9b33e300 BD |
1196 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
1197 | resets = <&cpg 310>; | |
1198 | status = "disabled"; | |
1199 | }; | |
1200 | ||
83e7620a BD |
1201 | scif3: serial@e6c50000 { |
1202 | compatible = "renesas,scif-r8a774b1", | |
1203 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1204 | reg = <0 0xe6c50000 0 0x40>; | |
1205 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
1206 | clocks = <&cpg CPG_MOD 204>, | |
1207 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
1208 | <&scif_clk>; | |
1209 | clock-names = "fck", "brg_int", "scif_clk"; | |
1210 | dmas = <&dmac0 0x57>, <&dmac0 0x56>; | |
1211 | dma-names = "tx", "rx"; | |
1212 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1213 | resets = <&cpg 204>; | |
1214 | status = "disabled"; | |
1215 | }; | |
1216 | ||
1217 | scif4: serial@e6c40000 { | |
1218 | compatible = "renesas,scif-r8a774b1", | |
1219 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1220 | reg = <0 0xe6c40000 0 0x40>; | |
1221 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
1222 | clocks = <&cpg CPG_MOD 203>, | |
1223 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
1224 | <&scif_clk>; | |
1225 | clock-names = "fck", "brg_int", "scif_clk"; | |
1226 | dmas = <&dmac0 0x59>, <&dmac0 0x58>; | |
1227 | dma-names = "tx", "rx"; | |
1228 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1229 | resets = <&cpg 203>; | |
1230 | status = "disabled"; | |
1231 | }; | |
1232 | ||
1233 | scif5: serial@e6f30000 { | |
1234 | compatible = "renesas,scif-r8a774b1", | |
1235 | "renesas,rcar-gen3-scif", "renesas,scif"; | |
1236 | reg = <0 0xe6f30000 0 0x40>; | |
1237 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
1238 | clocks = <&cpg CPG_MOD 202>, | |
1239 | <&cpg CPG_CORE R8A774B1_CLK_S3D1>, | |
1240 | <&scif_clk>; | |
1241 | clock-names = "fck", "brg_int", "scif_clk"; | |
1242 | dmas = <&dmac1 0x5b>, <&dmac1 0x5a>, | |
1243 | <&dmac2 0x5b>, <&dmac2 0x5a>; | |
1244 | dma-names = "tx", "rx", "tx", "rx"; | |
1245 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1246 | resets = <&cpg 202>; | |
1247 | status = "disabled"; | |
1248 | }; | |
1249 | ||
c88657c4 FC |
1250 | msiof0: spi@e6e90000 { |
1251 | compatible = "renesas,msiof-r8a774b1", | |
1252 | "renesas,rcar-gen3-msiof"; | |
1253 | reg = <0 0xe6e90000 0 0x0064>; | |
1254 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; | |
1255 | clocks = <&cpg CPG_MOD 211>; | |
1256 | dmas = <&dmac1 0x41>, <&dmac1 0x40>, | |
1257 | <&dmac2 0x41>, <&dmac2 0x40>; | |
1258 | dma-names = "tx", "rx", "tx", "rx"; | |
1259 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1260 | resets = <&cpg 211>; | |
1261 | #address-cells = <1>; | |
1262 | #size-cells = <0>; | |
1263 | status = "disabled"; | |
1264 | }; | |
1265 | ||
1266 | msiof1: spi@e6ea0000 { | |
1267 | compatible = "renesas,msiof-r8a774b1", | |
1268 | "renesas,rcar-gen3-msiof"; | |
1269 | reg = <0 0xe6ea0000 0 0x0064>; | |
1270 | interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; | |
1271 | clocks = <&cpg CPG_MOD 210>; | |
1272 | dmas = <&dmac1 0x43>, <&dmac1 0x42>, | |
1273 | <&dmac2 0x43>, <&dmac2 0x42>; | |
1274 | dma-names = "tx", "rx", "tx", "rx"; | |
1275 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1276 | resets = <&cpg 210>; | |
1277 | #address-cells = <1>; | |
1278 | #size-cells = <0>; | |
1279 | status = "disabled"; | |
1280 | }; | |
1281 | ||
1282 | msiof2: spi@e6c00000 { | |
1283 | compatible = "renesas,msiof-r8a774b1", | |
1284 | "renesas,rcar-gen3-msiof"; | |
1285 | reg = <0 0xe6c00000 0 0x0064>; | |
1286 | interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; | |
1287 | clocks = <&cpg CPG_MOD 209>; | |
1288 | dmas = <&dmac0 0x45>, <&dmac0 0x44>; | |
1289 | dma-names = "tx", "rx"; | |
1290 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1291 | resets = <&cpg 209>; | |
1292 | #address-cells = <1>; | |
1293 | #size-cells = <0>; | |
1294 | status = "disabled"; | |
1295 | }; | |
1296 | ||
1297 | msiof3: spi@e6c10000 { | |
1298 | compatible = "renesas,msiof-r8a774b1", | |
1299 | "renesas,rcar-gen3-msiof"; | |
1300 | reg = <0 0xe6c10000 0 0x0064>; | |
1301 | interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; | |
1302 | clocks = <&cpg CPG_MOD 208>; | |
1303 | dmas = <&dmac0 0x47>, <&dmac0 0x46>; | |
1304 | dma-names = "tx", "rx"; | |
1305 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1306 | resets = <&cpg 208>; | |
1307 | #address-cells = <1>; | |
1308 | #size-cells = <0>; | |
1309 | status = "disabled"; | |
1310 | }; | |
1311 | ||
bf216639 BD |
1312 | vin0: video@e6ef0000 { |
1313 | compatible = "renesas,vin-r8a774b1"; | |
1314 | reg = <0 0xe6ef0000 0 0x1000>; | |
1315 | interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; | |
1316 | clocks = <&cpg CPG_MOD 811>; | |
1317 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1318 | resets = <&cpg 811>; | |
1319 | renesas,id = <0>; | |
1320 | status = "disabled"; | |
1321 | ||
1322 | ports { | |
1323 | #address-cells = <1>; | |
1324 | #size-cells = <0>; | |
1325 | ||
1326 | port@1 { | |
1327 | #address-cells = <1>; | |
1328 | #size-cells = <0>; | |
1329 | ||
1330 | reg = <1>; | |
1331 | ||
1332 | vin0csi20: endpoint@0 { | |
1333 | reg = <0>; | |
1334 | remote-endpoint = <&csi20vin0>; | |
1335 | }; | |
1336 | vin0csi40: endpoint@2 { | |
1337 | reg = <2>; | |
1338 | remote-endpoint = <&csi40vin0>; | |
1339 | }; | |
1340 | }; | |
1341 | }; | |
1342 | }; | |
1343 | ||
1344 | vin1: video@e6ef1000 { | |
1345 | compatible = "renesas,vin-r8a774b1"; | |
1346 | reg = <0 0xe6ef1000 0 0x1000>; | |
1347 | interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; | |
1348 | clocks = <&cpg CPG_MOD 810>; | |
1349 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1350 | resets = <&cpg 810>; | |
1351 | renesas,id = <1>; | |
1352 | status = "disabled"; | |
1353 | ||
1354 | ports { | |
1355 | #address-cells = <1>; | |
1356 | #size-cells = <0>; | |
1357 | ||
1358 | port@1 { | |
1359 | #address-cells = <1>; | |
1360 | #size-cells = <0>; | |
1361 | ||
1362 | reg = <1>; | |
1363 | ||
1364 | vin1csi20: endpoint@0 { | |
1365 | reg = <0>; | |
1366 | remote-endpoint = <&csi20vin1>; | |
1367 | }; | |
1368 | vin1csi40: endpoint@2 { | |
1369 | reg = <2>; | |
1370 | remote-endpoint = <&csi40vin1>; | |
1371 | }; | |
1372 | }; | |
1373 | }; | |
1374 | }; | |
1375 | ||
1376 | vin2: video@e6ef2000 { | |
1377 | compatible = "renesas,vin-r8a774b1"; | |
1378 | reg = <0 0xe6ef2000 0 0x1000>; | |
1379 | interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | |
1380 | clocks = <&cpg CPG_MOD 809>; | |
1381 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1382 | resets = <&cpg 809>; | |
1383 | renesas,id = <2>; | |
1384 | status = "disabled"; | |
1385 | ||
1386 | ports { | |
1387 | #address-cells = <1>; | |
1388 | #size-cells = <0>; | |
1389 | ||
1390 | port@1 { | |
1391 | #address-cells = <1>; | |
1392 | #size-cells = <0>; | |
1393 | ||
1394 | reg = <1>; | |
1395 | ||
1396 | vin2csi20: endpoint@0 { | |
1397 | reg = <0>; | |
1398 | remote-endpoint = <&csi20vin2>; | |
1399 | }; | |
1400 | vin2csi40: endpoint@2 { | |
1401 | reg = <2>; | |
1402 | remote-endpoint = <&csi40vin2>; | |
1403 | }; | |
1404 | }; | |
1405 | }; | |
1406 | }; | |
1407 | ||
1408 | vin3: video@e6ef3000 { | |
1409 | compatible = "renesas,vin-r8a774b1"; | |
1410 | reg = <0 0xe6ef3000 0 0x1000>; | |
1411 | interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; | |
1412 | clocks = <&cpg CPG_MOD 808>; | |
1413 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1414 | resets = <&cpg 808>; | |
1415 | renesas,id = <3>; | |
1416 | status = "disabled"; | |
1417 | ||
1418 | ports { | |
1419 | #address-cells = <1>; | |
1420 | #size-cells = <0>; | |
1421 | ||
1422 | port@1 { | |
1423 | #address-cells = <1>; | |
1424 | #size-cells = <0>; | |
1425 | ||
1426 | reg = <1>; | |
1427 | ||
1428 | vin3csi20: endpoint@0 { | |
1429 | reg = <0>; | |
1430 | remote-endpoint = <&csi20vin3>; | |
1431 | }; | |
1432 | vin3csi40: endpoint@2 { | |
1433 | reg = <2>; | |
1434 | remote-endpoint = <&csi40vin3>; | |
1435 | }; | |
1436 | }; | |
1437 | }; | |
1438 | }; | |
1439 | ||
1440 | vin4: video@e6ef4000 { | |
1441 | compatible = "renesas,vin-r8a774b1"; | |
1442 | reg = <0 0xe6ef4000 0 0x1000>; | |
1443 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; | |
1444 | clocks = <&cpg CPG_MOD 807>; | |
1445 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1446 | resets = <&cpg 807>; | |
1447 | renesas,id = <4>; | |
1448 | status = "disabled"; | |
1449 | ||
1450 | ports { | |
1451 | #address-cells = <1>; | |
1452 | #size-cells = <0>; | |
1453 | ||
1454 | port@1 { | |
1455 | #address-cells = <1>; | |
1456 | #size-cells = <0>; | |
1457 | ||
1458 | reg = <1>; | |
1459 | ||
1460 | vin4csi20: endpoint@0 { | |
1461 | reg = <0>; | |
1462 | remote-endpoint = <&csi20vin4>; | |
1463 | }; | |
1464 | vin4csi40: endpoint@2 { | |
1465 | reg = <2>; | |
1466 | remote-endpoint = <&csi40vin4>; | |
1467 | }; | |
1468 | }; | |
1469 | }; | |
1470 | }; | |
1471 | ||
1472 | vin5: video@e6ef5000 { | |
1473 | compatible = "renesas,vin-r8a774b1"; | |
1474 | reg = <0 0xe6ef5000 0 0x1000>; | |
1475 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; | |
1476 | clocks = <&cpg CPG_MOD 806>; | |
1477 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1478 | resets = <&cpg 806>; | |
1479 | renesas,id = <5>; | |
1480 | status = "disabled"; | |
1481 | ||
1482 | ports { | |
1483 | #address-cells = <1>; | |
1484 | #size-cells = <0>; | |
1485 | ||
1486 | port@1 { | |
1487 | #address-cells = <1>; | |
1488 | #size-cells = <0>; | |
1489 | ||
1490 | reg = <1>; | |
1491 | ||
1492 | vin5csi20: endpoint@0 { | |
1493 | reg = <0>; | |
1494 | remote-endpoint = <&csi20vin5>; | |
1495 | }; | |
1496 | vin5csi40: endpoint@2 { | |
1497 | reg = <2>; | |
1498 | remote-endpoint = <&csi40vin5>; | |
1499 | }; | |
1500 | }; | |
1501 | }; | |
1502 | }; | |
1503 | ||
1504 | vin6: video@e6ef6000 { | |
1505 | compatible = "renesas,vin-r8a774b1"; | |
1506 | reg = <0 0xe6ef6000 0 0x1000>; | |
1507 | interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; | |
1508 | clocks = <&cpg CPG_MOD 805>; | |
1509 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1510 | resets = <&cpg 805>; | |
1511 | renesas,id = <6>; | |
1512 | status = "disabled"; | |
1513 | ||
1514 | ports { | |
1515 | #address-cells = <1>; | |
1516 | #size-cells = <0>; | |
1517 | ||
1518 | port@1 { | |
1519 | #address-cells = <1>; | |
1520 | #size-cells = <0>; | |
1521 | ||
1522 | reg = <1>; | |
1523 | ||
1524 | vin6csi20: endpoint@0 { | |
1525 | reg = <0>; | |
1526 | remote-endpoint = <&csi20vin6>; | |
1527 | }; | |
1528 | vin6csi40: endpoint@2 { | |
1529 | reg = <2>; | |
1530 | remote-endpoint = <&csi40vin6>; | |
1531 | }; | |
1532 | }; | |
1533 | }; | |
1534 | }; | |
1535 | ||
1536 | vin7: video@e6ef7000 { | |
1537 | compatible = "renesas,vin-r8a774b1"; | |
1538 | reg = <0 0xe6ef7000 0 0x1000>; | |
1539 | interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; | |
1540 | clocks = <&cpg CPG_MOD 804>; | |
1541 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1542 | resets = <&cpg 804>; | |
1543 | renesas,id = <7>; | |
1544 | status = "disabled"; | |
1545 | ||
1546 | ports { | |
1547 | #address-cells = <1>; | |
1548 | #size-cells = <0>; | |
1549 | ||
1550 | port@1 { | |
1551 | #address-cells = <1>; | |
1552 | #size-cells = <0>; | |
1553 | ||
1554 | reg = <1>; | |
1555 | ||
1556 | vin7csi20: endpoint@0 { | |
1557 | reg = <0>; | |
1558 | remote-endpoint = <&csi20vin7>; | |
1559 | }; | |
1560 | vin7csi40: endpoint@2 { | |
1561 | reg = <2>; | |
1562 | remote-endpoint = <&csi40vin7>; | |
1563 | }; | |
1564 | }; | |
1565 | }; | |
1566 | }; | |
1567 | ||
9b33e300 | 1568 | rcar_sound: sound@ec500000 { |
067eca6d | 1569 | /* |
9e72606c | 1570 | * #sound-dai-cells is required if simple-card |
067eca6d BD |
1571 | * |
1572 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
1573 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
1574 | */ | |
1575 | /* | |
1576 | * #clock-cells is required for audio_clkout0/1/2/3 | |
1577 | * | |
1578 | * clkout : #clock-cells = <0>; <&rcar_sound>; | |
1579 | * clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>; | |
1580 | */ | |
953b392a | 1581 | compatible = "renesas,rcar_sound-r8a774b1", "renesas,rcar_sound-gen3"; |
9b33e300 BD |
1582 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
1583 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
1584 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
1585 | <0 0xec541000 0 0x280>, /* SSI */ | |
1586 | <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/ | |
067eca6d BD |
1587 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; |
1588 | ||
1589 | clocks = <&cpg CPG_MOD 1005>, | |
1590 | <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>, | |
1591 | <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>, | |
1592 | <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>, | |
1593 | <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>, | |
1594 | <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>, | |
1595 | <&cpg CPG_MOD 1022>, <&cpg CPG_MOD 1023>, | |
1596 | <&cpg CPG_MOD 1024>, <&cpg CPG_MOD 1025>, | |
1597 | <&cpg CPG_MOD 1026>, <&cpg CPG_MOD 1027>, | |
1598 | <&cpg CPG_MOD 1028>, <&cpg CPG_MOD 1029>, | |
1599 | <&cpg CPG_MOD 1030>, <&cpg CPG_MOD 1031>, | |
1600 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
1601 | <&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>, | |
1602 | <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>, | |
1603 | <&audio_clk_a>, <&audio_clk_b>, | |
1604 | <&audio_clk_c>, | |
f2802c62 | 1605 | <&cpg CPG_MOD 922>; |
067eca6d BD |
1606 | clock-names = "ssi-all", |
1607 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
1608 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
1609 | "ssi.1", "ssi.0", | |
1610 | "src.9", "src.8", "src.7", "src.6", | |
1611 | "src.5", "src.4", "src.3", "src.2", | |
1612 | "src.1", "src.0", | |
1613 | "mix.1", "mix.0", | |
1614 | "ctu.1", "ctu.0", | |
1615 | "dvc.0", "dvc.1", | |
1616 | "clk_a", "clk_b", "clk_c", "clk_i"; | |
1617 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
1618 | resets = <&cpg 1005>, | |
1619 | <&cpg 1006>, <&cpg 1007>, | |
1620 | <&cpg 1008>, <&cpg 1009>, | |
1621 | <&cpg 1010>, <&cpg 1011>, | |
1622 | <&cpg 1012>, <&cpg 1013>, | |
1623 | <&cpg 1014>, <&cpg 1015>; | |
1624 | reset-names = "ssi-all", | |
1625 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", | |
1626 | "ssi.5", "ssi.4", "ssi.3", "ssi.2", | |
1627 | "ssi.1", "ssi.0"; | |
1628 | status = "disabled"; | |
1629 | ||
1630 | rcar_sound,ctu { | |
1631 | ctu00: ctu-0 { }; | |
1632 | ctu01: ctu-1 { }; | |
1633 | ctu02: ctu-2 { }; | |
1634 | ctu03: ctu-3 { }; | |
1635 | ctu10: ctu-4 { }; | |
1636 | ctu11: ctu-5 { }; | |
1637 | ctu12: ctu-6 { }; | |
1638 | ctu13: ctu-7 { }; | |
1639 | }; | |
1640 | ||
1641 | rcar_sound,dvc { | |
1642 | dvc0: dvc-0 { | |
1643 | dmas = <&audma1 0xbc>; | |
1644 | dma-names = "tx"; | |
1645 | }; | |
1646 | dvc1: dvc-1 { | |
1647 | dmas = <&audma1 0xbe>; | |
1648 | dma-names = "tx"; | |
1649 | }; | |
1650 | }; | |
1651 | ||
1652 | rcar_sound,mix { | |
1653 | mix0: mix-0 { }; | |
1654 | mix1: mix-1 { }; | |
1655 | }; | |
1656 | ||
1657 | rcar_sound,src { | |
1658 | src0: src-0 { | |
1659 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; | |
1660 | dmas = <&audma0 0x85>, <&audma1 0x9a>; | |
1661 | dma-names = "rx", "tx"; | |
1662 | }; | |
1663 | src1: src-1 { | |
1664 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; | |
1665 | dmas = <&audma0 0x87>, <&audma1 0x9c>; | |
1666 | dma-names = "rx", "tx"; | |
1667 | }; | |
1668 | src2: src-2 { | |
1669 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; | |
1670 | dmas = <&audma0 0x89>, <&audma1 0x9e>; | |
1671 | dma-names = "rx", "tx"; | |
1672 | }; | |
1673 | src3: src-3 { | |
1674 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; | |
1675 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; | |
1676 | dma-names = "rx", "tx"; | |
1677 | }; | |
1678 | src4: src-4 { | |
1679 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; | |
1680 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; | |
1681 | dma-names = "rx", "tx"; | |
1682 | }; | |
1683 | src5: src-5 { | |
1684 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; | |
1685 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; | |
1686 | dma-names = "rx", "tx"; | |
1687 | }; | |
1688 | src6: src-6 { | |
1689 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; | |
1690 | dmas = <&audma0 0x91>, <&audma1 0xb4>; | |
1691 | dma-names = "rx", "tx"; | |
1692 | }; | |
1693 | src7: src-7 { | |
1694 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; | |
1695 | dmas = <&audma0 0x93>, <&audma1 0xb6>; | |
1696 | dma-names = "rx", "tx"; | |
1697 | }; | |
1698 | src8: src-8 { | |
1699 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; | |
1700 | dmas = <&audma0 0x95>, <&audma1 0xb8>; | |
1701 | dma-names = "rx", "tx"; | |
1702 | }; | |
1703 | src9: src-9 { | |
1704 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; | |
1705 | dmas = <&audma0 0x97>, <&audma1 0xba>; | |
1706 | dma-names = "rx", "tx"; | |
1707 | }; | |
1708 | }; | |
9b33e300 BD |
1709 | |
1710 | rcar_sound,ssi { | |
067eca6d BD |
1711 | ssi0: ssi-0 { |
1712 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; | |
1713 | dmas = <&audma0 0x01>, <&audma1 0x02>; | |
1714 | dma-names = "rx", "tx"; | |
1715 | }; | |
1716 | ssi1: ssi-1 { | |
1717 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; | |
1718 | dmas = <&audma0 0x03>, <&audma1 0x04>; | |
1719 | dma-names = "rx", "tx"; | |
1720 | }; | |
1721 | ssi2: ssi-2 { | |
1722 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; | |
1723 | dmas = <&audma0 0x05>, <&audma1 0x06>; | |
1724 | dma-names = "rx", "tx"; | |
1725 | }; | |
1726 | ssi3: ssi-3 { | |
1727 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; | |
1728 | dmas = <&audma0 0x07>, <&audma1 0x08>; | |
1729 | dma-names = "rx", "tx"; | |
1730 | }; | |
1731 | ssi4: ssi-4 { | |
1732 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; | |
1733 | dmas = <&audma0 0x09>, <&audma1 0x0a>; | |
1734 | dma-names = "rx", "tx"; | |
1735 | }; | |
1736 | ssi5: ssi-5 { | |
1737 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; | |
1738 | dmas = <&audma0 0x0b>, <&audma1 0x0c>; | |
1739 | dma-names = "rx", "tx"; | |
1740 | }; | |
1741 | ssi6: ssi-6 { | |
1742 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; | |
1743 | dmas = <&audma0 0x0d>, <&audma1 0x0e>; | |
1744 | dma-names = "rx", "tx"; | |
1745 | }; | |
1746 | ssi7: ssi-7 { | |
1747 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; | |
1748 | dmas = <&audma0 0x0f>, <&audma1 0x10>; | |
1749 | dma-names = "rx", "tx"; | |
1750 | }; | |
1751 | ssi8: ssi-8 { | |
1752 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; | |
1753 | dmas = <&audma0 0x11>, <&audma1 0x12>; | |
1754 | dma-names = "rx", "tx"; | |
1755 | }; | |
1756 | ssi9: ssi-9 { | |
1757 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; | |
1758 | dmas = <&audma0 0x13>, <&audma1 0x14>; | |
1759 | dma-names = "rx", "tx"; | |
1760 | }; | |
9b33e300 | 1761 | }; |
067eca6d BD |
1762 | |
1763 | rcar_sound,ssiu { | |
1764 | ssiu00: ssiu-0 { | |
1765 | dmas = <&audma0 0x15>, <&audma1 0x16>; | |
1766 | dma-names = "rx", "tx"; | |
1767 | }; | |
1768 | ssiu01: ssiu-1 { | |
1769 | dmas = <&audma0 0x35>, <&audma1 0x36>; | |
1770 | dma-names = "rx", "tx"; | |
1771 | }; | |
1772 | ssiu02: ssiu-2 { | |
1773 | dmas = <&audma0 0x37>, <&audma1 0x38>; | |
1774 | dma-names = "rx", "tx"; | |
1775 | }; | |
1776 | ssiu03: ssiu-3 { | |
1777 | dmas = <&audma0 0x47>, <&audma1 0x48>; | |
1778 | dma-names = "rx", "tx"; | |
1779 | }; | |
1780 | ssiu04: ssiu-4 { | |
1781 | dmas = <&audma0 0x3F>, <&audma1 0x40>; | |
1782 | dma-names = "rx", "tx"; | |
1783 | }; | |
1784 | ssiu05: ssiu-5 { | |
1785 | dmas = <&audma0 0x43>, <&audma1 0x44>; | |
1786 | dma-names = "rx", "tx"; | |
1787 | }; | |
1788 | ssiu06: ssiu-6 { | |
1789 | dmas = <&audma0 0x4F>, <&audma1 0x50>; | |
1790 | dma-names = "rx", "tx"; | |
1791 | }; | |
1792 | ssiu07: ssiu-7 { | |
1793 | dmas = <&audma0 0x53>, <&audma1 0x54>; | |
1794 | dma-names = "rx", "tx"; | |
1795 | }; | |
1796 | ssiu10: ssiu-8 { | |
1797 | dmas = <&audma0 0x49>, <&audma1 0x4a>; | |
1798 | dma-names = "rx", "tx"; | |
1799 | }; | |
1800 | ssiu11: ssiu-9 { | |
1801 | dmas = <&audma0 0x4B>, <&audma1 0x4C>; | |
1802 | dma-names = "rx", "tx"; | |
1803 | }; | |
1804 | ssiu12: ssiu-10 { | |
1805 | dmas = <&audma0 0x57>, <&audma1 0x58>; | |
1806 | dma-names = "rx", "tx"; | |
1807 | }; | |
1808 | ssiu13: ssiu-11 { | |
1809 | dmas = <&audma0 0x59>, <&audma1 0x5A>; | |
1810 | dma-names = "rx", "tx"; | |
1811 | }; | |
1812 | ssiu14: ssiu-12 { | |
1813 | dmas = <&audma0 0x5F>, <&audma1 0x60>; | |
1814 | dma-names = "rx", "tx"; | |
1815 | }; | |
1816 | ssiu15: ssiu-13 { | |
1817 | dmas = <&audma0 0xC3>, <&audma1 0xC4>; | |
1818 | dma-names = "rx", "tx"; | |
1819 | }; | |
1820 | ssiu16: ssiu-14 { | |
1821 | dmas = <&audma0 0xC7>, <&audma1 0xC8>; | |
1822 | dma-names = "rx", "tx"; | |
1823 | }; | |
1824 | ssiu17: ssiu-15 { | |
1825 | dmas = <&audma0 0xCB>, <&audma1 0xCC>; | |
1826 | dma-names = "rx", "tx"; | |
1827 | }; | |
1828 | ssiu20: ssiu-16 { | |
1829 | dmas = <&audma0 0x63>, <&audma1 0x64>; | |
1830 | dma-names = "rx", "tx"; | |
1831 | }; | |
1832 | ssiu21: ssiu-17 { | |
1833 | dmas = <&audma0 0x67>, <&audma1 0x68>; | |
1834 | dma-names = "rx", "tx"; | |
1835 | }; | |
1836 | ssiu22: ssiu-18 { | |
1837 | dmas = <&audma0 0x6B>, <&audma1 0x6C>; | |
1838 | dma-names = "rx", "tx"; | |
1839 | }; | |
1840 | ssiu23: ssiu-19 { | |
1841 | dmas = <&audma0 0x6D>, <&audma1 0x6E>; | |
1842 | dma-names = "rx", "tx"; | |
1843 | }; | |
1844 | ssiu24: ssiu-20 { | |
1845 | dmas = <&audma0 0xCF>, <&audma1 0xCE>; | |
1846 | dma-names = "rx", "tx"; | |
1847 | }; | |
1848 | ssiu25: ssiu-21 { | |
1849 | dmas = <&audma0 0xEB>, <&audma1 0xEC>; | |
1850 | dma-names = "rx", "tx"; | |
1851 | }; | |
1852 | ssiu26: ssiu-22 { | |
1853 | dmas = <&audma0 0xED>, <&audma1 0xEE>; | |
1854 | dma-names = "rx", "tx"; | |
1855 | }; | |
1856 | ssiu27: ssiu-23 { | |
1857 | dmas = <&audma0 0xEF>, <&audma1 0xF0>; | |
1858 | dma-names = "rx", "tx"; | |
1859 | }; | |
1860 | ssiu30: ssiu-24 { | |
1861 | dmas = <&audma0 0x6f>, <&audma1 0x70>; | |
1862 | dma-names = "rx", "tx"; | |
1863 | }; | |
1864 | ssiu31: ssiu-25 { | |
1865 | dmas = <&audma0 0x21>, <&audma1 0x22>; | |
1866 | dma-names = "rx", "tx"; | |
1867 | }; | |
1868 | ssiu32: ssiu-26 { | |
1869 | dmas = <&audma0 0x23>, <&audma1 0x24>; | |
1870 | dma-names = "rx", "tx"; | |
1871 | }; | |
1872 | ssiu33: ssiu-27 { | |
1873 | dmas = <&audma0 0x25>, <&audma1 0x26>; | |
1874 | dma-names = "rx", "tx"; | |
1875 | }; | |
1876 | ssiu34: ssiu-28 { | |
1877 | dmas = <&audma0 0x27>, <&audma1 0x28>; | |
1878 | dma-names = "rx", "tx"; | |
1879 | }; | |
1880 | ssiu35: ssiu-29 { | |
1881 | dmas = <&audma0 0x29>, <&audma1 0x2A>; | |
1882 | dma-names = "rx", "tx"; | |
1883 | }; | |
1884 | ssiu36: ssiu-30 { | |
1885 | dmas = <&audma0 0x2B>, <&audma1 0x2C>; | |
1886 | dma-names = "rx", "tx"; | |
1887 | }; | |
1888 | ssiu37: ssiu-31 { | |
1889 | dmas = <&audma0 0x2D>, <&audma1 0x2E>; | |
1890 | dma-names = "rx", "tx"; | |
1891 | }; | |
1892 | ssiu40: ssiu-32 { | |
953b392a | 1893 | dmas = <&audma0 0x71>, <&audma1 0x72>; |
067eca6d BD |
1894 | dma-names = "rx", "tx"; |
1895 | }; | |
1896 | ssiu41: ssiu-33 { | |
1897 | dmas = <&audma0 0x17>, <&audma1 0x18>; | |
1898 | dma-names = "rx", "tx"; | |
1899 | }; | |
1900 | ssiu42: ssiu-34 { | |
1901 | dmas = <&audma0 0x19>, <&audma1 0x1A>; | |
1902 | dma-names = "rx", "tx"; | |
1903 | }; | |
1904 | ssiu43: ssiu-35 { | |
1905 | dmas = <&audma0 0x1B>, <&audma1 0x1C>; | |
1906 | dma-names = "rx", "tx"; | |
1907 | }; | |
1908 | ssiu44: ssiu-36 { | |
1909 | dmas = <&audma0 0x1D>, <&audma1 0x1E>; | |
1910 | dma-names = "rx", "tx"; | |
1911 | }; | |
1912 | ssiu45: ssiu-37 { | |
1913 | dmas = <&audma0 0x1F>, <&audma1 0x20>; | |
1914 | dma-names = "rx", "tx"; | |
1915 | }; | |
1916 | ssiu46: ssiu-38 { | |
1917 | dmas = <&audma0 0x31>, <&audma1 0x32>; | |
1918 | dma-names = "rx", "tx"; | |
1919 | }; | |
1920 | ssiu47: ssiu-39 { | |
1921 | dmas = <&audma0 0x33>, <&audma1 0x34>; | |
1922 | dma-names = "rx", "tx"; | |
1923 | }; | |
1924 | ssiu50: ssiu-40 { | |
1925 | dmas = <&audma0 0x73>, <&audma1 0x74>; | |
1926 | dma-names = "rx", "tx"; | |
1927 | }; | |
1928 | ssiu60: ssiu-41 { | |
1929 | dmas = <&audma0 0x75>, <&audma1 0x76>; | |
1930 | dma-names = "rx", "tx"; | |
1931 | }; | |
1932 | ssiu70: ssiu-42 { | |
1933 | dmas = <&audma0 0x79>, <&audma1 0x7a>; | |
1934 | dma-names = "rx", "tx"; | |
1935 | }; | |
1936 | ssiu80: ssiu-43 { | |
1937 | dmas = <&audma0 0x7b>, <&audma1 0x7c>; | |
1938 | dma-names = "rx", "tx"; | |
1939 | }; | |
1940 | ssiu90: ssiu-44 { | |
1941 | dmas = <&audma0 0x7d>, <&audma1 0x7e>; | |
1942 | dma-names = "rx", "tx"; | |
1943 | }; | |
1944 | ssiu91: ssiu-45 { | |
1945 | dmas = <&audma0 0x7F>, <&audma1 0x80>; | |
1946 | dma-names = "rx", "tx"; | |
1947 | }; | |
1948 | ssiu92: ssiu-46 { | |
1949 | dmas = <&audma0 0x81>, <&audma1 0x82>; | |
1950 | dma-names = "rx", "tx"; | |
1951 | }; | |
1952 | ssiu93: ssiu-47 { | |
1953 | dmas = <&audma0 0x83>, <&audma1 0x84>; | |
1954 | dma-names = "rx", "tx"; | |
1955 | }; | |
1956 | ssiu94: ssiu-48 { | |
1957 | dmas = <&audma0 0xA3>, <&audma1 0xA4>; | |
1958 | dma-names = "rx", "tx"; | |
1959 | }; | |
1960 | ssiu95: ssiu-49 { | |
1961 | dmas = <&audma0 0xA5>, <&audma1 0xA6>; | |
1962 | dma-names = "rx", "tx"; | |
1963 | }; | |
1964 | ssiu96: ssiu-50 { | |
1965 | dmas = <&audma0 0xA7>, <&audma1 0xA8>; | |
1966 | dma-names = "rx", "tx"; | |
1967 | }; | |
1968 | ssiu97: ssiu-51 { | |
1969 | dmas = <&audma0 0xA9>, <&audma1 0xAA>; | |
1970 | dma-names = "rx", "tx"; | |
1971 | }; | |
1972 | }; | |
1973 | }; | |
1974 | ||
1975 | audma0: dma-controller@ec700000 { | |
1976 | compatible = "renesas,dmac-r8a774b1", | |
1977 | "renesas,rcar-dmac"; | |
1978 | reg = <0 0xec700000 0 0x10000>; | |
0aab5b91 GU |
1979 | interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, |
1980 | <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, | |
1981 | <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, | |
1982 | <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, | |
1983 | <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, | |
1984 | <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, | |
1985 | <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, | |
1986 | <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, | |
1987 | <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, | |
1988 | <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, | |
1989 | <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, | |
1990 | <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, | |
1991 | <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, | |
1992 | <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, | |
1993 | <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, | |
1994 | <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, | |
1995 | <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>; | |
067eca6d BD |
1996 | interrupt-names = "error", |
1997 | "ch0", "ch1", "ch2", "ch3", | |
1998 | "ch4", "ch5", "ch6", "ch7", | |
1999 | "ch8", "ch9", "ch10", "ch11", | |
2000 | "ch12", "ch13", "ch14", "ch15"; | |
2001 | clocks = <&cpg CPG_MOD 502>; | |
2002 | clock-names = "fck"; | |
2003 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2004 | resets = <&cpg 502>; | |
2005 | #dma-cells = <1>; | |
2006 | dma-channels = <16>; | |
2007 | }; | |
2008 | ||
2009 | audma1: dma-controller@ec720000 { | |
2010 | compatible = "renesas,dmac-r8a774b1", | |
2011 | "renesas,rcar-dmac"; | |
2012 | reg = <0 0xec720000 0 0x10000>; | |
0aab5b91 GU |
2013 | interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, |
2014 | <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, | |
2015 | <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, | |
2016 | <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, | |
2017 | <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, | |
2018 | <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, | |
2019 | <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, | |
2020 | <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, | |
2021 | <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, | |
2022 | <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, | |
2023 | <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, | |
2024 | <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, | |
2025 | <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, | |
2026 | <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, | |
2027 | <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, | |
2028 | <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, | |
2029 | <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>; | |
067eca6d BD |
2030 | interrupt-names = "error", |
2031 | "ch0", "ch1", "ch2", "ch3", | |
2032 | "ch4", "ch5", "ch6", "ch7", | |
2033 | "ch8", "ch9", "ch10", "ch11", | |
2034 | "ch12", "ch13", "ch14", "ch15"; | |
2035 | clocks = <&cpg CPG_MOD 501>; | |
2036 | clock-names = "fck"; | |
2037 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2038 | resets = <&cpg 501>; | |
2039 | #dma-cells = <1>; | |
2040 | dma-channels = <16>; | |
9b33e300 BD |
2041 | }; |
2042 | ||
2043 | xhci0: usb@ee000000 { | |
4ec25b30 FC |
2044 | compatible = "renesas,xhci-r8a774b1", |
2045 | "renesas,rcar-gen3-xhci"; | |
9b33e300 | 2046 | reg = <0 0xee000000 0 0xc00>; |
4ec25b30 FC |
2047 | interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
2048 | clocks = <&cpg CPG_MOD 328>; | |
2049 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2050 | resets = <&cpg 328>; | |
2051 | status = "disabled"; | |
9b33e300 BD |
2052 | }; |
2053 | ||
2054 | usb3_peri0: usb@ee020000 { | |
4ec25b30 FC |
2055 | compatible = "renesas,r8a774b1-usb3-peri", |
2056 | "renesas,rcar-gen3-usb3-peri"; | |
9b33e300 | 2057 | reg = <0 0xee020000 0 0x400>; |
4ec25b30 FC |
2058 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
2059 | clocks = <&cpg CPG_MOD 328>; | |
2060 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2061 | resets = <&cpg 328>; | |
2062 | status = "disabled"; | |
9b33e300 BD |
2063 | }; |
2064 | ||
2065 | ohci0: usb@ee080000 { | |
561668aa | 2066 | compatible = "generic-ohci"; |
9b33e300 | 2067 | reg = <0 0xee080000 0 0x100>; |
561668aa FC |
2068 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
2069 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; | |
2070 | phys = <&usb2_phy0 1>; | |
2071 | phy-names = "usb"; | |
2072 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2073 | resets = <&cpg 703>, <&cpg 704>; | |
2074 | status = "disabled"; | |
9b33e300 BD |
2075 | }; |
2076 | ||
2077 | ohci1: usb@ee0a0000 { | |
561668aa | 2078 | compatible = "generic-ohci"; |
9b33e300 | 2079 | reg = <0 0xee0a0000 0 0x100>; |
561668aa FC |
2080 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
2081 | clocks = <&cpg CPG_MOD 702>; | |
2082 | phys = <&usb2_phy1 1>; | |
2083 | phy-names = "usb"; | |
2084 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2085 | resets = <&cpg 702>; | |
2086 | status = "disabled"; | |
9b33e300 BD |
2087 | }; |
2088 | ||
2089 | ehci0: usb@ee080100 { | |
561668aa | 2090 | compatible = "generic-ehci"; |
9b33e300 | 2091 | reg = <0 0xee080100 0 0x100>; |
561668aa FC |
2092 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
2093 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; | |
2094 | phys = <&usb2_phy0 2>; | |
2095 | phy-names = "usb"; | |
2096 | companion = <&ohci0>; | |
2097 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2098 | resets = <&cpg 703>, <&cpg 704>; | |
2099 | status = "disabled"; | |
9b33e300 BD |
2100 | }; |
2101 | ||
2102 | ehci1: usb@ee0a0100 { | |
561668aa | 2103 | compatible = "generic-ehci"; |
9b33e300 | 2104 | reg = <0 0xee0a0100 0 0x100>; |
561668aa FC |
2105 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
2106 | clocks = <&cpg CPG_MOD 702>; | |
2107 | phys = <&usb2_phy1 2>; | |
2108 | phy-names = "usb"; | |
2109 | companion = <&ohci1>; | |
2110 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2111 | resets = <&cpg 702>; | |
2112 | status = "disabled"; | |
9b33e300 BD |
2113 | }; |
2114 | ||
2115 | usb2_phy0: usb-phy@ee080200 { | |
561668aa FC |
2116 | compatible = "renesas,usb2-phy-r8a774b1", |
2117 | "renesas,rcar-gen3-usb2-phy"; | |
9b33e300 | 2118 | reg = <0 0xee080200 0 0x700>; |
561668aa FC |
2119 | interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
2120 | clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>; | |
2121 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2122 | resets = <&cpg 703>, <&cpg 704>; | |
2123 | #phy-cells = <1>; | |
2124 | status = "disabled"; | |
9b33e300 BD |
2125 | }; |
2126 | ||
2127 | usb2_phy1: usb-phy@ee0a0200 { | |
561668aa FC |
2128 | compatible = "renesas,usb2-phy-r8a774b1", |
2129 | "renesas,rcar-gen3-usb2-phy"; | |
9b33e300 | 2130 | reg = <0 0xee0a0200 0 0x700>; |
561668aa FC |
2131 | clocks = <&cpg CPG_MOD 702>; |
2132 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2133 | resets = <&cpg 702>; | |
2134 | #phy-cells = <1>; | |
2135 | status = "disabled"; | |
9b33e300 BD |
2136 | }; |
2137 | ||
a6cb262a | 2138 | sdhi0: mmc@ee100000 { |
63177367 BD |
2139 | compatible = "renesas,sdhi-r8a774b1", |
2140 | "renesas,rcar-gen3-sdhi"; | |
9b33e300 | 2141 | reg = <0 0xee100000 0 0x2000>; |
63177367 | 2142 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
52e844ee WS |
2143 | clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A774B1_CLK_SD0H>; |
2144 | clock-names = "core", "clkh"; | |
63177367 BD |
2145 | max-frequency = <200000000>; |
2146 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2147 | resets = <&cpg 314>; | |
2148 | status = "disabled"; | |
9b33e300 BD |
2149 | }; |
2150 | ||
a6cb262a | 2151 | sdhi1: mmc@ee120000 { |
63177367 BD |
2152 | compatible = "renesas,sdhi-r8a774b1", |
2153 | "renesas,rcar-gen3-sdhi"; | |
9b33e300 | 2154 | reg = <0 0xee120000 0 0x2000>; |
63177367 | 2155 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
52e844ee WS |
2156 | clocks = <&cpg CPG_MOD 313>, <&cpg CPG_CORE R8A774B1_CLK_SD1H>; |
2157 | clock-names = "core", "clkh"; | |
63177367 BD |
2158 | max-frequency = <200000000>; |
2159 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2160 | resets = <&cpg 313>; | |
2161 | status = "disabled"; | |
9b33e300 BD |
2162 | }; |
2163 | ||
a6cb262a | 2164 | sdhi2: mmc@ee140000 { |
63177367 BD |
2165 | compatible = "renesas,sdhi-r8a774b1", |
2166 | "renesas,rcar-gen3-sdhi"; | |
9b33e300 | 2167 | reg = <0 0xee140000 0 0x2000>; |
63177367 | 2168 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
52e844ee WS |
2169 | clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A774B1_CLK_SD2H>; |
2170 | clock-names = "core", "clkh"; | |
63177367 BD |
2171 | max-frequency = <200000000>; |
2172 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2173 | resets = <&cpg 312>; | |
2174 | status = "disabled"; | |
9b33e300 BD |
2175 | }; |
2176 | ||
a6cb262a | 2177 | sdhi3: mmc@ee160000 { |
63177367 BD |
2178 | compatible = "renesas,sdhi-r8a774b1", |
2179 | "renesas,rcar-gen3-sdhi"; | |
9b33e300 | 2180 | reg = <0 0xee160000 0 0x2000>; |
63177367 | 2181 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
52e844ee WS |
2182 | clocks = <&cpg CPG_MOD 311>, <&cpg CPG_CORE R8A774B1_CLK_SD3H>; |
2183 | clock-names = "core", "clkh"; | |
63177367 BD |
2184 | max-frequency = <200000000>; |
2185 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2186 | resets = <&cpg 311>; | |
2187 | status = "disabled"; | |
9b33e300 BD |
2188 | }; |
2189 | ||
8811955d AF |
2190 | rpc: spi@ee200000 { |
2191 | compatible = "renesas,r8a774b1-rpc-if", | |
2192 | "renesas,rcar-gen3-rpc-if"; | |
2193 | reg = <0 0xee200000 0 0x200>, | |
2194 | <0 0x08000000 0 0x4000000>, | |
2195 | <0 0xee208000 0 0x100>; | |
2196 | reg-names = "regs", "dirmap", "wbuf"; | |
2197 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
2198 | clocks = <&cpg CPG_MOD 917>; | |
8811955d AF |
2199 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; |
2200 | resets = <&cpg 917>; | |
2201 | #address-cells = <1>; | |
2202 | #size-cells = <0>; | |
2203 | status = "disabled"; | |
2204 | }; | |
2205 | ||
1510faee FC |
2206 | sata: sata@ee300000 { |
2207 | compatible = "renesas,sata-r8a774b1", | |
2208 | "renesas,rcar-gen3-sata"; | |
2209 | reg = <0 0xee300000 0 0x200000>; | |
2210 | interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
2211 | clocks = <&cpg CPG_MOD 815>; | |
2212 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2213 | resets = <&cpg 815>; | |
2214 | status = "disabled"; | |
2215 | }; | |
2216 | ||
9b33e300 BD |
2217 | gic: interrupt-controller@f1010000 { |
2218 | compatible = "arm,gic-400"; | |
2219 | #interrupt-cells = <3>; | |
2220 | #address-cells = <0>; | |
2221 | interrupt-controller; | |
2222 | reg = <0x0 0xf1010000 0 0x1000>, | |
2223 | <0x0 0xf1020000 0 0x20000>, | |
2224 | <0x0 0xf1040000 0 0x20000>, | |
2225 | <0x0 0xf1060000 0 0x20000>; | |
2226 | interrupts = <GIC_PPI 9 | |
2227 | (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
2228 | clocks = <&cpg CPG_MOD 408>; | |
2229 | clock-names = "clk"; | |
2230 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2231 | resets = <&cpg 408>; | |
2232 | }; | |
2233 | ||
2234 | pciec0: pcie@fe000000 { | |
b3ddadfa FC |
2235 | compatible = "renesas,pcie-r8a774b1", |
2236 | "renesas,pcie-rcar-gen3"; | |
9b33e300 BD |
2237 | reg = <0 0xfe000000 0 0x80000>; |
2238 | #address-cells = <3>; | |
2239 | #size-cells = <2>; | |
2240 | bus-range = <0x00 0xff>; | |
b3ddadfa | 2241 | device_type = "pci"; |
9504a9f2 GU |
2242 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, |
2243 | <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, | |
2244 | <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, | |
2245 | <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
86d904b6 YS |
2246 | /* Map all possible DDR/IOMMU as inbound ranges */ |
2247 | dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; | |
b3ddadfa FC |
2248 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
2249 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
2250 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
2251 | #interrupt-cells = <1>; | |
2252 | interrupt-map-mask = <0 0 0 0>; | |
2253 | interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
2254 | clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; | |
2255 | clock-names = "pcie", "pcie_bus"; | |
2256 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2257 | resets = <&cpg 319>; | |
86d904b6 YS |
2258 | iommu-map = <0 &ipmmu_hc 0 1>; |
2259 | iommu-map-mask = <0>; | |
b3ddadfa | 2260 | status = "disabled"; |
9b33e300 BD |
2261 | }; |
2262 | ||
2263 | pciec1: pcie@ee800000 { | |
b3ddadfa FC |
2264 | compatible = "renesas,pcie-r8a774b1", |
2265 | "renesas,pcie-rcar-gen3"; | |
9b33e300 BD |
2266 | reg = <0 0xee800000 0 0x80000>; |
2267 | #address-cells = <3>; | |
2268 | #size-cells = <2>; | |
2269 | bus-range = <0x00 0xff>; | |
b3ddadfa | 2270 | device_type = "pci"; |
9504a9f2 GU |
2271 | ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, |
2272 | <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, | |
2273 | <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, | |
2274 | <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; | |
86d904b6 YS |
2275 | /* Map all possible DDR/IOMMU as inbound ranges */ |
2276 | dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; | |
b3ddadfa FC |
2277 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, |
2278 | <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
2279 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
2280 | #interrupt-cells = <1>; | |
2281 | interrupt-map-mask = <0 0 0 0>; | |
2282 | interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; | |
2283 | clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; | |
2284 | clock-names = "pcie", "pcie_bus"; | |
2285 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2286 | resets = <&cpg 318>; | |
86d904b6 YS |
2287 | iommu-map = <0 &ipmmu_hc 1 1>; |
2288 | iommu-map-mask = <0>; | |
b3ddadfa | 2289 | status = "disabled"; |
9b33e300 BD |
2290 | }; |
2291 | ||
d12d1620 LP |
2292 | pciec0_ep: pcie-ep@fe000000 { |
2293 | compatible = "renesas,r8a774b1-pcie-ep", | |
2294 | "renesas,rcar-gen3-pcie-ep"; | |
2295 | reg = <0x0 0xfe000000 0 0x80000>, | |
2296 | <0x0 0xfe100000 0 0x100000>, | |
2297 | <0x0 0xfe200000 0 0x200000>, | |
2298 | <0x0 0x30000000 0 0x8000000>, | |
2299 | <0x0 0x38000000 0 0x8000000>; | |
2300 | reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; | |
2301 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
2302 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
2303 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
2304 | clocks = <&cpg CPG_MOD 319>; | |
2305 | clock-names = "pcie"; | |
2306 | resets = <&cpg 319>; | |
2307 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2308 | status = "disabled"; | |
2309 | }; | |
2310 | ||
2311 | pciec1_ep: pcie-ep@ee800000 { | |
2312 | compatible = "renesas,r8a774b1-pcie-ep", | |
2313 | "renesas,rcar-gen3-pcie-ep"; | |
2314 | reg = <0x0 0xee800000 0 0x80000>, | |
2315 | <0x0 0xee900000 0 0x100000>, | |
2316 | <0x0 0xeea00000 0 0x200000>, | |
2317 | <0x0 0xc0000000 0 0x8000000>, | |
2318 | <0x0 0xc8000000 0 0x8000000>; | |
2319 | reg-names = "apb-base", "memory0", "memory1", "memory2", "memory3"; | |
2320 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, | |
2321 | <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, | |
2322 | <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; | |
2323 | clocks = <&cpg CPG_MOD 318>; | |
2324 | clock-names = "pcie"; | |
2325 | resets = <&cpg 318>; | |
2326 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2327 | status = "disabled"; | |
2328 | }; | |
2329 | ||
ab46816a BD |
2330 | fdp1@fe940000 { |
2331 | compatible = "renesas,fdp1"; | |
2332 | reg = <0 0xfe940000 0 0x2400>; | |
2333 | interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; | |
2334 | clocks = <&cpg CPG_MOD 119>; | |
2335 | power-domains = <&sysc R8A774B1_PD_A3VP>; | |
2336 | resets = <&cpg 119>; | |
2337 | renesas,fcp = <&fcpf0>; | |
2338 | }; | |
2339 | ||
955ceb56 BD |
2340 | fcpf0: fcp@fe950000 { |
2341 | compatible = "renesas,fcpf"; | |
2342 | reg = <0 0xfe950000 0 0x200>; | |
2343 | clocks = <&cpg CPG_MOD 615>; | |
2344 | power-domains = <&sysc R8A774B1_PD_A3VP>; | |
2345 | resets = <&cpg 615>; | |
2346 | }; | |
2347 | ||
966607b8 BD |
2348 | vspb: vsp@fe960000 { |
2349 | compatible = "renesas,vsp2"; | |
2350 | reg = <0 0xfe960000 0 0x8000>; | |
2351 | interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; | |
2352 | clocks = <&cpg CPG_MOD 626>; | |
2353 | power-domains = <&sysc R8A774B1_PD_A3VP>; | |
2354 | resets = <&cpg 626>; | |
2355 | ||
2356 | renesas,fcp = <&fcpvb0>; | |
2357 | }; | |
2358 | ||
2359 | vspi0: vsp@fe9a0000 { | |
2360 | compatible = "renesas,vsp2"; | |
2361 | reg = <0 0xfe9a0000 0 0x8000>; | |
2362 | interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>; | |
2363 | clocks = <&cpg CPG_MOD 631>; | |
2364 | power-domains = <&sysc R8A774B1_PD_A3VP>; | |
2365 | resets = <&cpg 631>; | |
2366 | ||
2367 | renesas,fcp = <&fcpvi0>; | |
2368 | }; | |
2369 | ||
2370 | vspd0: vsp@fea20000 { | |
2371 | compatible = "renesas,vsp2"; | |
2372 | reg = <0 0xfea20000 0 0x5000>; | |
2373 | interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; | |
2374 | clocks = <&cpg CPG_MOD 623>; | |
2375 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2376 | resets = <&cpg 623>; | |
2377 | ||
2378 | renesas,fcp = <&fcpvd0>; | |
2379 | }; | |
2380 | ||
2381 | vspd1: vsp@fea28000 { | |
2382 | compatible = "renesas,vsp2"; | |
2383 | reg = <0 0xfea28000 0 0x5000>; | |
2384 | interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; | |
2385 | clocks = <&cpg CPG_MOD 622>; | |
2386 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2387 | resets = <&cpg 622>; | |
2388 | ||
2389 | renesas,fcp = <&fcpvd1>; | |
2390 | }; | |
2391 | ||
955ceb56 BD |
2392 | fcpvb0: fcp@fe96f000 { |
2393 | compatible = "renesas,fcpv"; | |
2394 | reg = <0 0xfe96f000 0 0x200>; | |
2395 | clocks = <&cpg CPG_MOD 607>; | |
2396 | power-domains = <&sysc R8A774B1_PD_A3VP>; | |
2397 | resets = <&cpg 607>; | |
2398 | }; | |
2399 | ||
2400 | fcpvd0: fcp@fea27000 { | |
2401 | compatible = "renesas,fcpv"; | |
2402 | reg = <0 0xfea27000 0 0x200>; | |
2403 | clocks = <&cpg CPG_MOD 603>; | |
2404 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2405 | resets = <&cpg 603>; | |
2406 | }; | |
2407 | ||
2408 | fcpvd1: fcp@fea2f000 { | |
2409 | compatible = "renesas,fcpv"; | |
2410 | reg = <0 0xfea2f000 0 0x200>; | |
2411 | clocks = <&cpg CPG_MOD 602>; | |
2412 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2413 | resets = <&cpg 602>; | |
2414 | }; | |
2415 | ||
2416 | fcpvi0: fcp@fe9af000 { | |
2417 | compatible = "renesas,fcpv"; | |
2418 | reg = <0 0xfe9af000 0 0x200>; | |
2419 | clocks = <&cpg CPG_MOD 611>; | |
2420 | power-domains = <&sysc R8A774B1_PD_A3VP>; | |
2421 | resets = <&cpg 611>; | |
2422 | }; | |
2423 | ||
bf216639 BD |
2424 | csi20: csi2@fea80000 { |
2425 | compatible = "renesas,r8a774b1-csi2"; | |
2426 | reg = <0 0xfea80000 0 0x10000>; | |
2427 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; | |
2428 | clocks = <&cpg CPG_MOD 714>; | |
2429 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2430 | resets = <&cpg 714>; | |
2431 | status = "disabled"; | |
2432 | ||
2433 | ports { | |
2434 | #address-cells = <1>; | |
2435 | #size-cells = <0>; | |
2436 | ||
0a96c059 NS |
2437 | port@0 { |
2438 | reg = <0>; | |
2439 | }; | |
2440 | ||
bf216639 BD |
2441 | port@1 { |
2442 | #address-cells = <1>; | |
2443 | #size-cells = <0>; | |
2444 | ||
2445 | reg = <1>; | |
2446 | ||
2447 | csi20vin0: endpoint@0 { | |
2448 | reg = <0>; | |
2449 | remote-endpoint = <&vin0csi20>; | |
2450 | }; | |
2451 | csi20vin1: endpoint@1 { | |
2452 | reg = <1>; | |
2453 | remote-endpoint = <&vin1csi20>; | |
2454 | }; | |
2455 | csi20vin2: endpoint@2 { | |
2456 | reg = <2>; | |
2457 | remote-endpoint = <&vin2csi20>; | |
2458 | }; | |
2459 | csi20vin3: endpoint@3 { | |
2460 | reg = <3>; | |
2461 | remote-endpoint = <&vin3csi20>; | |
2462 | }; | |
2463 | csi20vin4: endpoint@4 { | |
2464 | reg = <4>; | |
2465 | remote-endpoint = <&vin4csi20>; | |
2466 | }; | |
2467 | csi20vin5: endpoint@5 { | |
2468 | reg = <5>; | |
2469 | remote-endpoint = <&vin5csi20>; | |
2470 | }; | |
2471 | csi20vin6: endpoint@6 { | |
2472 | reg = <6>; | |
2473 | remote-endpoint = <&vin6csi20>; | |
2474 | }; | |
2475 | csi20vin7: endpoint@7 { | |
2476 | reg = <7>; | |
2477 | remote-endpoint = <&vin7csi20>; | |
2478 | }; | |
2479 | }; | |
2480 | }; | |
2481 | }; | |
2482 | ||
2483 | csi40: csi2@feaa0000 { | |
2484 | compatible = "renesas,r8a774b1-csi2"; | |
2485 | reg = <0 0xfeaa0000 0 0x10000>; | |
2486 | interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; | |
2487 | clocks = <&cpg CPG_MOD 716>; | |
2488 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2489 | resets = <&cpg 716>; | |
2490 | status = "disabled"; | |
2491 | ||
2492 | ports { | |
2493 | #address-cells = <1>; | |
2494 | #size-cells = <0>; | |
2495 | ||
0a96c059 NS |
2496 | port@0 { |
2497 | reg = <0>; | |
2498 | }; | |
2499 | ||
bf216639 BD |
2500 | port@1 { |
2501 | #address-cells = <1>; | |
2502 | #size-cells = <0>; | |
2503 | ||
2504 | reg = <1>; | |
2505 | ||
2506 | csi40vin0: endpoint@0 { | |
2507 | reg = <0>; | |
2508 | remote-endpoint = <&vin0csi40>; | |
2509 | }; | |
2510 | csi40vin1: endpoint@1 { | |
2511 | reg = <1>; | |
2512 | remote-endpoint = <&vin1csi40>; | |
2513 | }; | |
2514 | csi40vin2: endpoint@2 { | |
2515 | reg = <2>; | |
2516 | remote-endpoint = <&vin2csi40>; | |
2517 | }; | |
2518 | csi40vin3: endpoint@3 { | |
2519 | reg = <3>; | |
2520 | remote-endpoint = <&vin3csi40>; | |
2521 | }; | |
2522 | csi40vin4: endpoint@4 { | |
2523 | reg = <4>; | |
2524 | remote-endpoint = <&vin4csi40>; | |
2525 | }; | |
2526 | csi40vin5: endpoint@5 { | |
2527 | reg = <5>; | |
2528 | remote-endpoint = <&vin5csi40>; | |
2529 | }; | |
2530 | csi40vin6: endpoint@6 { | |
2531 | reg = <6>; | |
2532 | remote-endpoint = <&vin6csi40>; | |
2533 | }; | |
2534 | csi40vin7: endpoint@7 { | |
2535 | reg = <7>; | |
2536 | remote-endpoint = <&vin7csi40>; | |
2537 | }; | |
2538 | }; | |
2539 | }; | |
2540 | }; | |
2541 | ||
9b33e300 | 2542 | hdmi0: hdmi@fead0000 { |
3a02555a BD |
2543 | compatible = "renesas,r8a774b1-hdmi", |
2544 | "renesas,rcar-gen3-hdmi"; | |
9b33e300 | 2545 | reg = <0 0xfead0000 0 0x10000>; |
3a02555a BD |
2546 | interrupts = <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>; |
2547 | clocks = <&cpg CPG_MOD 729>, | |
2548 | <&cpg CPG_CORE R8A774B1_CLK_HDMI>; | |
2549 | clock-names = "iahb", "isfr"; | |
2550 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2551 | resets = <&cpg 729>; | |
2552 | status = "disabled"; | |
9b33e300 BD |
2553 | |
2554 | ports { | |
2555 | #address-cells = <1>; | |
2556 | #size-cells = <0>; | |
2557 | ||
2558 | port@0 { | |
2559 | reg = <0>; | |
2560 | dw_hdmi0_in: endpoint { | |
3a02555a | 2561 | remote-endpoint = <&du_out_hdmi0>; |
9b33e300 BD |
2562 | }; |
2563 | }; | |
2564 | port@1 { | |
2565 | reg = <1>; | |
2566 | }; | |
3a02555a BD |
2567 | port@2 { |
2568 | /* HDMI sound */ | |
2569 | reg = <2>; | |
2570 | }; | |
9b33e300 BD |
2571 | }; |
2572 | }; | |
2573 | ||
2574 | du: display@feb00000 { | |
04e4bad3 | 2575 | compatible = "renesas,du-r8a774b1"; |
9b33e300 | 2576 | reg = <0 0xfeb00000 0 0x80000>; |
04e4bad3 BD |
2577 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
2578 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, | |
2579 | <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>; | |
721b7619 | 2580 | clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>, |
04e4bad3 BD |
2581 | <&cpg CPG_MOD 721>; |
2582 | clock-names = "du.0", "du.1", "du.3"; | |
721b7619 GU |
2583 | resets = <&cpg 724>, <&cpg 722>; |
2584 | reset-names = "du.0", "du.3"; | |
04e4bad3 BD |
2585 | status = "disabled"; |
2586 | ||
03abfdd3 | 2587 | renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>; |
9b33e300 BD |
2588 | |
2589 | ports { | |
2590 | #address-cells = <1>; | |
2591 | #size-cells = <0>; | |
2592 | ||
2593 | port@0 { | |
2594 | reg = <0>; | |
9b33e300 BD |
2595 | }; |
2596 | port@1 { | |
2597 | reg = <1>; | |
2598 | du_out_hdmi0: endpoint { | |
3a02555a | 2599 | remote-endpoint = <&dw_hdmi0_in>; |
9b33e300 BD |
2600 | }; |
2601 | }; | |
2602 | port@2 { | |
2603 | reg = <2>; | |
2604 | du_out_lvds0: endpoint { | |
04e4bad3 BD |
2605 | remote-endpoint = <&lvds0_in>; |
2606 | }; | |
2607 | }; | |
2608 | }; | |
2609 | }; | |
2610 | ||
2611 | lvds0: lvds@feb90000 { | |
2612 | compatible = "renesas,r8a774b1-lvds"; | |
2613 | reg = <0 0xfeb90000 0 0x14>; | |
2614 | clocks = <&cpg CPG_MOD 727>; | |
2615 | power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>; | |
2616 | resets = <&cpg 727>; | |
2617 | status = "disabled"; | |
2618 | ||
2619 | ports { | |
2620 | #address-cells = <1>; | |
2621 | #size-cells = <0>; | |
2622 | ||
2623 | port@0 { | |
2624 | reg = <0>; | |
2625 | lvds0_in: endpoint { | |
2626 | remote-endpoint = <&du_out_lvds0>; | |
2627 | }; | |
2628 | }; | |
2629 | port@1 { | |
2630 | reg = <1>; | |
9b33e300 BD |
2631 | }; |
2632 | }; | |
2633 | }; | |
2634 | ||
2635 | prr: chipid@fff00044 { | |
2636 | compatible = "renesas,prr"; | |
2637 | reg = <0 0xfff00044 0 4>; | |
2638 | }; | |
2639 | }; | |
2640 | ||
95b3547f | 2641 | thermal-zones { |
82ce7939 | 2642 | sensor1_thermal: sensor1-thermal { |
95b3547f BD |
2643 | polling-delay-passive = <250>; |
2644 | polling-delay = <1000>; | |
2645 | thermal-sensors = <&tsc 0>; | |
2646 | sustainable-power = <2439>; | |
2647 | ||
2648 | trips { | |
2649 | sensor1_crit: sensor1-crit { | |
2650 | temperature = <120000>; | |
2651 | hysteresis = <1000>; | |
2652 | type = "critical"; | |
2653 | }; | |
2654 | }; | |
2655 | }; | |
2656 | ||
82ce7939 | 2657 | sensor2_thermal: sensor2-thermal { |
95b3547f BD |
2658 | polling-delay-passive = <250>; |
2659 | polling-delay = <1000>; | |
2660 | thermal-sensors = <&tsc 1>; | |
2661 | sustainable-power = <2439>; | |
2662 | ||
2663 | trips { | |
2664 | sensor2_crit: sensor2-crit { | |
2665 | temperature = <120000>; | |
2666 | hysteresis = <1000>; | |
2667 | type = "critical"; | |
2668 | }; | |
2669 | }; | |
2670 | }; | |
2671 | ||
82ce7939 | 2672 | sensor3_thermal: sensor3-thermal { |
95b3547f BD |
2673 | polling-delay-passive = <250>; |
2674 | polling-delay = <1000>; | |
2675 | thermal-sensors = <&tsc 2>; | |
2676 | sustainable-power = <2439>; | |
2677 | ||
2678 | cooling-maps { | |
2679 | map0 { | |
2680 | trip = <&target>; | |
2681 | cooling-device = <&a57_0 0 2>; | |
2682 | contribution = <1024>; | |
2683 | }; | |
2684 | }; | |
2685 | trips { | |
2686 | target: trip-point1 { | |
2687 | temperature = <100000>; | |
2688 | hysteresis = <1000>; | |
2689 | type = "passive"; | |
2690 | }; | |
2691 | ||
2692 | sensor3_crit: sensor3-crit { | |
2693 | temperature = <120000>; | |
2694 | hysteresis = <1000>; | |
2695 | type = "critical"; | |
2696 | }; | |
2697 | }; | |
2698 | }; | |
2699 | }; | |
2700 | ||
9b33e300 BD |
2701 | timer { |
2702 | compatible = "arm,armv8-timer"; | |
2703 | interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
2704 | <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
2705 | <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
2706 | <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
2707 | }; | |
2708 | ||
2709 | /* External USB clocks - can be overridden by the board */ | |
2710 | usb3s0_clk: usb3s0 { | |
2711 | compatible = "fixed-clock"; | |
2712 | #clock-cells = <0>; | |
2713 | clock-frequency = <0>; | |
2714 | }; | |
2715 | ||
2716 | usb_extal_clk: usb_extal { | |
2717 | compatible = "fixed-clock"; | |
2718 | #clock-cells = <0>; | |
2719 | clock-frequency = <0>; | |
2720 | }; | |
2721 | }; |